JPS63158871A - Optoelectronic integrated circuit - Google Patents
Optoelectronic integrated circuitInfo
- Publication number
- JPS63158871A JPS63158871A JP61307032A JP30703286A JPS63158871A JP S63158871 A JPS63158871 A JP S63158871A JP 61307032 A JP61307032 A JP 61307032A JP 30703286 A JP30703286 A JP 30703286A JP S63158871 A JPS63158871 A JP S63158871A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inp
- level shift
- etched
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005693 optoelectronics Effects 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000003287 optical effect Effects 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000031700 light absorption Effects 0.000 claims description 2
- 238000010521 absorption reaction Methods 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical group [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000623 nickel–chromium alloy Inorganic materials 0.000 description 1
- 235000011007 phosphoric acid Nutrition 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、超高速・大容量な光通信・光情報処理シス
テムの主構成要素となる光・電子集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optical/electronic integrated circuit that is a main component of an ultra-high-speed, large-capacity optical communication/optical information processing system.
光ファイバを伝送路とする光通信システムは、高速・大
容量の信号伝送が可能であり、半導体レーザ、アバラン
シェホトダイオード、ＰＩＮホトダイオード等の個別光
部品の組立によって、数百メガビット／Ｓの伝送容量の
システムが実用化されている。さらに、超高速、高信頼
、低価格な光通信システムの実現のため、半導体レーザ
あるいはＰＩＮホトダイオード等の光素子とトランジス
タ等の電子素子を同一基板上に集積する試みが活発に進
められている。ＰＩＮホトダイオード。Optical communication systems using optical fibers as transmission paths are capable of high-speed, large-capacity signal transmission, and can achieve transmission capacities of several hundred megabits/s by assembling individual optical components such as semiconductor lasers, avalanche photodiodes, and PIN photodiodes. The system has been put into practical use. Furthermore, in order to realize ultra-high-speed, highly reliable, and low-cost optical communication systems, attempts are being made to integrate optical elements such as semiconductor lasers or PIN photodiodes and electronic elements such as transistors on the same substrate. PIN photodiode.
トランジスタの他、抵抗、レベルシフト・ダイオード等
を同一基板上に形成し回路集積を行なうことにより動作
電源数を少なくできる。したがって、周辺回路なしで動
作できる超高速、高信頼。By forming not only transistors but also resistors, level shift diodes, etc. on the same substrate and performing circuit integration, the number of operating power supplies can be reduced. Therefore, it can operate without any peripheral circuits and is extremely fast and reliable.
低価格が可能な受光用の光・電子集積回路が実現できる
。第２図にその１例の回路図を示す。このような光・電
子集積回路を実現するためには寄生抵抗、寄生容量の小
さいレベルシフト・ダイオードの開発が鍵となる。従来
からはＧａＡｓ／ＧａＡ／ Ａｓを主材料とする系にお
いて、ｎ型ＧａＡｓ上にアルミニウムによるショットキ
ー電極を形成することにより、レベルシフト・ダイオー
ドを作る方法が知られていた。このような例は、アイイ
ーイーイー・エレクトロン・デバイスイズ・レターズ誌
（ＪＥＥＲＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥＳ ＬＨＴ
ＴＥＲ５）、第６巻、第１２号、１９８５年、第６３４
〜６３５頁に記載されている。A low-cost optical/electronic integrated circuit for light reception can be realized. FIG. 2 shows a circuit diagram of one example. The key to realizing such opto-electronic integrated circuits is the development of level shift diodes with low parasitic resistance and capacitance. Conventionally, a method has been known in which a level shift diode is fabricated by forming an aluminum Schottky electrode on n-type GaAs in a system mainly made of GaAs/GaA/As. An example of this is the JEERELECTRON DEVICES LHT magazine.
TER5), Volume 6, No. 12, 1985, No. 634
It is described on pages 635 to 635.
従来はＧａＡｓ／ＧａＡｆ Ａｓを主材料とするもので
あるため、ショットキー電極によるレベルシフト・ダイ
オードの形成が容易である。一方、光フアイバ通信に有
利な波長１μｍ帯のＩｎＰ／ＩｎＧａＡｓＰを主材料と
する系においては、ショットキー電極によるレベルシフ
ト・ダイオードの形成が難しい。この材料系でレベルシ
フト・ダイオードを作る場合、ＰＩＮホトダイオードの
ＰＮ接合を利用する方法、又接合型電界効果トランジス
タのＰＮ接合を利用する方法が検討されている。しかし
、前者はレベルシフト電圧が０．６■程度と小さく、後
者は薄層構造のため、寄生抵抗が大きいという欠点を有
していた。Conventionally, since the main material is GaAs/GaAf As, it is easy to form a level shift diode using a Schottky electrode. On the other hand, in a system mainly made of InP/InGaAsP with a wavelength band of 1 μm, which is advantageous for optical fiber communication, it is difficult to form a level shift diode using a Schottky electrode. When making a level shift diode using this material system, methods of using the PN junction of a PIN photodiode and methods of using the PN junction of a junction field effect transistor are being considered. However, the former has a low level shift voltage of about 0.6 square meters, and the latter has a thin layer structure, so it has a large parasitic resistance.
本発明の目的は、これらの問題点を解決し、レベルシフ
ト電圧の大きなレベルシフト・ダイオ−ドを実現し、周
辺回路なしで動作可能な超高速。The purpose of the present invention is to solve these problems, to realize a level shift diode with a large level shift voltage, and to achieve ultra-high speed operation without any peripheral circuitry.
高信頼、低価格な受光用の光・電子集積回路を提供する
ことにある。Our objective is to provide highly reliable, low-cost optical/electronic integrated circuits for light reception.
〔問題点を解決するための手段〕 ・
本発明の光・電子集積回路は、半絶縁性半導体基板上に
、ＩｎＰからなるコンタクト層及びＩｎＰより禁制帯幅
の狭い半導体からなる光吸収層を順次積層して形成した
ホトダイオードと、トランジスタ及びレベルシフト・ダ
イオードを含んで構成され前記ホトダイオードの出力信
号を増幅する増幅回路とを集積してなる光・電子集積回
路において、前記レベルシフト・ダイオードは前記コン
タクト層と同時に成長されたＩｎＰ層に形成されたＰＮ
接合を有してなるものである。[Means for Solving the Problems] - The opto-electronic integrated circuit of the present invention includes a contact layer made of InP and a light absorption layer made of a semiconductor whose forbidden band width is narrower than that of InP, which are sequentially formed on a semi-insulating semiconductor substrate. In an opto-electronic integrated circuit that integrates a stacked photodiode and an amplifier circuit that includes a transistor and a level shift diode and amplifies the output signal of the photodiode, the level shift diode is connected to the contact. PN formed on an InP layer grown simultaneously with the
It has a bond.
ＰＩＮフォトダイオードのＩｏＰからなるコック１一層
に選択的に不純物拡散層を設けて得られるＰＮ接合を利
用することによって、約１．２■の大きなレベルシフト
電圧を有する寄生抵抗の小さなレベルシフト・ダイオー
ドが得られる。By utilizing a PN junction obtained by selectively providing an impurity diffusion layer in the cock 1 layer made of the IoP of a PIN photodiode, a level shift diode with a small parasitic resistance and a large level shift voltage of about 1.2μ is created. is obtained.
ｒ実施例〕
次に、本発明の実施例について図面を参照して説明する
。Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の主要部を示す半導体チップ
の断面図である。本実施例では３μｍの段差をつけたＦ
ｅドープの半絶縁性１ｎＰ基板１０上に液相もしくは気
相成長法によってｎ −１ｎＰからなるチャネル層１１
（厚さ０．２μｍ、キャリア濃度Ｉ Ｘ １０ ”Ｃ１
１−’） 、 ｐＩｎｎ−ｓＩＧａｏ、ｔｑＡｓｏ、４
、ＰＯ−５９からなるＦＥＴ層１２（厚さ０．４μｍ。FIG. 1 is a sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention. In this example, an F with a step of 3 μm is used.
A channel layer 11 made of n −1 nP is formed on an e-doped semi-insulating 1 nP substrate 10 by liquid phase or vapor phase growth.
(Thickness 0.2 μm, carrier concentration I
1-'), pInn-sIGao, tqAso, 4
, PO-59 (thickness: 0.4 μm).
キャリア濃度５ Ｘ １０１８Ｃ１１−’） 、ｎ −
１ｎＰからなるコンタクト層１３（厚さ１μｍ、キャリ
ア濃度１ ｘ’ｉ ０ ”Ｃ１１−’） 、ｎ Ｉｎ
、）、４７Ｇａ（、，５３Ａｓからなる吸収層１４（厚
さ２μｍ、キャリア濃度１×１０１６Ｃ１ｌ−’） 、
ｎ −１ｏＰからなるウィンドウ層１５（厚さ９．５μ
ｍ、キャリア濃度” ×１０１７ｅ１ｍ−’）を順次成
長させる。次に、通常のホトリソグラフィー技術及びエ
ツチング技術によりＰＩＮホトダイオード１となる領域
以外のウィンドウ層１５、吸収層１４を順次エツチング
する。さらにウェーハ全面にＳｉＯ□をＣＶＤ法により
堆積させ、ホトリソグラフィー技術及びＺｎ拡散法を用
いて、選択的にＺｏ拡散を行ないＰＩＮフォトダイオー
ドのＰ膨面転領域１６、レベルシフト・ダイオードのＰ
膨面転領域１７を形成する０次に、さらにＰＩＮフォト
ダイオード１及びレベルシフト・ダイオード２となる領
域以外のｎ −１ｏＰからなるコンタクト層１３をエツ
チングする。Carrier concentration 5 x 1018C11-'), n-
Contact layer 13 made of 1 nP (thickness 1 μm, carrier concentration 1 x'i 0 "C11-'), n In
, ), 47Ga(, , 53As absorption layer 14 (thickness 2 μm, carrier concentration 1×10 16 C1l-'),
Window layer 15 (thickness 9.5 μm) consisting of n −1oP
m, carrier concentration "x1017e1m-'). Next, the window layer 15 and absorption layer 14 other than the region that will become the PIN photodiode 1 are sequentially etched using normal photolithography and etching techniques. Furthermore, the entire surface of the wafer is etched. SiO□ is deposited by the CVD method, and Zo is selectively diffused using the photolithography technique and the Zn diffusion method to form the P expansion region 16 of the PIN photodiode and the P of the level shift diode.
After forming the dilatation area 17, the contact layer 13 made of n-1oP is further etched in areas other than the areas that will become the PIN photodiode 1 and the level shift diode 2.
次に、ＰＩＮホ１〜ダイオード１及びレベルシフト・ダ
イオード２、接合型電界効果トランジスタ４となる領域
以外のｐ −ＩｎＧａＡｓＰからなるＦＥＴ層１２、ｎ
−１ｎＰからなるチャネル層１１及び半絶縁性１ｎＰ
基板１０を順次エツチングする。この場合、ＩｎＧａＡ
ｓからなる吸収層１４、ＩｎＧａＡｓＰからなるＦＥＴ
層１２は、Ｈ２ＳＯ４、８２０２及びＨ２Ｏの混合液で
除去され、ＩｎＰ組成である１ウィンドウ層１５、コン
タクト層１３．チャネル層１１．基板１０はＨＣｊ’
、Ｈ３ＰＯ４の混合液によって除去される。Next, the FET layer 12 made of p-InGaAsP, n
- Channel layer 11 made of 1nP and semi-insulating 1nP
The substrate 10 is sequentially etched. In this case, InGaA
Absorption layer 14 made of S, FET made of InGaAsP
Layer 12 is removed with a mixture of H2SO4, 8202 and H2O to form one window layer 15 of InP composition, contact layer 13. Channel layer 11. The board 10 is HCj'
, H3PO4.
次に、ホトリソグラフィ技術及びクロム及び金の蒸着に
よりＰＩＮホトダイオード１のｎ側電極１８、レベルシ
フト・ダイオード２のｎ側電極１９、接合型電界効果ト
ランジスタ４のｐ １！ｌ電極２０を形成する。次に、
接合型電界効果トランジスタ４のＦＥＴ層１２をエツチ
ングする。このときＦＥＴ層１２は、サイドエツチング
によってｎ側電極２０の下までエツチングされ、ひさし
２１を形成する。次に、ホトリソグラフィー及び金。Next, by photolithography technique and vapor deposition of chromium and gold, the n-side electrode 18 of the PIN photodiode 1, the n-side electrode 19 of the level shift diode 2, and the p1! of the junction field effect transistor 4 are removed. 1 electrode 20 is formed. next,
The FET layer 12 of the junction field effect transistor 4 is etched. At this time, the FET layer 12 is etched to below the n-side electrode 20 by side etching to form the eaves 21. Next, photolithography and gold.
ゲルマニウム、ニッケルの蒸着によりＰＩＮフォトダイ
オードのｎ側電極２２レベルシフト・ダイオード２のｎ
側電極２３．接合型電界効果トランジスタ４のｎ１ｌｌ
電極２４を形成する。（なお、接合型電界効果トランジ
スタ４の製造法については、１９８６年、秋季、第４７
回、応用物理学会学術講演会予稿集、２８ｐ−ｘ−１に
詳しい記載がある。）
熱処理後、抵抗３をホトリソグラフィー技術及びニッケ
ル・クロム合金の蒸着によって形成し、５ｉ０２膜２５
をＣＶＤ法により全面に付着させた後、ホトリソグラフ
ィー技術及び金の蒸着により電気配線層を形成し、第２
図にその等価回路を示した光・電子集積回路ができあが
る。The n-side electrode 22 of the PIN photodiode is formed by vapor deposition of germanium and nickel.
Side electrode 23. n1ll of junction field effect transistor 4
Electrodes 24 are formed. (For the manufacturing method of the junction field effect transistor 4, please refer to the 47th publication, Autumn 1986.
A detailed description can be found in the Proceedings of the 2011 Academic Conference of the Japan Society of Applied Physics, 28p-x-1. ) After heat treatment, a resistor 3 is formed by photolithography technique and evaporation of nickel-chromium alloy, and a 5i02 film 25 is formed.
After depositing on the entire surface by CVD method, an electrical wiring layer is formed by photolithography technology and gold vapor deposition, and the second
The optical/electronic integrated circuit whose equivalent circuit is shown in the figure is completed.
この様に、受光用の光・電子集積回路において、ＰＩＮ
フォトダイオード１のコンタクト層１３に不純物拡散を
行ないＰＮ接合を形成することにより、１．２ Ｖとい
う大きなレベルシフト電圧を有し、寄生抵抗の小さいダ
イオードの形成が可能となる。したがって、同一基板上
にＰＩＮホトダイオード、トランジスタ、抵抗及びこの
レベルシフト・ダイオードを集積することによって波長
１μｍ帯の超高速、高信頼、低価格な受光用の光・電子
集積回路が実現できる。In this way, in optical/electronic integrated circuits for light reception, PIN
By diffusing impurities into the contact layer 13 of the photodiode 1 to form a PN junction, it is possible to form a diode with a large level shift voltage of 1.2 V and a small parasitic resistance. Therefore, by integrating a PIN photodiode, a transistor, a resistor, and this level shift diode on the same substrate, an ultra-high-speed, highly reliable, and low-cost optoelectronic integrated circuit for light reception in the 1 μm wavelength band can be realized.
上述の実施例において寸法例も示したが、結晶成長の様
子は、成長法１条件等で大幅に変わるのでそれらととも
に適切な寸法を採用すべきことはいうまでもない。また
電極金属、抵抗配線金属の種類に関しても制限はない。Examples of dimensions were also shown in the above-mentioned embodiments, but since the state of crystal growth varies greatly depending on the conditions of the growth method, etc., it goes without saying that appropriate dimensions should be adopted along with these. Furthermore, there are no restrictions on the types of electrode metals and resistance wiring metals.
以上詳述した様に本発明によれば、受光用の光・電子集
積回路において、ＰＩＮホトダイオードのコンタクト層
に不純物拡散を行ないＰＮ接合を形成することにより大
きなレベルシフＩ・電圧を有し、寄生抵抗の小さなレベ
ルシフト・ダイオードをつくることが可能となる。した
がって、同一基板上にＰＩＮホトダイオード、トランジ
スタ、抵抗及びこのレベルシフト・ダイオードを集積す
ることによって波長１μｍ帯の超高速、高信頼、低価格
な受光用の光・電子集積回路が実現できる。As described in detail above, according to the present invention, in an opto-electronic integrated circuit for light reception, impurity diffusion is performed in the contact layer of a PIN photodiode to form a PN junction, thereby achieving a large level shift I/voltage and reducing parasitic resistance. This makes it possible to create small level shift diodes. Therefore, by integrating a PIN photodiode, a transistor, a resistor, and this level shift diode on the same substrate, an ultra-high-speed, highly reliable, and low-cost optoelectronic integrated circuit for light reception in the 1 μm wavelength band can be realized.
第１図は本発明の一実施例の主要部を示す半導体チップ
の断面図、第２図は光・電子集積回路の一例を示す回路
図である。
１・・・ＰＩＮホトダイオード、２・・・レベルシフト
・ダイオード、３・・・抵抗、４・・・接合型電界効果
トランジスタ、１０・・・半絶縁性１ｎＰ基板、１１・
・・チャネル層、１２・・・ＦＥＴ層、１３・・・コン
タクト層、１４・・・吸収層、１５・・・ウィンドウ層
、１６・・・ＰＩＮホトダイオードのｐ膨面転領域、１
７・・・レベルシフト・ダイオードのｐ膨面転領域、１
８・・・ＰＩＮホトダイオードのＰ側電極、１９・・・
レベルシフト・ダイオードのｐ（！ｌ電極、２０・・・
接合型電界効果トランジスタのｐ側電極、２１・・・ひ
さし、２２・・・ＰＩＮホトダイオードのｎ側電極、２
３・・・レベルシフト・ダイオードのｎ側電極、２４・
・・接合型電界効果トランジスタのｎ側電極、２５・・
・５ｉ０２膜。FIG. 1 is a sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of an opto-electronic integrated circuit. DESCRIPTION OF SYMBOLS 1... PIN photodiode, 2... Level shift diode, 3... Resistor, 4... Junction field effect transistor, 10... Semi-insulating 1nP substrate, 11...
. . . Channel layer, 12 . . . FET layer, 13 . . . Contact layer, 14 .
7... p expansion area of level shift diode, 1
8... P-side electrode of PIN photodiode, 19...
Level shift diode p(!l electrode, 20...
P-side electrode of junction field effect transistor, 21... Eaves, 22... N-side electrode of PIN photodiode, 2
3... n-side electrode of level shift diode, 24.
...N-side electrode of junction field effect transistor, 25...
・5i02 membrane.
Claims (1)
及びＩｎＰより禁制帯幅の狭い半導体からなる光吸収層
を順次積層して形成したホトダイオードと、トランジス
タ及びレベルシフト・ダイオードを含んで構成され前記
ホトダイオードの出力信号を増幅する増幅回路とを集積
してなる光・電子集積回路において、前記レベルシフト
・ダイオードは前記コンタクト層と同時に成長されたＩ
ｎＰ層に形成されたＰＮ接合を有してなることを特徴と
する光・電子集積回路。A photodiode formed by sequentially stacking a contact layer made of InP and a light absorption layer made of a semiconductor having a narrower bandgap than InP on a semi-insulating semiconductor substrate, and a transistor and a level shift diode. In the opto-electronic integrated circuit which is formed by integrating an amplifier circuit for amplifying the output signal of
An optical/electronic integrated circuit characterized by having a PN junction formed in an nP layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61307032A JPS63158871A (en) | 1986-12-22 | 1986-12-22 | Optoelectronic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61307032A JPS63158871A (en) | 1986-12-22 | 1986-12-22 | Optoelectronic integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63158871A true JPS63158871A (en) | 1988-07-01 |
Family
ID=17964213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61307032A Pending JPS63158871A (en) | 1986-12-22 | 1986-12-22 | Optoelectronic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63158871A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399884A (en) * | 1993-11-10 | 1995-03-21 | General Electric Company | Radiation imager with single passivation dielectric for transistor and diode |
| CN104992953A (en) * | 2015-07-13 | 2015-10-21 | 成都嘉石科技有限公司 | GaAs-based optoelectronic integrated device and preparation method thereof |
-
1986
- 1986-12-22 JP JP61307032A patent/JPS63158871A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399884A (en) * | 1993-11-10 | 1995-03-21 | General Electric Company | Radiation imager with single passivation dielectric for transistor and diode |
| US5516712A (en) * | 1993-11-10 | 1996-05-14 | General Electric Company | Method of fabricating radiation imager with single passivation dielectric for transistor and diode |
| CN104992953A (en) * | 2015-07-13 | 2015-10-21 | 成都嘉石科技有限公司 | GaAs-based optoelectronic integrated device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4625225A (en) | Integrated light detection or generation means and amplifying means | |
| JPH0212968A (en) | Integrated multilayer quantum well photon and electron device | |
| US5061977A (en) | Semiconductor photodetector device | |
| JPS62188385A (en) | Semiconductor light-emitting element | |
| JPS63158871A (en) | Optoelectronic integrated circuit | |
| JPH0582829A (en) | Semiconductor light receiving element | |
| JPS63174361A (en) | Opto-electronic integrated circuit | |
| JPH02199877A (en) | Optical receiver and photoelectric integrated circuit | |
| KR100249785B1 (en) | Semiconductor device integrating heterojunction bipolar transistor and lateral pin photo-diode and its fabricating method | |
| EP0388161B1 (en) | Semiconductor device having pin photodiodes | |
| JP2626149B2 (en) | Optoelectronic integrated circuit manufacturing method | |
| JPH01175776A (en) | Semiconductor photodetector | |
| JPS6126278A (en) | Photoelectronic ic | |
| JP2570424B2 (en) | Semiconductor light receiving element | |
| JPH01196182A (en) | Photodiode | |
| JPH0316275A (en) | Manufacture of semiconductor photodetector | |
| JPH01226173A (en) | Manufacture of optoelectronic integrated circuit | |
| GB2240874A (en) | Photodiode | |
| JPS6064464A (en) | Semiconductor device and manufacture thereof | |
| JPH0582827A (en) | Semiconductor light receiving element | |
| JPH06132511A (en) | Photodetecting integrated element | |
| JPH02228077A (en) | Semiconductor photodetector | |
| JP2000277791A (en) | Semiconductor light receiver and its manufacture | |
| JPH0722641A (en) | Photodetector | |
| JP3199414B2 (en) | Optoelectronic integrated circuit device |