JPH0582827A - Semiconductor light receiving element - Google Patents

Semiconductor light receiving element

Info

Publication number
JPH0582827A
JPH0582827A JP3238484A JP23848491A JPH0582827A JP H0582827 A JPH0582827 A JP H0582827A JP 3238484 A JP3238484 A JP 3238484A JP 23848491 A JP23848491 A JP 23848491A JP H0582827 A JPH0582827 A JP H0582827A
Authority
JP
Japan
Prior art keywords
film
light receiving
mesa
inp
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3238484A
Other languages
Japanese (ja)
Inventor
Takeshi Takeuchi
剛 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3238484A priority Critical patent/JPH0582827A/en
Publication of JPH0582827A publication Critical patent/JPH0582827A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Landscapes

  • Photovoltaic Devices (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To lessen the parasitic capacity and improve the high-speed responsiveness by having a passivation-cum-reflection preventive film on the surface of an element, and specifying the thickness. CONSTITUTION:The crystals of n<+>-InP 2, n<->-InGaAs 3, and n-InP layers 4 are stacked in order on a semiinsulating InP substrate 1, and then pn junction is made in the InGaAs 3 by the selective heat diffusion of Zn. Next, a mesa 6 including a light receiving part and a mesa 7 for an electrode are made by selective etching, and then a silicon nitride film 8 is made on the surface of the element by plasma CVD. This film doubles as a passivation film and a reflection preventive film, and the thickness shall be the wavelength (2n+1) within the film of an incident light/4 times (n is a natural number). Thereby, the process for changing the thicknesses of the films on the light receiving part and the section excluding it can be omitted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体受光素子に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light receiving element.

【0002】[0002]

【従来の技術】化合物半導体を用いた半導体受光素子は
光通信用素子などに広く用いられている。この光通信用
素子の一例としてInGaAs pinフォトダイオー
ドがあげられる。応答特性の高速化,受信感度の向上が
この素子には求められている。応答特性の高速化のため
には素子容量を低減することが重要となる。そのために
は、接合径を充分小さくし、接合容量を低減すると共
に、寄生容量も低減する必要がある。寄生容量を低減す
るための素子構造として、たとえば選択拡散によるp+
−n型のプレーナ型素子の場合、半絶縁性基板とメサ構
造による素子分離技術を用いて受光部とは別のメサ分離
された領域にp電極を形成し、これとp+ 領域とを段差
配線で接続する構造が考えられている。この様な構造を
とることで寄生容量を増やすことなく、素子実装に必要
充分な広い面積を持つpパッド電極を形成することがで
きる。また、受信感度の向上のためには、第一には光吸
収層を厚くすればよいが、ある程度以上厚くするとキャ
リアの走行時間制限により応答速度の劣化が起こってく
るため無制限に厚くすることはできない。そこで、例え
ば表面入射型素子の場合は、鏡面研磨した素子裏面に反
射膜を形成し、裏面反射光を再び光吸収層に入射させる
ことで実効的な吸収層厚を増加させたり、あるいは素子
の受光部の表面に窒化シリコン膜を形成し、その膜厚を
入射光の膜中での波長の1/4とすることにより表面反
射を抑えるなどして受信感度を向上させるための工夫が
なされている。
2. Description of the Related Art A semiconductor light receiving element using a compound semiconductor is widely used as an element for optical communication. An example of this optical communication element is an InGaAs pin photodiode. Higher response characteristics and improved receiver sensitivity are required for this device. It is important to reduce the element capacitance in order to speed up the response characteristics. For that purpose, it is necessary to reduce the junction diameter sufficiently to reduce the junction capacitance and also the parasitic capacitance. As an element structure for reducing the parasitic capacitance, for example, p + by selective diffusion is used .
-In the case of an n-type planar type element, a p-electrode is formed in a mesa-isolated region different from the light-receiving part by using an element isolation technique using a semi-insulating substrate and a mesa structure, and a step is formed between this and the p + region. A structure in which wiring is used for connection is being considered. By adopting such a structure, it is possible to form a p-pad electrode having a large area necessary for mounting an element without increasing the parasitic capacitance. Further, in order to improve the receiving sensitivity, firstly, the light absorption layer may be thickened, but if it is thickened to a certain extent or more, the response speed is deteriorated due to the limitation of the transit time of the carrier, so it is not possible to make the thickness unlimited. Can not. Therefore, for example, in the case of a front-illuminated element, a reflective film is formed on the back surface of the element that is mirror-polished, and the back-reflected light is incident on the light absorption layer again to increase the effective absorption layer thickness, or A silicon nitride film is formed on the surface of the light receiving part, and its thickness is set to 1/4 of the wavelength in the film of incident light, so that surface reflection is suppressed to improve the receiving sensitivity. There is.

【0003】[0003]

【発明が解決しようとする課題】選択拡散によるp+
n型のプレーナ型のInGaAs pinフォトダイオ
ードを考える。半絶縁性基板を用いて受光部とは別のメ
サ領域を設け、この領域にpパッド電極を形成し、これ
とp+ 領域とを段差配線で接続する構造の素子の場合、
段差配線の一部がパッシベイション膜を介してn領域上
を通る。この部分で寄生容量が発生する。この様な構造
の素子においては、通常は同一の窒化シリコン膜に、パ
ッシベイション膜と反射防止膜の二つの機能をもたせて
いる。光通信で通常用いる光の波長は1.3μm〜1.
55μmであり、この窒化シリコンの膜厚は、この光の
膜中での波長の1/4とするのが普通である。したがっ
てこの窒化シリコン膜の膜厚は、0.2μm程度と薄
く、前述の寄生容量が大きくなってしまうという問題点
があった。この寄生容量の増加を防ぐには、例えば最初
に充分厚い窒化シリコン膜を形成し、後で選択エッチン
グにより受光部の膜厚のみを約0.2μmとするという
方法がある。しかしこの方法で受光部を形成するために
は、PR工程,選択エッチング工程が余計に必要となる
という問題点がある。 本発明の目的は、このような問
題点を解決した半導体受光素子を提供することにある。
P + − by selective diffusion
Consider an n-type planar InGaAs pin photodiode. In the case of an element having a structure in which a mesa region different from the light receiving portion is provided using a semi-insulating substrate, a p pad electrode is formed in this region, and this and the p + region are connected by step wiring,
Part of the step wiring passes over the n region via the passivation film. Parasitic capacitance is generated in this portion. In the element having such a structure, the same silicon nitride film is usually provided with two functions of a passivation film and an antireflection film. The wavelength of light normally used in optical communication is 1.3 μm to 1.
It is 55 μm, and the film thickness of this silicon nitride is usually 1/4 of the wavelength in the film of this light. Therefore, the thickness of this silicon nitride film is as thin as about 0.2 μm, and there is a problem that the above-mentioned parasitic capacitance becomes large. In order to prevent this increase in parasitic capacitance, for example, there is a method in which a sufficiently thick silicon nitride film is first formed and then only the film thickness of the light receiving portion is set to about 0.2 μm by selective etching. However, in order to form the light receiving portion by this method, there is a problem that the PR process and the selective etching process are additionally required. An object of the present invention is to provide a semiconductor light receiving element that solves such problems.

【0004】[0004]

【課題を解決するための手段】前述の課題を解決するた
めに本発明が提供する半導体受光素子は、素子表面にパ
ッシベイション膜兼反射防止膜を有し、かつその膜厚が
入射光の膜中での波長の(2n+1)/4倍(nは自然
数)であることを特徴とする。
In order to solve the above-mentioned problems, a semiconductor light receiving element provided by the present invention has a passivation film / antireflection film on the element surface, and the film thickness of the incident light is The wavelength is (2n + 1) / 4 times (n is a natural number) in the film.

【0005】[0005]

【実施例】以下本発明の一実施例について、図面を参照
して説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0006】図1は本発明の一実施例を示すpinフォ
トダイオードの断面構造模式図である。本実施例の構造
を、その製造工程とともに説明する。
FIG. 1 is a schematic sectional view of a pin photodiode showing an embodiment of the present invention. The structure of this embodiment will be described together with its manufacturing process.

【0007】まず、半絶縁性InP基板1上に気相成長
法により順次n+−InP2,n- −InGaAs3,
n−InP層4の結晶を積層する。その後、Znの選択
熱拡散により直径40μmのpn接合をInGaAs3
中に形成する。次に、選択エッチングにより受光部を含
むメサ6とpパッド電極用メサ7を形成する。このとき
のエッチングは半絶縁性基板1に達するまで行うことに
より、これらのメサを電気的に分離している。その後、
プラズマCVDにより素子表面に窒化シリコン膜8を形
成する。このときの膜厚は、ここでは入射光の膜中での
波長の3/4倍とした。最後に、p側電極9及びn側電
極10を形成する。p側電極9は、p+ 領域5上のコン
タクト電極部とパッド電極部とを段差配線で接続した構
造となっている。
First, n + -InP2, n -- InGaAs3 are sequentially formed on the semi-insulating InP substrate 1 by vapor phase epitaxy.
The crystals of the n-InP layer 4 are stacked. After that, a pn junction having a diameter of 40 μm is formed by InGaAs3 by selective thermal diffusion of Zn.
Form inside. Next, the mesa 6 including the light receiving portion and the mesa 7 for the p-pad electrode are formed by selective etching. These mesas are electrically separated by performing the etching at this time until reaching the semi-insulating substrate 1. afterwards,
A silicon nitride film 8 is formed on the device surface by plasma CVD. The film thickness at this time was 3/4 times the wavelength of the incident light in the film. Finally, the p-side electrode 9 and the n-side electrode 10 are formed. The p-side electrode 9 has a structure in which the contact electrode portion on the p + region 5 and the pad electrode portion are connected by a step wiring.

【0008】次に窒化シリコン膜8について詳細に説明
する。この膜はパッシベイション膜と反射防止膜を兼ね
ている。反射防止膜としての機能ももち、しかも寄生容
量を低減するためになるべく膜厚が厚い方がよいという
要請から、この膜の膜厚は、入射光の膜中での波長の3
/4倍としている。こうすることにより、受光部上とそ
うでない部分の膜厚を変えるための工程を省略すること
ができる。
Next, the silicon nitride film 8 will be described in detail. This film also serves as a passivation film and an antireflection film. Since the film has a function as an antireflection film and it is preferable that the film thickness be as thick as possible in order to reduce parasitic capacitance, the film thickness of this film is 3 times the wavelength of incident light in the film.
/ 4 times. By doing so, it is possible to omit the step of changing the film thickness on the light receiving portion and on the other portion.

【0009】尚、この例では窒化シリコン膜8の膜厚を
入射光の膜中での波長の3/4倍とする場合を示した
が、3/4倍に限らず(2n+1)/4倍(nは自然
数)であれば同様の効果が得られる。
In this example, the case where the film thickness of the silicon nitride film 8 is set to 3/4 times the wavelength of the incident light in the film is shown, but it is not limited to 3/4 times and (2n + 1) / 4 times. If (n is a natural number), the same effect can be obtained.

【0010】[0010]

【発明の効果】以上説明したように、本発明によれば寄
生容量が小さく高速応答性に優れた半導体受光素子を少
ない工程数で得ることができる。
As described above, according to the present invention, a semiconductor light receiving element having a small parasitic capacitance and an excellent high-speed response can be obtained in a small number of steps.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すpinフォトダイオー
ドの断面構造模式図である。
FIG. 1 is a schematic sectional view of a pin photodiode showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半絶縁性InP基板 2 n+ −InP 3 n- −InGaAs 4 n−InP 5 p+ 領域 6 受光部を含むメサ 7 pパッド電極用メサ 8 窒化シリコン膜 9 p側電極 10 n側電極1 Semi-insulating InP substrate 2 n + -InP 3 n -- InGaAs 4 n -InP 5 p + region 6 Mesa including light receiving part 7 Mesa for p pad electrode 8 Silicon nitride film 9 p-side electrode 10 n-side electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】素子表面にパッシベイション膜兼反射防止
膜を有し、かつその膜厚が入射光の膜中での波長の(2
n+1)/4倍(nは自然数)であることを特徴とする
半導体受光素子。
1. A device has a passivation film and an antireflection film on the surface thereof, and the film thickness is (2) the wavelength of the incident light in the film.
n + 1) / 4 times (n is a natural number).
JP3238484A 1991-09-19 1991-09-19 Semiconductor light receiving element Pending JPH0582827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3238484A JPH0582827A (en) 1991-09-19 1991-09-19 Semiconductor light receiving element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3238484A JPH0582827A (en) 1991-09-19 1991-09-19 Semiconductor light receiving element

Publications (1)

Publication Number Publication Date
JPH0582827A true JPH0582827A (en) 1993-04-02

Family

ID=17030933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3238484A Pending JPH0582827A (en) 1991-09-19 1991-09-19 Semiconductor light receiving element

Country Status (1)

Country Link
JP (1) JPH0582827A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791153B2 (en) 2002-03-08 2004-09-14 Kabushiki Kaisha Toshiba Photo detector with passivation layer and antireflection layer made of the same material
JP2008244368A (en) * 2007-03-29 2008-10-09 Eudyna Devices Inc Optical semiconductor module and light-receiving element
US7687874B2 (en) 2006-07-04 2010-03-30 Opnext Japan, Inc. Surface illuminated photodiode and optical receiver module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791153B2 (en) 2002-03-08 2004-09-14 Kabushiki Kaisha Toshiba Photo detector with passivation layer and antireflection layer made of the same material
US7042059B2 (en) 2002-03-08 2006-05-09 Kabushiki Kaisha Toshiba Optical semiconductor device and method for manufacturing optical semiconductor device
US7687874B2 (en) 2006-07-04 2010-03-30 Opnext Japan, Inc. Surface illuminated photodiode and optical receiver module
JP2008244368A (en) * 2007-03-29 2008-10-09 Eudyna Devices Inc Optical semiconductor module and light-receiving element

Similar Documents

Publication Publication Date Title
JP4220688B2 (en) Avalanche photodiode
JP2002289904A (en) Semiconductor light-receiving element and its manufacturing method
JP2003163364A (en) Semiconductor photodetector and method of driving the same
JPH0287684A (en) Integrated pin photo detector and method
US6396117B1 (en) Semiconductor photodetector, method for manufacturing semiconductor photodetector and photodetector module
JPH0677518A (en) Semiconductor photodetector
EP1204148A2 (en) Planar resonant cavity enhanced photodetector
US6489232B1 (en) ESD resistant device
JPH0582829A (en) Semiconductor light receiving element
JP4109159B2 (en) Semiconductor photo detector
JP2001320081A (en) Semiconductor light receiving element
JPH0582827A (en) Semiconductor light receiving element
JPH0567769A (en) Three-dimensional photoelectronic integrated circuit device
JP2730472B2 (en) Semiconductor light receiving element
JPH01296676A (en) Semiconductor photodetecting device
JPH07118548B2 (en) III-V group compound semiconductor PIN photo diode
JP2007504659A (en) Systems and methods having metal-semiconductor-metal (MSM) photodetectors with buried oxide layers
JPH04360585A (en) Semiconductor photodetector
JPS6032812B2 (en) photodetector
JPH02199877A (en) Optical receiver and photoelectric integrated circuit
JPH07142759A (en) Semiconductor photoreceptor element
JP2000188415A (en) Semiconductor light receiving device
JPS61224468A (en) Semiconductor photodetector
JP2004158763A (en) Semiconductor photo detector
JPS59149070A (en) Photodetector