JPH01196182A - Photodiode - Google Patents

Abstract

PURPOSE:To remove the parasitic capacitance due to a conductive substrate or the like, to realize a high-speed operation and to comply with an OEIC (optoelectronic integrated circuit) by a method wherein one electrode comes into contact with a high-concentration impurity region in a p-n junction to the interface with a light-absorption layer and the other electrode is connected to the light-absorption layer via a contact layer. CONSTITUTION:Both sides of a p<+> region 6 which is laminated on one surface of a semi-insulating InP substrate 1 and is formed by diffusing Zn in a circular form are dug down from the surface side; an SI-InP buried layer 7 reaching the surface of an n<-> InP buffer layer 2 is formed on one side; an n<-> electrode 12 is formed on an n<+> contact layer 3 on the other side so as to come into contact with the surface of the contact layer 3. In addition, a ring-shaped p<-> electrode 10 is formed so as to come into contact with the surface of the p<+> region 6 via a contact hole made in a passivating film 8 which is formed on the surface of an n<-> InP window layer 5, the p<+> region 6 and the SI-InP buried layer 7 and on a side wall face of the n<-> electrode 12. A bonding pad 11 extended on the surface side of the SI-InP buried layer 7 is continued to the electrode 10.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to photodiodes used in fields such as optical transmission and optical information processing. [Conventional technology]

Conventionally, for example, a tie-auto with a PIN structure as shown in FIG. 12 has been widely used. That is, this photodiode is connected to an n+-1nP substrate 3].
-InP buffer J! 32. It has a product R structure in which an n-1nGa nano-sP light absorption layer 33 and an n-1nP winding layer 34 are sequentially crystal-grown, and Zn is diffused into a circular region with a diameter of about 100 μm using the SiO□ film 36 as a mask. 1) + region 37 formed by
It has a p- electrode 38 formed at the periphery of this p+ region and three n- electrodes formed on the back surface of the substrate 31.

[Problems to be solved by the invention]

However, the conventional photodiode having such a structure has a problem in that it is not compatible with opto-electronic integrated circuits (EIC) in which an optical element and an electronic element are integrated on the same substrate. In addition, conductive substrates and
Deterioration of response speed due to parasitic capacitance caused by pads is also a problem. The object of the present invention is to eliminate parasitic capacitance caused by a conductive substrate and the like to increase speed, and to provide a phototire with a structure that can be adapted to 0EIC. [Means for Solving the Problems] A photodiode according to the present invention includes a semi-insulating substrate, a buffer layer of one conductivity type that is successively crystal-grown on one surface of the substrate, and a buffer layer identical to the buffer layer. a contact layer of a conductivity type, a light absorption layer and a window layer of the same conductivity type as above, a high impurity concentration region of a conductivity type opposite to the above and provided from the surface of the window layer (-), and a high impurity concentration region of the high impurity concentration region. The electrode formed on the surface periphery and the contact 1 from the surface side
- an electrode formed so as to be in contact with the contact layer at a portion dug down to the contact layer.

[For production]

A pn junction is formed at the interface between the high impurity concentration region and the light absorption layer. One electrode is in contact with this high impurity concentration region, and the other electrode is connected to the light absorption layer via the contact 1 layer. Therefore, when a reverse bias voltage is applied to the pH junction via these electrodes, the light absorption layer becomes a depletion layer. When light enters this depleted light absorption layer, the light is absorbed and electron-hole pairs are generated. This electron-hole pair becomes a depletion layer and is separated by the electric field in the photo-absorbing layer into the drift 1 to become a photocurrent, which is taken out from the two electrodes.

【Example】

A foyer tie auto according to a preferred embodiment of the present invention has a structure as shown in FIG. That is, on one surface of a semi-insulating InP substrate (SI-InP substrate) 1, an n-1 nP buffer layer 2, an n''-InGaAs layer or an n''-InGaAsP layer are successively grown on one surface of a semi-insulating InP substrate (SI-InP substrate) 1.
n4-contact 1 to layer 3, n--InGaA
s light absorption As light n--I "IP (or 5I-1nP
) It has a laminated structure of a wind layer 5. The surface side has a resistance region 6 formed by circularly diffusing Zn. Both sides of this p+ region 6 are dug down from the surface side, and on one side there is the 5I-1nP buried layer 7 that reaches the surface of the 1--■nP buffer layer 2, and on the other side. An n-electrode 12 is provided on the contact 1-layer 3 so as to be in contact with the surface of the 11'-contact I-layer 3.Furthermore, this n-1nP wint layer 5,
．． A passivation film (made of SiNx, etc.) is formed on the surface of the 5l-1nP buried layer 7 and the side wall surface on the n-electrode 12 side.
8 is formed, and a p-electrode 10 is attached in a ring shape so as to be in contact with the surface of the p" region 6 through a contact 1-pole provided on this passivation film 8. 10 is continuous with a punch ink pad 11 extending to the surface side of the 5I-1nP buried layer 7. In a photodiode with such a structure, an inverse n −1n depending on the bias voltage
The GaAs light absorption layer 4 becomes a depletion layer. For this depleted layer of n″′-InGaAs light absorption As light, InGaA
When light having a photon energy greater than the Hann l-' gap of s is incident, the light is absorbed and electron-hole pairs are generated in the n"'-1n GaAs light absorption layer 4 as shown in FIG. This electron-hole pair is a depleted layer of n--1n.
The Ga, As light is separated and drifted by the electric field within the light absorption layer to become a photocurrent, which is taken out from the electrode 10.12. The follo-tiort of the above structure is created as follows. First, as shown in FIG. 3, an n-InP buffer layer 2, an n4-contact layer 3, an n-1nGaAs light absorption layer 4, and an n-1nP window layer 5 are formed by crystal growth on the surface of a 5I-InP substrate. are formed sequentially. Next, a SiNx film 8 is formed on the n''-1nP layer 5.
is formed and patterned for forming an etching mask. Then, by a chemical etching method or a dry etching method (for example, RIE method, etc.), n−1n is etched.
The P buffer layer 2 is etched vertically to form grooves 21 at regular intervals as shown in FIG. After that, using the same mask, this groove 21 is made into a semi-insulating 1nP film.
5 to form an SI-InP buried layer 7 as shown in FIG. Next, this 5jNx film 8 (Fig. 4) is removed and the SI
An Nχ film 8 is formed and patterned to create a mask of the SiNx film 8 having circular holes with a diameter of 100 μm as shown in FIG. - A p+ region 6 is formed at a depth that slightly penetrates into the TnGaAs light absorption layer 4. After this 5jNx film 8 is removed again and the SiNx film 8 (see FIG. 6) is deposited again, patterning is performed to form an etching mask. Then, by dry or chemical etching, etching is performed in the vertical direction up to the n+-contact layer 1-3 to form a groove 22 as shown in FIG. Thereafter, a concentric p- electrode]0 is formed on the p'' region 6 by a technique such as a lift-off method so as to be in contact with the p+ region 6 (see FIG. 6).
. Furthermore, after forming the SINx film 8 as shown in FIG. 7 on the entire surface formed as shown in FIG. , the Si-1nP substrate 1 is etched vertically by RIE method or the like. In the case of the R, IE method, the etching directionality is good, so the SiNx film 8 is etched only in the direction perpendicular to the substrate, and only the SiNx film 8 at the bottom of the groove 22 is removed and the sidewall surface of the groove 22 is etched. S j-Nχ film 8
remains as is. Next, after removing 23 from the photoresist 1, the SiNx film 8 (
In this state, metal such as Ti/Au is deposited over the entire surface. Then, the metal layer deposited on the SiNx film 8 on the side wall of the groove 22 is removed by a method such as oblique ion milling. In this way, separated bonding pads 1] and n-electrodes 12 are formed as shown in FIG. Thereafter, the bond ink pad 11 is patterned as shown in FIG. 9, and cut into pellets by cutting at the n-electrode@12 part at the bottom of the groove 22 and the S l-1nP buried layer 7 part. A photodiode having the structure shown in FIG. 1 is completed. In this example, the 5I-InP buried layer 7 is provided, or the groove (21 in FIG. 4) for the S I-1nP buried layer 7 is not provided as shown in FIG. No buried layer is provided, or S I
- Although a groove (21 in FIG. 4) for the 1nP buried layer 7 is provided, this groove is not filled with the 5I-1nP buried layer 7, and is pumped from the side wall surface to the surface of the 5I-TnP substrate 1. It is also possible to extend the contact pad 11. In these embodiments, since a semi-insulating InP substrate 1 is used, the phototire and the P necessary for its operation are
Electronic elements such as UTs can be integrated on the same substrate, and parasitic capacitance can be reduced. In other words, ○EIC, which integrates an optical element and the electronic circuit necessary for its operation on the same substrate,
Eliminates the effects of wiring interface and parasitic capacitance, which are problems when using conventional individual optical elements, and improves response speed and
Since the operating characteristics of optical devices such as noise characteristics can be significantly improved, they are attracting attention as a new form of optical technology for the future fields of optical communications and information processing. A vertical integrated structure in which an insulating layer is provided on a conductive substrate and electronic devices such as FE processing are integrated on the second layer, and a horizontal integrated structure in which optical devices and electronic devices are integrated on a semi-insulating substrate. In the case of ■, there is a problem that the response speed deteriorates due to the parasitic capacitance caused by the optical element conductive substrate below the electronic element.On the other hand, in the case of ■, the electronic element Due to the thin thickness of the substrate, a step may occur, which may cause problems in lithography.However, this problem can be overcome by improving the manufacturing process, and therefore the structure described in (2) is becoming mainstream. Since the photo diode is formed using a semi-insulating substrate as shown in the figure, the 0E of the structure shown in
It became possible to use IC. Furthermore, in order to achieve high-speed response, it is necessary to reduce the capacitance of the element itself, and for this purpose, it is important to reduce the stray capacitance due to the bond ink pad as much as possible. Here, 5 Honding Padco]
I-1nP buried layer 7 (FIG. 1), 5I-
By arranging it on a 1nP substrate 1 (FIG. 11), stray capacitance due to this bonding pad 11 is eliminated. Furthermore, crystal defects such as dislocations in the n--1nGaAs light absorption layer 4 cause an increase in dark current and a decrease in sensitivity, but n'
-- Forming InP buffer layer 2 on 5I-1nP substrate 1 --
10 = As a result, it is possible to prevent the propagation of dislocations from the 5I-TnP substrate 1, and since a stable surface is obtained, the n + - contact layer 3 etc. can be formed on it by growth with good crystallinity. . The n+-contact layer 3 is made of an n+-1nGaAs layer or a -InGa, AsP layer, but especially an n''-
In the case of a 1nGaAs layer, a low ohmic contact can be obtained because the band gap of InGaAs is small and high concentration Tobink is possible. For this reason,
The series resistance is also reduced, which is preferable in terms of high-speed response. When the n--■nGaAs light absorption layer 4 is not completely depleted, the minority carriers generated in the neutral region outside the depletion layer are annihilated by recombination in the region other than the diffusion length. Minority carriers generated within the diffusion length diffuse to the edge of the depletion layer, drift due to the high electric field within the depletion layer, and arrive at the edge of the depletion layer on the opposite side. Since the diffusion time is generally longer than the transit time in the depletion layer of Drifts 1 to 2, this diffusion current component cannot follow the optical signal during high-speed response and does not contribute to the photocurrent. Therefore, only the light absorbed within the depletion layer contributes to the photocurrent. From the above, in order to increase the quantum efficiency, n-~InGaAsI
Is it necessary to make the nGaAsP absorption layer a depletion layer? Also from the viewpoint of response speed, the n--InGaAs light absorption layer 4
If there is a neutral region that is not completely depleted, this region acts as a high resistance layer, increasing the CR time constant of the element and slowing down the response speed. Therefore, in the above embodiment, the carrier concentration of the n--InGaAs light absorption layer 4 is set to 1.
~2×1015cm-3, 3 at a low voltage of about 5■
The n'-InGaAs light absorbing layer 4 having a thickness of μ■ is completely made into a depletion layer so that 95% of light is absorbed and effectively converted into photocurrent. Furthermore, when the passivation film 8 is directly deposited on the n--InGaAs light absorption layer 4, the quantum efficiency decreases due to surface recombination.
An n--InP wind layer 5 with a larger band gap is grown on the n-GaAs light absorption layer 4, and an n--InP wind layer 5 is grown on the n--InP
An energetic barrier to holes is formed at the interface between the aAs light absorption layer 4 and the n -1nP window layer 5 to prevent the quantum efficiency from decreasing due to the above-mentioned surface recombination.

【Effect of the invention】

According to the photodiode of the present invention, since a semi-insulating substrate is used and the electrode structure is planar, high-speed ○EIC (
It can be manufactured as an opto-electronic integrated circuit). In addition, a buffer layer of one conductivity type is crystal-grown on a semi-insulating substrate, and since the surface of this buffer layer is stable, it enables good crystal growth of the contact layer that is crystal-grown on top of it. At the same time, it is possible to prevent the propagation of the transition in the light absorption layer f\.

[Brief explanation of the drawing]

FIG. 1 is a partially sectional perspective view of an embodiment of the present invention;
Figure 2 is an energy band diagram for explaining the operation, and Figures 3, 4, 5, 6, 7, 8, and 9 are cross-sectional views showing an example of the manufacturing process. , Figure 10 and Figure 1
FIG. 1 is a sectional view of another embodiment, and FIG. 12 is a sectional view of a conventional example. =13-1---3I-InP substrate, 2.32-n--1nP buffer layer, 3-n+-contact layer, 4-n--1n
GaAs light absorption layer, 5...n--1nP wind layer,
6.37... p″ region, 7 ・5I-InP buried layer, 8
...Passivation film (SiNx film), 9.. Antireflection film (SiNx film), 10.38. P-electrode, 12.
39'=-n-electrode, 1]...Honding pin 1, 21.22 Groove, 23...Photoresis 1~.
3]...n"-1nP substrate, 33n--InGaAsP
Light absorption layer, 34 =・n-1nPwin) layer, 36・
・5i02 membrane.

Claims (1)

[Claims] (1) A semi-insulating substrate, a buffer layer of one conductivity type that is successively crystal-grown on one surface of the substrate, a contact layer of the same conductivity type as the buffer layer, and a light absorption layer of the same conductivity type as the above. and a window layer, a high impurity concentration region of a conductivity type opposite to the above provided from the surface of the window layer, an electrode formed on the surface periphery of the high impurity concentration region, and digging down from the surface side to the contact layer. and an electrode formed so as to be in contact with the contact layer at the contact layer.