JP2626149B2 - Optoelectronic integrated circuit manufacturing method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an improvement in a method for manufacturing an optoelectronic integrated circuit which is a core of a future optical communication system or the like.

[Conventional technology]

With the advancement of optical communication technology, its application field is rapidly expanding from backbone transmission systems to subscriber systems, LANs, data links, and other systems. In order to respond to the sophistication of the optical system, it is indispensable that the optical device has higher performance and higher functionality.

Opto-electronic integrated circuits are one of the key devices at the core of these optical systems. In addition to the basic advantages of integration such as low cost, small size, high reliability, and no adjustment, high speed
High functionality that supports future optical systems such as optical device performance improvement such as higher sensitivity and optical wiring and optical switching
Research and development aiming at realization of new functional devices are being conducted.

In order to improve the performance of optoelectronic integrated circuits, a fine electrode forming process technology capable of forming a gate electrode of 1 μm or less with good reproducibility in an electronic element to be used is required. When an optoelectronic integrated circuit is manufactured, a step of several μm occurs in a wafer due to a difference in a layer structure between an optical element and an electronic element. For this reason, when an optoelectronic integrated circuit is manufactured by using a normal photolithography technique, a 1 μm
It becomes difficult to form the following fine patterns. In order to solve the spread of the pattern, there has been known a method in which a step substrate is used, and an optical element is formed below the step and an electronic element is formed above the step so that the optical element and the electronic element have the same height. As an optoelectronic integrated circuit having such a step structure, there is, for example, an invention described in Japanese Patent Application No. 62-072053, which is the invention of Teramon et al.

[Problems to be solved by the invention]

However, in this prior art, the height of the photoelectron and the electronic element are the same, but the optical element has a mesa structure and there is a step of about several μm in the wafer. Pattern defects are likely to occur. Conventionally, in order to prevent this pattern failure, a thick resist having a thickness of about 2 μm has been used in the electrode forming process. However, when a thick resist is used, the gate length becomes 1
It is difficult to form a gate electrode of μm or less with good reproducibility, which makes it difficult to improve the performance of the FET, and further increases the variation in characteristics. As a result, not only is it not possible to obtain sufficient device characteristics as an optoelectronic integrated circuit, but also there is a defect that the characteristics are not uniform.

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method capable of eliminating these drawbacks and obtaining a high-performance optoelectronic integrated circuit with good reproducibility and controllability.

[Means for solving the problem]

In order to solve the above problems and achieve the above object, a first method for manufacturing an optoelectronic integrated circuit provided by the present invention is an optoelectronic integrated circuit in which an optical element and an electronic element are monolithically integrated on a substrate. Forming the optical element layer below the step of the semi-insulating semiconductor substrate having a step; forming an electronic element layer above the step of the semi-insulating semiconductor substrate; And a step of selectively filling a groove at a boundary between a layer and the electronic element layer with a semiconductor layer to planarize the wafer.

Further, a second manufacturing method is a method of manufacturing an optoelectronic integrated circuit in which an optical element and an electronic element are monolithically integrated on a substrate, wherein an optical element layer is partially provided on a flat semi-insulating semiconductor substrate. Forming a high-resistance semiconductor layer and an electronic element layer in a region on the semi-insulating substrate where the optical element layer is not formed; and forming the optical element layer and the electronic layer. The method is characterized in that the method includes a step of flattening a wafer by selectively filling a groove at a boundary with a semiconductor layer.

[Action]

In a first method for manufacturing an optoelectronic integrated circuit according to the present invention, an optical element layer is formed below a step of a semi-insulating semiconductor substrate having a step, an electronic element layer is formed above the step, and the optical element layer and the electronic element are further formed. By selectively burying the groove at the boundary between the layers with a semiconductor layer, the step of the wafer can be suppressed to 1 μm or less. Compared with the conventional method for manufacturing an optoelectronic integrated circuit having a step of 5 μm or more, the pattern defect of the photoresist at the step is improved, and further, since a thin film resist can be used, a fine gate electrode of 1 μm or less can be used in an electronic device. Good reproducibility and controllability. Therefore, a high-yield and high-performance optoelectronic integrated circuit can be obtained.

The second manufacturing method includes forming an optical element layer on a part of a flat semi-insulating semiconductor substrate, and forming a high-resistance semiconductor layer and an electronic element in a region on the semi-insulating substrate where the optical element layer is not formed. Layers are formed by laminating the layers, and the trench at the boundary between the optical element layer and the electronic element layer is selectively filled with a semiconductor layer, so that the step of the wafer can be suppressed to 1 μm or less.

For the same reason as in the first manufacturing method, a high-yield and high-performance optoelectronic integrated circuit can be obtained.

〔Example〕

Next, the manufacturing method of the embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of an optoelectronic integrated circuit manufactured by a first manufacturing method, and FIGS. 2A to 2D are process diagrams of wafer flattening, which is a main part of the first manufacturing method. It is.

First, on a semi-insulating semiconductor substrate 10 made of InP having a step of 5 μm, a first buffer layer 11 made of n-InGaAsP (thickness 0.5 μm, Carrier concentration 5 × 10 ¹⁸ cm ⁻³ ), second buffer layer 12 made of n ⁻ -InP (thickness 3.0 μm, carrier concentration 5 × 10 ¹⁵ cm ⁻³ ), and light absorption layer 13 made of n ⁻ -InGaAs (Thickness 1.5 μm, carrier concentration 5 × 10 ¹⁵ cm ⁻³ ), window layer 14 made of n ⁻ —InP (1.0 μm thickness, carrier concentration 5 × 1
0 ¹⁵ cm ⁻³ ) is grown to form an optical element layer 1. A mask 15 made of SiO ₂ is applied to a part of the optical element layer below the step, and the optical element layer above the step and the unnecessary optical element layer 1 below the step are etched, thereby forming a step on the semi-insulating semiconductor substrate 10. The optical element layer 1 is formed only on the lower portion (FIG. 2A). Next, a strain buffer layer 16 made of GaAs (thickness 0.8 μm, non-doped) and an active layer 17 made of n-GaAs (thickness 0.2 μm, carrier concentration 1 × 10 ¹⁷ cm) by a vapor phase growth method or a molecular beam growth method.
^-3 ) is grown to form the electronic element layer 2. A mask 18 made of SiO ₂ is applied to the electronic element layer 2 above the step (FIG. 2 (b)), and unnecessary electronic element layers (electronic element layers below the step and on the optical element layer) 2 are etched. An electronic element layer 2 is formed on the upper part (FIG. 2C). The wafer is flattened by selectively growing a semiconductor layer 20 made of Fe-doped InP at a depth of 5 μm in the groove 19 formed by this etching using a vapor phase selective growth method or a molecular beam growth method ( (FIG. 2 (d)). Thereafter, the optoelectronic integrated circuit is manufactured by a general manufacturing process. That is, the active layer
17 is selectively removed by etching to partition the field effect transistor 4. Next, selective zinc diffusion is performed on the window layer 14 of the optical element layer 1 using a mask made of SiO ₂ to form a p-type inversion region 21, thereby forming a PIN photodiode 3. Further PIN
The p-type inversion region 21 of the photodiode 3
An electrode 22, an n-electrode 23 made of AuGeNi is formed on the window layer 14, and a source electrode 24 / drain electrode 25 made of AuGeNi and a gate electrode 26 made of Ti / Pt / Au are formed on the active layer 17 of the field effect transistor 4. Then, a passivation film 27 made of a 0.2 μm thick Si ₃ N ₄ dielectric is formed on the PIN photodiode 3.
Is formed, a wiring 28 made of Ti / Au is provided, and the chip is divided into individual chips to complete the optoelectronic integrated circuit for light reception shown in FIG.

FIG. 3 is a cross-sectional view of an optoelectronic integrated circuit manufactured by the second manufacturing method, and FIGS. 4A to 4D are process diagrams of wafer flattening, which is a main part of the second manufacturing method. It is.

First, n is formed on a flat semi-insulating semiconductor substrate 10 made of InP by a liquid phase growth method, a vapor phase growth method, or a molecular beam growth method.
A first buffer layer 11 of InGaAsP (0.5 μm thick)
m, carrier concentration 5 × 10 ¹⁸ cm ⁻³ ), second buffer layer 12 of n ⁻ -InP (thickness 3.0 μm, carrier concentration 5 × 1
0 ¹⁵ cm ^-3 ), a light absorption layer 13 (1.5 μm thick) made of n ⁻ -InGaAs
m, carrier concentration 5 × 10 ¹⁵ cm ⁻³ ), window layer 14 made of n ⁻ -InP (thickness 1.0 μm, carrier concentration 5 × 10 ¹⁵ cm ³ )
^-3 ) is grown to ^obtain an optical element layer 1. An optical element layer 1 is selectively formed on a part of the semi-insulating semiconductor substrate 10 by applying a mask 15 made of SiO ₂ to a partial region on the optical element layer and etching an unnecessary optical element layer 1 ( FIG. 4 (a)). next,
A high-resistance semiconductor layer 29 (5 μm in thickness) made of Fe-doped InP is grown by a vapor phase growth method or a molecular beam growth method.
A strain buffer layer 16 made of GaAs (thickness 0.8 μm, non-doped) and an active layer 17 made of n-GaAs (thickness 0.2 μm, carrier concentration 1 × 17 ¹⁷ cm ⁻³ ) are grown to form an electronic element layer 2. . A mask 18 made of SiO ₂ is applied to the electronic element layer 2 (fourth step).
(FIG. 4B), the unnecessary electronic element layer 1 and the high-resistance semiconductor layer 29 on the optical element layer 1 are removed by etching (fourth step).
Figure (c). The wafer is flattened by selectively growing a semiconductor layer 20 made of Fe-doped InP at a depth of 5 μm in the groove 19 formed by this etching using a vapor phase selective growth method or a molecular beam growth method ( (FIG. 4 (d)). Thereafter, as already described in detail in the embodiment of the first manufacturing method,
The optoelectronic integrated circuit shown in FIG. 3 is manufactured by a general manufacturing process.

As described above, in the first manufacturing method, the optical element layer 1 is formed below the step of the semi-insulating semiconductor substrate 10 having the step, the electronic element layer 2 is formed above the step, and the optical element layer is further formed. The trench 19 at the boundary between the semiconductor device 1 and the electronic element layer 2 is selectively buried in the semiconductor layer 20 so that the step of the wafer is 1 μm.
In contrast to the conventional method of manufacturing an optoelectronic integrated circuit having a step of 5 μm or more, the pattern defect of the photoresist at the step is improved, and the thin film resist can be used. The fine gate electrode 26 of 1 μm or less has good reproducibility.
Good controllability is obtained. Therefore, a high-yield and high-performance optoelectronic integrated circuit can be obtained. In the second manufacturing method, the optical element layer 1 is formed on a part of the flat semi-insulating semiconductor substrate 10, and a high-resistance semiconductor is formed in a region on the semi-insulating substrate 10 where the optical element layer 1 is not formed. A layer 29 and an electronic element layer 2 are laminated and formed;
Further, by selectively filling the groove 19 at the boundary between the optical element layer 1 and the electronic element layer 2 with the semiconductor layer 20, the step of the wafer can be suppressed to 1 μm or less. Second
Also in the manufacturing method of (1), a high-yield and high-performance optoelectronic integrated circuit can be obtained for the same reason as in the first manufacturing method.

In the above-described embodiments, examples of dimensions are also shown. However, it is needless to say that appropriate dimensions should be adopted together with crystal growth since the state of crystal growth varies greatly depending on the growth method and conditions. There is no limitation on the types of electrode metal and wiring metal. Although GaAs MESFETs were used for electronic devices, InP-based transistors such as AlGaAs / InGaAs MESFETs and junction type FETs
・ MISFET, etc. may be used.
It is apparent that a semiconductor laser, a waveguide type optical switch, or the like may be used instead of the N photodiode, without further detailed description.

〔The invention's effect〕

As described above in detail, according to the present invention, in any of the first manufacturing method and the second manufacturing method, it is possible to suppress the step of the wafer of the optoelectronic integrated circuit to 1 μm or less, Compared with the conventional method of manufacturing an optoelectronic integrated circuit having a step of 5 μm or more, the pattern failure of the photoresist at the step is improved, and the reproducibility and controllability of forming a fine gate electrode of 1 μm or less in the electronic element are improved. An improved, high-yield, high-performance optoelectronic integrated circuit is obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an optoelectronic integrated circuit manufactured by a first manufacturing method according to a first embodiment of the present invention, and FIGS. 2 (a) to 2 (d) show a main part thereof. It is a manufacturing process figure showing a wafer flattening process. FIG. 3 is a sectional view of an optoelectronic integrated circuit manufactured by the second manufacturing method of the second embodiment, and FIG. 4 (a).
(D) are manufacturing process diagrams showing a wafer flattening process which is a main part thereof. In the figure, 1 is an optical element layer, 2 is an electronic element layer, 3 is a PIN
Photodiode, 4 is a field effect transistor (FET), 1
0 is a semi-insulating semiconductor substrate, 11 is a first buffer layer, 12
Is a second buffer layer, 13 is a light absorbing layer, 14 is a window layer, 15 is a mask, 16 is a strain buffer layer, 17 is an active layer, 18
Is a mask, 19 is a groove, 20 is a buried semiconductor layer, 21 is a p-type inversion region, 22 is a p-electrode, 23 is an n-electrode, 24 is a source electrode, 25
Is a drain electrode, 26 is a gate electrode, 27 is a passivation film, 28 is a wiring, and 29 is a high-resistance semiconductor layer.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References IEEE Photonics Technology Letters Vol. 2, No. 10PP. 721-3 [1990] IEEE Transactions on Electron Devices, Vol. ED-34, no. 2P. 241-6 [1987] Applied Physics Letters Vol. 48, No. 21 p. P. 1461-3 [1986]

Claims (2)

(57) [Claims] In a method of manufacturing an optoelectronic integrated circuit in which an optical element and an electronic element are monolithically integrated on a substrate, a step of forming an optical element layer below a step of a semi-insulating semiconductor substrate having a step. Forming an electronic element layer above the step of the semi-insulating semiconductor substrate, and flattening the wafer by selectively filling a groove at a boundary between the optical element layer and the electronic element layer with a semiconductor layer. A method for manufacturing an optoelectronic integrated circuit, comprising the steps of: 2. A method of manufacturing an optoelectronic integrated circuit in which an optical element and an electronic element are monolithically integrated on a substrate, wherein an optical element layer is formed on a part of a flat semi-insulating semiconductor substrate. Forming a high-resistance semiconductor layer and an electronic element layer in a region on the semi-insulating substrate where the optical element layer is not formed, and forming a groove at a boundary between the optical element layer and the electronic layer. A step of flattening the wafer by selectively embedding the semiconductor device in a semiconductor layer.