JPH0612809B2 - Method for manufacturing optoelectronic integrated circuit - Google Patents

Description

The present invention relates to a method for manufacturing an optoelectronic integrated circuit.

(Conventional Technology and Its Problems) With the progress of optical communication technology, its application field is rapidly expanding from the backbone transmission system to the subscriber system, LAN, data link and other systems. In order to respond to such sophistication of optical systems, higher performance and higher functionality of optical devices are indispensable.

Optoelectronic integrated circuits are one of the key devices at the core of these optical systems. Therefore, in addition to the basic advantages of integration such as low price, small size, high reliability, and no adjustment, the performance improvement of optical devices such as high speed and high sensitivity, as well as the high performance to support future optical systems such as optical wiring and optical switching. Development of optoelectronic integrated circuits is being energetically carried out with the aim of realizing functional and new functional devices.

In order to improve the performance of an optoelectronic integrated circuit, a fine electrode forming process technology capable of forming a gate electrode of 1 μm or less with high reproducibility is required in an electronic element used. When manufacturing an optoelectronic integrated circuit, a step difference of several μm occurs in the wafer due to the difference in the layer structure between the optical element and the electronic element. For this reason, when an optoelectronic integrated circuit is manufactured by using a normal photolithography technique, the mask pattern spreads to 1 μm.
It is difficult to form the following fine patterns. In order to solve the spread of this pattern, a method is known in which a stepped substrate is used, an optical element is formed below the step and an electronic element is formed above the step, and the heights of the optical element and the electronic element are matched. Examples of such an optoelectronic integrated circuit having a step structure include Teramon et al.
There is an invention of Japanese Patent Application No. 62-072053, which is a name invention.

However, in this conventional example, although the heights of the optical element and the electronic element are the same, since the optical element has a mesa structure and there is a step difference of about several μm in the wafer, there is a break in the resist at the step difference. Pattern defects are likely to occur. In order to prevent this pattern failure, a thick film resist having a thickness of about 2 μm is used in the electrode forming process. However, when a thick film resist is used, it is difficult to form a gate electrode having a gate length of 1 μm or less with good reproducibility, so that it is difficult to improve the performance of the transistor and there is a large variation in the characteristics. As a result, not only sufficient device characteristics cannot be obtained as an optoelectronic integrated circuit, but also the characteristics are not uniform.

An object of the present invention is to eliminate these drawbacks and to provide a manufacturing method capable of obtaining a high-performance optoelectronic integrated circuit with good reproducibility.

(Means for Solving Problems) In order to solve the above problems and achieve the above object, the method for manufacturing an optoelectronic integrated circuit provided by the present invention is formed below a step of a substrate having a step. In a method for manufacturing an optoelectronic integrated circuit in which an optical device and a transistor formed above a step are monolithically integrated, a step is formed by etching a part of a substrate to form the step lower portion and the step upper portion. Is provided on the substrate, a semiconductor layer for optical devices is formed below the step of the substrate, and a semiconductor layer for transistors is formed on the step of the substrate to planarize the wafer, and the optical device and the optical device. After forming a thick film resist with a thickness of 1 μm or more so as to cover the step area between the transistor and the transistor, photolithography using a thin film resist with a thickness of 1 μm or less By the technique 1
a step of forming a gate electrode of a transistor having a gate length of μm or less, wherein a depth of the step formed by the etching is a difference between a thickness of a semiconductor layer of the optical device and a thickness of a semiconductor layer of the transistor. ± 1 μm
It is characterized by being within the range.

(Operation) According to the present invention, a stepped portion of a substrate having a step is covered with a thick film resist, and then a thin film resist is used to form an electrode pattern of a transistor, so that a fine electrode of 1 μm or less can be reproducibly manufactured. Is possible. Therefore,
By adopting the method of the present invention, it becomes possible to reduce the gate length to 1 μm or less while maintaining uniformity within the wafer.
High performance and high yield of transistors are achieved, and as a result, high performance optoelectronic integrated circuits can be manufactured with good reproducibility.

(Example) Next, a manufacturing method of an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of an optoelectronic integrated circuit manufactured by the method of the embodiment, and FIGS. 2A to 2C are particularly fine patterns in the manufacturing process of the optoelectronic integrated circuit of this embodiment. FIG. 6 is a process diagram illustrating a method of forming a gate electrode of a transistor that needs to be formed. That is, the manufacturing method of the present invention is a manufacturing method of the optoelectronic integrated circuit described in the above-mentioned Japanese Patent Application No. 62-072053, which is a conventional example, and in particular, a new photo that can form a fine pattern of 1 μm or less. It provides a method of lithography. The manufacturing method will be described below.

First, an etching mask made of SiO ₂ is formed on a part of the semi-insulating substrate 1, and the substrate is etched with a mixed solution of HCl and H ₃ PO ₄ to form a 2.8 μm step.
After removing the etching mask, the contact layer 4 made of n-type InP (thickness: 1.5 μm, carrier concentration: 1 × 10 ¹⁸ ) was formed on the semi-insulating InP substrate 1 by liquid phase or vapor phase growth.
cm ⁻³ ), n-type In _0.47 Ga _0.53 As light absorption layer 5 (thickness 1.5 μm, carrier concentration 2 × 10 ¹⁵ cm ⁻³ ), n-type InP
Window layer 6 (thickness 1 μm, carrier concentration 2
× 10 ¹⁵ cm ^-3 ). Next, the PIN photodiode portion 2 is left, and the window layer 6, the light absorption layer 5, and the contact layer 4 are mesa-etched to expose the semi-insulating InP substrate 1. For etching the light absorption layer 5, H ₂ SO ₄ , H ₂ O ₂ and H ₂ O _{2 are used.}
Is used as a mixed solution of HCl and H ₃ PO ₄ for etching the window layer 6 and the contact layer 4. Further, a mask made of SiO ₂ is applied to the PIN photodiode part 2, and a strain buffer layer 7 made of GaAs (thickness 1.0 μm, non-doped) by using a vapor phase growth method or a molecular beam growth method, an active layer made of n-type GaAs. 8 (thickness 0.2 μm, carrier concentration 1 × 10 ¹⁷ cm
^-3 ) form. Next, after removing the active layer 8 and the strain buffer layer 7 on the PIN photodiode part 2, selective zinc diffusion is performed using a mask 15 made of SiO ₂ to form a p-type inversion region 9, and a source electrode made of AuGeNi. 12, drain electrode 13, photodiode n-electrode 11, AuZn photodiode p-electrode 10, Al gate electrode 14, Ti / Au
The wiring 16 is formed to complete the optoelectronic integrated circuit of this embodiment (FIG. 1). Particularly, the gate electrode 14 which requires a fine electrode structure of 1 μm or less is formed by a two-layer resist structure as shown in FIGS. 2 (a) to (c). That is,
After forming a thick film resist 17 having a thickness of 2 μm on the step portion by a photolithography technique, a pattern of the gate electrode is formed using a thin film resist 18 having a thickness of about 0.5 μm (FIG. 2 (b)). Next, Al is deposited and the gate electrode 14 is formed by the lift-off method (FIG. 2 (c)).

As described above, the thick film / thin film two-layer resist structure facilitates miniaturization of the gate electrode and enables manufacture of a high-performance transistor having a gate length of 1 μm or less. Therefore, according to the method of this embodiment, an optoelectronic integrated circuit having high performance and good uniformity can be manufactured.

Although the gate electrode of the transistor is Al in the above embodiments, any material other than Al can be used as the material of the gate electrode as long as the Schottky junction can be obtained in the present invention. Further, the thickness of the active layer and the carrier concentration composition may be any as long as they are optimized as an electronic device for optoelectronic integrated circuits, and a two-dimensional electron gas having a heterostructure including AlGaAs mixed crystal is used. Structure, InAl
It may be an InP-based transistor containing As, InGaAs, InGaAsP. The optical device in the optoelectronic integrated circuit to which the manufacturing method of the present invention is applied is a semiconductor laser, a light emitting diode,
Avalanche photodiodes and optical bistable elements,
It may be an optical functional element such as an optical amplifier or an optical switch. Similarly, the electronic circuit in the optoelectronic integrated circuit is not limited to the transistor. For example, it may include a diode and a resistor, and the scale of the integrated circuit may be larger.

(Effects of the Invention) As described above, according to the present invention, in an optoelectronic integrated circuit in which an optical device formed below a step and a transistor formed above the step of a substrate having a step are monolithically integrated, By forming a thick film resist so as to cover the region and then forming an electrode pattern of the transistor using the thin film resist,
It becomes possible to manufacture fine electrodes of m or less with good reproducibility, and as a result, a high-performance optoelectronic integrated circuit can be obtained with good reproducibility.

[Brief description of drawings]

FIG. 1 is a sectional view of an optoelectronic integrated circuit manufactured in an embodiment of the present invention, and FIGS. 2A to 2C are manufacturing process drawings of the embodiment. In the figure, 1 is a semi-insulating InP substrate, 2 is a PIN photodiode, 3 is a field effect transistor, 4 is a contact layer of the photodiode, 5 is a light absorption layer of the photodiode, 6 is a window layer of the photodiode, 7 is a strain buffer layer,
8 is an active layer, 9 is a p-type inversion region, 10 is a p-electrode of a photodiode, 11 is a n-electrode of a photodiode, 12 is a source electrode, 13 is a drain electrode, 14 is a gate electrode, 15 is a SiO ₂ mask, 16 is a wiring , 17 is a thick film resist, and 18 is a thin film resist.

Claims (1)

[Claims] 1. A method of manufacturing an optoelectronic integrated circuit in which an optical device formed below a step of a substrate having a step and a transistor formed above the step are monolithically integrated, and a part of the substrate is etched. The step lower part and the step upper part are provided on the substrate by forming the step difference, the semiconductor layer for an optical device is formed under the step difference of the substrate, and the transistor semiconductor layer is formed over the step difference of the substrate. Thus, after the step of flattening the wafer, and after forming the thick film resist with a thickness of 1 μm or more so as to cover the step region between the optical device and the transistor,
The method includes a step of forming a gate electrode of a transistor having a gate length of 1 μm or less by a photolithography method using a thin film resist having a thickness of 1 μm or less, and the depth of the step formed by the etching is determined by the depth of the optical device. A method of manufacturing an optoelectronic integrated circuit, wherein the difference between the thickness of the semiconductor layer and the thickness of the semiconductor layer of the transistor is within ± 1 μm.