JPH021979A - Manufacture of photoelectric integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a photoelectric integrated circuit of high performance with good reproducibility by a method wherein a semiconductor layer of an optical element and a semiconductor layer of an electronic element are selectively made to grow in crystal to make a wafer flat, an etching is performed to expose a contact layer of the optical element on a substrate side after an electrode of an electronic element has been formed, and an electrode is formed on the above contact layer. CONSTITUTION:A semiconductor layer of an optical element and semiconductor layers 20, 21 and 22 of an electronic element are selectively grown on a semiconductor substrate 10 respectively to make a wafer flat. Next, an electrode of the electronic element is formed. A part of the semiconductor layer of the optical element is removed through etching after the above electrode manufacturing process to expose a contact layer 11. An electrode 30 is formed on the contact layer exposed through an etching process. Thereby, in the electronic component, a fine gate electrode 1mum or less in size can be reproducibly manufactured. Therefore, a gate length can be made 1mum or less being kept excellent in uniformity inside the wafer, and a transistor can be made excellent in performance and yield, consequently an optical electric integrated circuit of high performance can be reproducibly obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing an optoelectronic integrated circuit.

[Conventional technology]

With the progress of optical communication technology, its application fields are rapidly expanding from core transmission systems to systems such as subscriber systems, LANs, and data links. In order to respond to such advances in optical systems, it is essential to improve the performance and functionality of optical devices.

Optoelectronic integrated circuits are one of the key devices at the core of these optical systems. In addition to the basic advantages of integration, such as low cost, small size, high reliability, and no adjustment, we also aim to improve the performance of optical devices, such as faster speeds and higher sensitivity, and to improve the performance of optical devices, such as optical wiring and switching, which will support future optical systems. Optoelectronic integrated circuits are being actively developed with the aim of realizing functional and new functional devices.

In order to improve the performance of optoelectronic integrated circuits, a fine electrode formation process technology that can form gate electrodes of 1 μm or less with good reproducibility is required in the electronic devices used. When manufacturing optoelectronic integrated circuits, a step difference of several micrometers occurs within the wafer due to the difference in layer structure between optical elements and electronic elements. For this reason, when optoelectronic integrated circuits are manufactured using ordinary photolithography techniques, it is difficult to form fine patterns of 1 μm or less due to the spread of the mask pattern. In order to solve this problem of pattern spreading, a method is known in which a stepped substrate is used (1), an optical element is formed below the step, and an electronic element is formed above the step, so that the heights of the optical element and the electronic element are matched. An example of such an optoelectronic integrated circuit having a stepped structure is the invention disclosed in Japanese Patent Application No. 1982-62072053 by Terakado et al.

[Problem to be solved by the invention]

However, in this conventional example, although the heights of the optical element and the electronic element are the same, the optical element has a mesa structure and there is a step difference of several μm within the wafer, so resist cuts may occur at the step part. It is easy to cause pattern defects due to this. In order to prevent this pattern failure, two steps are taken in the electrode formation process.
A thick film resist having a JW depth of about μm was used.

However, if a thick film resist is used, the gate length will be 1 μm.
It is difficult to form the following gate electrodes with good reproducibility, which makes it difficult to improve the performance of FETs, and furthermore, the characteristics vary widely. As a result, not only was it not possible to obtain sufficient device characteristics as a photoelectron <, p 1 circuit, but there was also a drawback that the characteristics lacked uniformity.

An object of the present invention is to provide a manufacturing method that eliminates these drawbacks and allows high-performance optoelectronic integrated circuits to be obtained with good reproducibility.

[Means to solve the problem]

In order to solve the above problems and achieve the above objects, the present invention provides a method for manufacturing an optoelectronic integrated circuit, which is a method for manufacturing an optoelectronic integrated circuit in which an optical element and an electronic element are monolithically integrated on the same substrate. The method includes a step of selectively growing crystals of the semiconductor layer of the optical device and a semiconductor layer of the electronic device on a semi-insulating substrate and flattening the wafer, a step of forming electrodes of the electronic device; The method is characterized in that it includes an etching step of removing a part of the semiconductor layer of the optical element to expose a contact layer after the electrode forming step, and a step of forming an electrode on the contact layer exposed in the etching step.

[Effect]

In the present invention, the semiconductor layer of the optical device and the semiconductor layer of the electronic device are selectively crystal-grown, the wafer is flattened, and the contact layer on the substrate side of the optical device is exposed after forming the gate electrode of the electronic device. By etching and forming electrodes on the contact layer, the thickness of 1 μm can be achieved in electronic devices.
It becomes possible to manufacture the following fine gate electrodes with good reproducibility. Therefore, by adopting the method of the present invention, it is possible to reduce the gate length to 1 μm or less while maintaining uniformity within the wafer, thereby achieving high performance and high yield of transistors, and as a result, high performance optoelectronic integrated circuits. Can be manufactured with good reproducibility.

〔Example〕

Next, a manufacturing method according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a photoelectronic 4LVi manufactured by the method of the example.

It is a sectional view of a circuit, and is an example in which a semiconductor laser 1 and a field effect transistor 2 are integrated. FIGS. 2(a) to 2(d) are manufacturing process diagrams of the optoelectronic integrated circuit of this example. First, n-I is deposited on a semi-insulating semiconductor substrate 10 made of InP by a liquid phase growth method, a vapor phase growth method, a molecular beam growth method, etc.
First contact layer 11 made of nGaAsP (thickness 0
．． 5μm, carrier concentration 5 x 1018cm-')
, n - [nP first cladding layer 12 (thickness 1
．． 0 μm, carrier concentration 5 × 10 “cm-’)
, an active layer 13 made of InGaAsP (thickness 0.1JJ
, m, non-doped), second cladding layer 14 made of P-1nP (thickness 1.5 μm, carrier concentration 5×10
18 cm-') and mesa-etched the second cladding layer 14 and active layer 13, a first current blocking layer 15 made of p-InP (thickness 0.5 μm, carrier concentration 5×10” cm) was grown. -'), a second current blocking layer 16 made of nInP (thickness 0.5 μm, carrier concentration I x 10 "am-3>", p=buried layer 17 made of InP (thickness 1.0 μm, carrier concentration 1
A second contact layer 18 (thickness 0.5 μm, carrier concentration 5 x 10'8 cm-') made of p-1nGaAsP is grown to form the buried semiconductor laser 1 ( Figure 1(a)).

Next, one mask made of 5i02 is applied to form the semiconductor laser 1 into a mesa stripe to expose the semi-insulating semiconductor substrate 10, and then InP is formed by vapor phase epitaxy or molecular beam epitaxy.
The first high-resistance layer 20 (thickness 1.5 am, F
e-doped), the second high-resistance layer 21 made of GaAs (
1.5 μm thick, non-doped), active layer 22 made of n-GaAs (0.3 μm thick, carrier concentration I×1
0 "cm-') and planarize the wafer (
Figure 2(b)). Next, the active layer 22 is selectively etched away, and the field effect transistor (FET) forming region 23 is etched away.
compartmentalize. After forming the dielectric film 24, the first electrode 28 of the semiconductor laser 1 made of AuZn, the source electrode ji 25, the drain electrode 26, and the input 1 of the FET 2 made of AuGeNi are formed.
A gate electrode divided by 27 is formed (FIG. 2(C)).

Next, active; the semiconductor layer 1 of the semiconductor laser 1 near 113;
8°17.16, 15.12 are etched away and groove 2
9 is formed, and the first contact layer 11 is exposed. First contact layer 1 exposed in the trench after forming the dielectric 131
A second electrode 30 made of AuGeNi is formed on the substrate 1 (FIG. 2(d)). Finally, wiring 3 made of Ti/Au
2, and the optoelectronic integrated circuit of this example is completed (FIG. 1).

In this way, the semiconductor layer of the optical device and the semiconductor layer of the electronic device are selectively crystal-grown, the wafer is flattened, and the contact layer on the substrate side of the optical device is exposed after forming the electrodes of the electronic device. By etching and forming an electrode on the contact layer, it is easy to miniaturize the electrode to 1 μm.
It becomes possible to manufacture high-performance transistors having gate lengths of: Therefore, by the method of this embodiment, a high-performance optoelectronic integrated circuit can be manufactured with good reproducibility.

Incidentally, in the above-mentioned embodiment, an example of dimensions was shown, but since the state of crystal growth varies greatly depending on the growth method, conditions, etc., it goes without saying that appropriate dimensions should be adopted along with these. Furthermore, there are no restrictions on the types of electrode metals and wiring metals. GaAs MESFET was used for the electronic device, but InP
system transistors such as AlGaAs/InGaAs M
E S F E T, Junction FET, M I 5FE
It is obvious that a PIN photodiode, a waveguide type optical switch, etc. may be used instead of a semiconductor laser for the optical element, without needing to explain it in detail. .

[Effects of the Invention] As described in detail above, according to the present invention, the semiconductor layer of the optical device and the semiconductor layer of the electronic device are selectively grown by crystal growth to flatten the wafer, and the electrodes of the electronic device can be flattened. By etching to expose the contact layer on the substrate side of the optical device after formation and forming an electrode on the contact layer, it is easy to miniaturize the electrode and manufacture a high-performance transistor with a gate length of 1 μm or less. becomes possible. Therefore, by the method of this embodiment, a high-performance optoelectronic integrated circuit can be manufactured with good reproducibility.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an opto-electronic integrated circuit manufactured according to an embodiment of the present invention, and FIGS. 2(a) to 2(d) are manufacturing process diagrams of the embodiment. DESCRIPTION OF SYMBOLS 1... Semiconductor laser, 2... Field effect transistor (FET), 10... Semi-insulating semiconductor substrate, 11...
- First contact layer, 12... first cladding layer,
13... Active layer, 14... Second cladding layer, 15
...first current blocking layer, 16...second current blocking layer, 17...buried layer, 18...second contact layer, one...mask, 20...th 1 high resistance layer, 21... second high resistance layer, 22... active layer,
23... FET formation region, 24... dielectric, 25...
...Source electrode, 26...Drain electrode, 27...
Gate electrode, 28 Stomach-first electrode, 29... Groove, 30
...Second electrode, 31...Dielectric material, 32...Wiring. Agent Patent Attorney Uchihara Otoni 1 Diagram Z Diagram

Claims (1)

[Claims] A step of selectively growing crystals of a semiconductor layer of an optical device and a semiconductor layer of an electronic device on a semi-insulating substrate and flattening the wafer, a step of forming electrodes of the electronic device, and a step after this electrode forming step. An optoelectronic integrated circuit comprising: an etching step of removing a part of the semiconductor layer of the optical element to expose a contact layer on the substrate side; and a step of forming an electrode on the contact layer exposed in the etching step. manufacturing method.