JPS63157439A - Multilayer interconnection structure in through hole - Google Patents

Abstract

PURPOSE:To reduce the number of necessary through holes, eliminate the limitation of a through hole diameter, and manufacture excellently a mutilayer interconnection structure, by applying a multilayer structure to the wiring of through holes. CONSTITUTION:Wiring in the through hole 21 of a P-Si substrate 20 is formed as a multilayer structure wherein the respective wiring layers 24, 26 and 20 are stacked via the respective insulative layers 24, 2b and 28. On extending parts 26a, 26b, 28a and 28b to a rear surface 23, connection parts 35-38 to other wirings are formed so as to reach the surface 22 of the multilayer interconnections 24, 26 and 28. The wiring of through hole 21 is formed as a multilayer structure, and the number of necessary through holes 21 is reduced. Thereby the limitation of the diameter of through hole 21 is eliminated, and the multilayer interconnection structure is excellently manufactured.

Description

[Detailed Description of the Invention] (Summary) The present invention provides a multilayer wiring structure in a through hole, in which the wiring in the through hole is made into a multilayer structure, thereby reducing the number of through holes and enabling fine wiring on the surface of the substrate. It is something.

[Industrial application field]

The present invention relates to a multilayer wiring structure within a through hole.

[Conventional technology]

The present inventor has previously proposed a semiconductor device of the V4 structure, in which a plurality of semiconductor device chips 2.3.4 are stacked on a semiconductor mother chip 1, as shown in FIG. 2 (3° 4) is for electrical connection between the semiconductor device chip stacked on the upper side and the semiconductor device chip on the lower side, and for electrical connection with the semiconductor device section 5 within the semiconductor device chip itself. It has internal wiring for making connections. The internal wiring is one wiring per through hole on the board. 1st
In the figure, 6.7.8 is a through hole, and 9° and 10.11 are internal wirings of a single layer structure within the through hole 6.7.8, respectively.

[Problem that the invention seeks to solve]

Therefore, the same number of through holes as those required for the above-mentioned electrical connections are formed in the semiconductor device chip 2 (3, 4>). These through holes are formed, for example, by etching.

In this case, especially the substrate of semiconductor device chip is 400 to 5
When the thickness is 00 μm, it is particularly difficult to reduce the diameter of the through holes and narrow the distance between adjacent through holes.

As described above, due to the large number of through holes and the wide spacing between the through holes, there was a problem in that the wiring on the surface of the semiconductor device chip 2 (3, 4) could not be made fine.

[Means for solving problems]

The multilayer wiring structure in the through hole of the present invention has a multilayer structure in which the wiring in the through hole of the substrate is laminated with each of a plurality of wiring layers via an insulating layer, and the surface of the substrate of each wiring layer and A connecting portion with other wiring is provided on the extending portion onto the back surface.

[Effect]

By forming the wiring inside the through hole into a multilayer structure, the number of through holes required is reduced, restrictions on the diameter are relaxed, and through holes are easier to form.

Each distribution I! By providing connection parts with other wiring on the extensions to the front and back surfaces of the i1 layer board, it is possible to place the connection parts closely together, making it possible to miniaturize the wiring layers on the front and back sides. becomes.

〔Example〕

FIG. 1 shows an embodiment of the multilayer wiring structure in the through hole of the present invention, FIGS. 2(A) to (G) show the manufacturing process of the multilayer wiring structure, and FIG. This figure shows a semiconductor device chip (semiconductor device) to which a multilayer wiring structure in holes is applied.

The multilayer wiring structure shown in FIG. 1 will be explained along with its manufacturing process.

First, as shown in Fig. 2<A), the thickness t is 300 to 50.
A through hole 21 is formed in the O-8i substrate 20 of 0 μm by etching, for example. Since the wiring has a multilayer structure, the number of through holes 21 may be small, for example, one, and the diameter d of the through hole 21 may be large, so that the through hole 21 can be easily formed. In addition, the board 2
A semiconductor device portion (not shown) is formed in the portion 0.

Next, as shown in FIG. 2(B), an n+ diffusion layer 24 is formed on the inner peripheral surface of the through hole 21 and on the front surface 22 and back surface 23 of the substrate 20 near the opening of the through hole 21.

This constitutes the first wiring layer.

Next, thermal oxidation is performed, as shown in FIG. 2(C),
The 5iOz film 25 as the first insulating layer is inserted into the through hole 2.
1 and the front and back surfaces of the substrate 20.

Next, CVD is performed, and as shown in FIG. 2(D), S! Doped polysilicon is deposited on 02j025, and doped polysilicon 126 as a second wiring layer is formed on the inner peripheral surface of the through hole 21 and on the front and back surfaces of the substrate 20.

Next, thermal oxidation is performed to coat the entire surface of the film 26.
That is, as shown in FIG. 2(E), a 5fO2 film 2 is formed as a second insulating layer on the inner peripheral surface of the through hole and on the upper and lower surfaces of the substrate.
form 7. As a result, the doped polysilicon film 2
6 is sandwiched between 5iOz1025.27 from above and below.

Next, CVD is performed again to deposit doped polysilicon on the 5tO2 film 27 and form a doped polysilicon film 28 as a third wiring layer, as shown in FIG.
are formed on the inner peripheral surface of the through hole 21 and on the front and back surfaces of the substrate.

In this case, since diffusion, thermal oxidation, and CVD are used as the film forming method, the length of the through hole 21 (thickness tl of the substrate 20, :':!) as shown in FIG. 2(A). Even if the length of the
l! 25 to 28 are also reliably formed on the inner peripheral surface of the through hole 21.

Next, as shown in FIG. 2(G), the through hole portions are plated with ΔU (or P b /S n ) to form two Au layers as final wiring layers.

Next, as shown in FIG.
3, contact holes 31 to 34 are formed by selectively etching predetermined locations near the openings of through holes 21, pads 35 to 38 as connection parts are formed, and pads 35 to 38 and the Au layer 29 are formed. Upper and lower ends 29a, 29 of
Insulating layers 39 and 40 made of PSG are formed except for b.

Pads 35 and 36 are each doped polysilicon IE12.
6.28 extending portion 26a toward the substrate surface 22 side.

It is provided at 28a. Other pads 37 and 38 are provided on extending portions 26b and 28b of doped polysilicon 126 and 28 toward substrate back surface 23, respectively.

A pad 35 on the front surface of the substrate 20 and a pad 37 on the back surface are connected by a doped polysilicon film 26. Pad 36 and pad 38 are made of different doped polysilicon m.
28. Upper end 29a and lower end 29
b is electrically connected to ALIvA 29 itself within the through hole 21.

Furthermore, as shown by the two-dot chain line in FIG.
6 and an end portion 29a, etc., and the other end is connected to a semiconductor device portion (not shown) on the substrate 20. A bump (not shown) for chip stacking is formed at the other end of a portion of the surface wiring 41. Similarly, board 2o
The surface wiring 42 is also connected to the back surface 23 side, one end of which is connected to the pad 3.
7.38, end portion 29b, etc. A bump (not shown) for chip stacking is formed at the other end.

), the pads 35 to 38, and the upper and lower ends 29a.

29b are arranged close to each other with a relatively degree of freedom,
Both the front wiring 41 and the back wiring 42 are formed finely.

Particularly regarding the pads 35 to 38, they can be placed at positions where connection is easy in relation to the other party to which they are connected, and the front wiring 41 and the back wiring 42 can be structured to be easy to pattern.

As a result of the above, the internal wiring has a multilayer structure as shown in Figure 3.
A semiconductor device chip 50 is obtained.

This semiconductor device chip 50 is mounted on a semiconductor mother chip 51 using bumps 52 and 53, as shown in FIG. Furthermore, semiconductor device chips 54 and 55 having substantially the same structure as the chip 50 are stacked and mounted on the chip 50, thereby forming a three-layered semiconductor device 56.

In addition, 5IO by thermal oxidation shown in FIGS. 2(C) and (E)
Instead of the z film 27, a 5isN4 film formed by CVD may be used. Also, FIG. 2(D).

Instead of the doped polysilicon films 26 and 28 shown in (F), a silicide film such as tungsten silicide formed by CVD may be used. Also, Pb instead of AUU2O5
/5nliW, and in this case, flattening may be performed by beam flow.

〔Effect of the invention〕

According to the present invention, since the wiring inside the through hole has a multilayer structure, the number of through holes can be reduced compared to the conventional single layer fS structure, and the diameter of the through hole can be limited. It is possible to easily form through-holes, and since multiple connection parts are placed close together, it is possible to form fine wiring on the surface. It is effective when applied to semiconductor device chips.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the multilayer wiring structure in the through hole of the present invention, FIGS. 2(A) to (G) are diagrams showing the manufacturing process of the multilayer wiring structure in the through hole, and FIG. 3 4 is a diagram showing a semiconductor device in which the multilayer wiring structure in the through ball of FIG. 1 is applied as internal wiring, and FIG. 4 is a diagram showing a semiconductor device in which the internal wiring has a single layer structure. In the figure, 2o is a p-8i substrate, 21 is a through hole, 22 is a front surface, 23 is a back surface, 24 is an n+ diffusion layer, 25.27 is a SiO2 film, 26.28 is a doped polysilicon film, 26a, 26b
, 28a, 2sb are extension parts, 29 is an Au layer, 31 to 34 are contact balls, 35 to 38 are pads, 39.40 are insulating layers, 4゛1 is a surface layer 8 layer, 42 is a back layer IIA layer , 50, 54, and 55 are semiconductor device chips, and 56 is a semiconductor device. Figure 2 (1)

Claims (1)

[Claims] Each of the plurality of wiring layers (24, 26, 28) connects the wiring in the through hole (21) of the substrate (20) with an insulating layer (25,
27), and other wirings are formed in the extending portions (26a, 26b, 28a, 28b) of each wiring layer onto the front surface (22) and back surface (23) of the substrate. A multilayer wiring structure inside a through hole, which is provided with connection parts (35 to 38).