JPS629646A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the yield from deteriorating on account of repeated wiring processes by means of reducing the wiring layers formed in an integrated circuit substrate by a method wherein a wiring substrate with wiring layers is isolated from an integrated circuit substrate with active element. CONSTITUTION:A wiring substrate 13 with wiring layers 14 is positioned on an integrated circuit substrate 11. After positioning, the electrodes of both substrates 11, 13 are electrically conducted by conductors 15 using thermal pressure fixing process etc. to produce a semiconductor. In such a constitution, the wiring substrate 13 with specified wiring layers 14 preliminarily produced is utilized as the wiring layer of a semiconductor device so that the wiring may be performed without deteriorating the yield in semiconductor manufacturing process as well as the space of active element part may be expanded on the chip surface.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing semiconductor devices such as ICs and LSIs.

BACKGROUND OF THE INVENTION Progress in integration technology for semiconductor devices such as LSIs has led to increased density of semiconductor devices and a tendency to increase the number of interconnections between active elements such as transistors and diodes. An increase in the number of wires results in an increase in the area occupied by the wires within one semiconductor device (one chip). The end of Song, ゛F! - resulting in a reduction in the area of active component parts within the conductor arrangement.

As a countermeasure against this problem, the wiring is made into a multilayer structure to increase the area occupied by active elements within the semiconductor device.

The following process is generally used to obtain a multilayer wiring structure. As shown in FIG. 3, first, the semiconductor substrate 1
A first wiring 13 is formed through the first insulating film 2, then a second insulating film 4 is formed, and then the first wiring layer 3 and the second wiring layer 5 to be formed next are formed. In order to obtain an electrical connection between the layers, a through hole is formed in the second insulating film 4 by etching, and then a second wiring layer 5 is formed.

Many techniques have been proposed in such a multilayer wiring process. This technology is roughly divided into the following two types. That is, the insulating layer 2.4 is formed flat and the wiring layer 3.5 is formed flat.
technology to flatten the surface, and technology to obtain electrical connections in the living room. Techniques for flattening wiring include a method of coating with resin, a method of applying heat-resistant resin such as polyimide/ladder silicone, and a method of flattening wiring steps, and a method of applying heat-resistant resin such as polyimide/ladder silicone. There is a method of improving the electrical properties by compositing.Also, as a method using positive oxidation, there is a method of covering AQ with a resist and partially oxidizing it to transform it into alumina. As a method to use,
There is a method in which lead-based glass is used to provide fluidity and flatten it at a low temperature (800° C.). In addition, as a method using etchback, a living room insulation film is deposited to a thickness greater than the wiring step,
There are methods of flattening the resist by etching after applying it, and methods of flattening the resist by utilizing etching selectivity depending on the shape of the silicon nitride film. Further, as a bias sputtering method, there is a method in which deposition and re-sputtering are simultaneously caused by an RF sputtering method with a DC bias applied to flatten a step. Further, as a list-off method, there is a method in which an insulating film is buried using a resist on which wiring has been formed as a mask, and the resist is removed and planarized. Next, as a technique for obtaining electrical connections between layers, there is an interlayer connector method (embedding method), which is a method of embedding metal using the same process as the wiring forming process to connect between layers. In addition, as a method for improving through-holes, there is a method of improving the material of the living room insulating film and the etching method of wiring to make the dimensions of the through-hole larger than the dimensions of the wiring pad.

Problems that the invention aims to solve When integrating high-density transistors on the same chip, multilayer wiring technology is effective, but as the number of layers increases, photomasks and photomasks in the active element manufacturing process are effective. The number of masks is approximately the same as the number of photomasks in the wiring manufacturing process. As a result, LSI! The yield during eJ manufacturing will be extremely low.

The present invention solves the above-mentioned conventional problems, and provides a method for manufacturing a semiconductor device that can prevent a decrease in yield when wiring is multiplied and can increase the active element forming area within a chip. With the goal.

Means for Solving the Problems In order to solve the above-mentioned problems, the method for manufacturing a semiconductor device of the present invention provides an integrated circuit in which a wiring board having a predetermined wiring layer manufactured in advance is integrated with semiconductor elements in the same semiconductor. The electrodes are positioned and arranged on a circuit board, and the electrodes of the arranged board and the integrated circuit board are bonded.

According to the above method, a wiring board having a predetermined wiring layer that has been subjected to V3ii in advance is used for wiring AWI of a semiconductor device, so wiring can be performed without reducing the yield in the semiconductor manufacturing process, and active elements can be placed on the chip surface. The area of the part can be expanded.

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 and 2.

1 and 2 are cross-sectional views of a semiconductor device in a process of a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which 11 is an integrated S circuit board on which a C-MO8 circuit is formed;
2 is an electrode formed on the integrated circuit board 11; 13 is a wiring Il;
The l board 14 is the arrangement lll1i formed on the arrangement m board 13.
! 1, the end of this arrangement 114 constitutes an electrode. 15 is a conductor at the joint.

In manufacturing, first, as shown in FIG. 1, a wiring board 13 having a wiring layer 14 is positioned and arranged on an integrated circuit board 13. After this positioning, the inner board 11.13
Electrical continuity is established between the electrodes by a conductor 15 using a thermocompression bonding method or the like. In this way, a semiconductor device as shown in FIG. 2 is obtained.

Effects of the Invention As described above, according to the present invention, since the wiring board having the wiring layer and the integrated circuit board having the active elements are separated, it is possible to reduce the amount of interconnections l1III occupied within the integrated circuit board. The area occupied by the active elements can be expanded, and at the same time, it is possible to prevent a decrease in yield due to repeating the wiring process.

[Brief explanation of drawings]

1 to 2 are cross-sectional views of a semiconductor device in each process of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG.
The figure is a cross-sectional view of a conventional semiconductor device. 11... Integrated circuit board, 12... Electrode, 13...
Layout l1l) 3 boards, 14... Wiring layer agent Yoshihiro Morimoto Figure 1 Figure 2

Claims (1)

[Claims] 1. A wiring board having a predetermined wiring layer manufactured in advance is positioned and arranged on an integrated circuit board in which semiconductor elements are integrated in the same semiconductor, and the wiring board and the integrated circuit board are connected to each other. A method for manufacturing a semiconductor device that connects electrodes. 2. Claim 1, in which the wiring layer of the wiring board is multilayer
A method for manufacturing a semiconductor device according to section 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the integrated circuit board has no electrical connections.