JPS63157254A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To protect the storage contents of a RAM when a power supply is cut off by transferring collectively data to an EEPROM from the RAM with stand-by start within the RAM. CONSTITUTION:When the power supply voltage drops, a power supply voltage detecting circuit 31 detects this voltage drop and a stand-by control circuit 30 is started to send a control signal to a nonvolatile RAM 24. Then all storage contents of a RAM 24a storing various data within the RAM 24 are collectively transferred to a rewritable ROM 24b by the control signal. These storage contents are held although the power supply of a computer is completely cut off.

Description

[Detailed description of the invention]

〔Republic〕 The invention is a microphone

[J combination l- evening, non-volatile + I
It has a built-in UItAM, and the standby IF, 11, allows CPU access in the volatile RAM. Preserves the memory contents of Dansuke's RAM
, G. [Field of Application of PL Industry 1] The present invention relates to a single-chip microphone [1:1 amplifier], and relates to a single-chip microphone [1] having a built-in CPU, ROM, and RAM. Single-chip microphone 1]: "Nbi L-Y is East 16 circuit 1 chip contains C1) Ll, ROM, RAM, I10
All boats etc. are included. (Prior art) Conventionally, single f-tub microphones []'' have been equipped with complementary MOS (referred to as 1ζrC-MO).
There is a microcomputer with a configuration called 8J). In a micro combination coater with a C-MO8 configuration, a standby control circuit is provided to control the microphone 11 input:
1-CPU when no further operation is required. By stopping the operation of the clock generator, etc., the current consumption of the microcombination unit 1 is reduced from several TrLA during normal operation to several μ8! I'm here. [Problems to be solved by the invention] However, in the conventional single-chip microcombicoater, when the power supply is completely cut off, the internal + & R
4゜゜　　tP1 source cut-off In O) When trying to protect the RAM memory contents, the microcomputer will have a non-volatile t'1. It is conceivable to connect RAM. What is non-volatile RAM? Static RAM and Electrically Erasable ROM
It is a memory that can transfer data between the two. However, even with the above configuration, electrically erasable
Approximately 10g+scc is required to transfer the data to the ROM, and the control of the data transfer is controlled by the microphone [1] microphone C.
Must be done in the PU. After detecting a drop in the power supply voltage, it takes a certain amount of time to generate a data transfer control signal in CP tJ, and when data transfer in the non-volatile t'lRAM is started by this,
At trn where this data transfer ends -hlI≦! Electric 1F
There was a problem in that there was a risk that the static 17ΔM memory contents could not be protected because the static 17ΔM would drop to OV. The present invention has been developed in view of the above problems, and it is an object of the present invention to provide a single-chip microcombi-L-2 that protects the memory of RAM 113 when the power is cut off.
1 target. [Means for Solving the Problems] The single-chip microcomputer of the present invention uses C
F) LJ (21) with Akbis III function RAM (24a)
) and RAM (24a) compatible rewritable ROM
Non-volatile Rf'lR that performs batch Y-data transfer with (24b)
A single-run RAM that has an AM (2'l) and can be accessed by the CPU (21) by activation of the standby control circuit (30).
(24a) ROM (24a) whose storage data can be updated
b) Transfer them all at once. (Function) In the present invention, when the lightning source voltage drops and the standby control circuit (30) is activated by the detection signal, the non-volatile RAM (24) is configured and the CPU (21) is activated.
) is a RAM that stores various data.
The entire storage contents of (24a) also constitute a non-volatile RAM. The data is transferred all at once to the replaceable ROM (24b), and held after the microcomputer's FI source is completely shut off. [Example] Figure 1 shows a single-chip micro-amplifier of the present invention, 1
1. In the figure, the microcomputer 20 has a C-MO8 configuration and is configured with one conductor deep. . The CPU 21 in the microcomputer 20 connects to the ROM 23 . Nonvolatile 11R△M24.11
0 baud 1 to 25 respectively)g are continued. C1) The jJ21 beam is operated by receiving a clock signal from the clock generator 26, and reads and executes one gram sequentially when r< OM 23.
At the time of execution, the γ-data is stored in the nonvolatile RAM 24 and read out, and data is input and output from the input/output terminal 27 via the 1 and 10 ports 25. The above non-volatile RAM 24 is static RAM.
(hereinafter referred to as 1' S r < A M J) 24a and Electric Erasable Progemarble 1≧O
M (hereinafter referred to as "1-E2PRO~1") 24b. SRAM271a and E211ROM24
There is a one-to-one correspondence between people's storage areas and data transfer between the two is done collectively as a row/,1. 1 However, writing data from SRAM24a to E2PROM24b requires approximately 10IIISeC, and E2PROM2
Writing data from 4b to SRAM24a is as follows:
It is 0 μsec. Also, f'! fe Bamboo RAM2/I
The SRAM that can be directly accessed by the CPU 21
There are 24ar, and the E2 PROM 24b is a so-called single-site ROM for saving and replacing with the old one. The standby control circuit 30 is activated when there is a standby activation request from the CPU 21 or when the power supply voltage detection circuit 31 is activated. The microcomputer 20 is activated when it receives a detection signal that detects a voltage drop in the power supply. The standby control circuit 30 is a sequencer, and generates a control signal for starting standby from a clock signal and supplies it to all circuits of the microconvenience store including the nonvolatile RAM 24, the CPU 21, the clock generator 26, and the like. This allows data in SRAM24a to be transferred to E2P all at once.
It is transferred to the ROM 24b and held, and the CPU 21,
The entire circuit of the clock generator 26 controls its operation -It,'
+f'? +t. Furthermore, depending on the standby mode, the light output device 26 may operate four times in a row. Also, the standby control circuit 30 cancels standby when there is a request for canceling standby from the controller 32 during standby operation. -i now control υl jin"I]
Supply all circuits such as R'1-Z26. To this'', tsu UCP (J21.Clock!), 'l
: All circuits of 26 Hide resume their operation and E'PROM
24b is collectively transferred to the SRAM 24a, allowing the CPU 21 to access it. . Here, when the power supply voltage of the microcomputer 20 changes during dil+f' as shown in Figure 12 (Δ), the power supply type pressure detection circuit 'tA31 detects <ig voltage as shown in Figure (B). is supplied to the standby control υU circuit 30. Therefore, the standby υ1011 circuit 30 is
The control signal shown in C) is non-volatile! As shown in FIG. 2(D), the data in the SRAM 24a in the nonvolatile RAM 24 is transferred to the IRAM 24b. Further, as shown in FIG. 2(E), the CPU 21 enters a halt state from the rise of the control signal 1n, and when the power supply voltage 1r becomes OV, the CPU 21 enters the fJ+ state. Further, after the lightning source voltage Lt reaches a predetermined level (flVcc), a standby release signal as shown in FIG.
24a, and the CPU 21 starts operating.
Ru. Now, data transfer of CPU21C non-volatile bamboo RAM! Rather than generating a goningo, the standby control circuit 30 directly controls data transfer of the nonvolatile RAM 24 4w.
n e 44, so the S
It is possible to transfer all the storage contents of the RAM 24a to the E2PROM 24b, and it is possible to completely access the storage contents of the SRAM 24a. In addition, the standby control circuit 30 conventionally built into a single-chip microcomputer with a C-MOS configuration is used, and the present invention effectively controls G, L and E2.
Only the PROM 24b needs to be added, and the circuit configuration is already in place. <g Jj, the power supply voltage detection circuit 31 is a single chip
-2 Microcombi L-Y20 connected to the outside of M11<
, lit! It is not limited to the examples. (Effect of bright light) As mentioned in 1, if wood 5 is connected to bright single-chip microphone ``] computer 1-, then f'H power d'I'll d
! ：＋ fJ' The memory contents of the RAM do not disappear, the memory contents can be preserved, and the circuit configuration is very useful during the song. 4. Figure 1A of the drawings, j2, Figure 1G, 1. Single-chip microphone of the present invention [1,]
Kazumi Nbuta/ll! ll! The block system diagram of /I, Figure 2 is the one shown in Figure 1? Iku [1 Timing block for explaining the operation of combinator 11-1・-C・1 11th fi
In tj, 21 is CPU, 24 LL non-volatile transfer R8 1. 2.18 is S I<ΔM, 24 b$iE2 PROM, 26 beam "179 shot 1, 304, L star> Ha4 ai'l '6n ["l
31 is the Ichigen Lightning J1 detection circuit. 11 people per day 1131 j month? f′i b
- Timing chart for explaining the operation of the 4-microcombeater shown in Figure 1, Figure 2.

Claims (1)

[Claims] A standby control circuit (3) which includes at least a CPU (21), a ROM (23), and a RAM, and which reduces the current consumption of each of these circuits (21, 23) to stop their operation.
In a single-chip microcomputer with a complementary MOS configuration having 0), batch data is transferred between a RAM (24a) that can be accessed by the SPU (21) and a rewritable ROM (24b) that corresponds to the RAM (24a). It has a non-volatile RAM (24) that performs
21) A single-chip microcomputer characterized in that the data stored in the RAM (24a) accessible in 21) is transferred all at once to the rewritable ROM (24b).