JP2891063B2 - Control device - Google Patents
Control deviceInfo
- Publication number
- JP2891063B2 JP2891063B2 JP5264558A JP26455893A JP2891063B2 JP 2891063 B2 JP2891063 B2 JP 2891063B2 JP 5264558 A JP5264558 A JP 5264558A JP 26455893 A JP26455893 A JP 26455893A JP 2891063 B2 JP2891063 B2 JP 2891063B2
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- control device
- flash rom
- data
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Combined Controls Of Internal Combustion Engines (AREA)
- Debugging And Monitoring (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、制御装置に係り、特に
外部からのデータの消去及び書き込みが可能な不揮発性
メモリー（フラッシュＲＯＭ）の使用に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device and, more particularly, to the use of a nonvolatile memory (flash ROM) capable of erasing and writing data from outside.
【０００２】[0002]
【従来の技術】従来、制御装置にフラッシュＲＯＭを使
用する場合、ＣＰＵの動作を監視する監視回路がある
と、外部からのデータの消去及び書き込み中にはＣＰＵ
の動作を示すモニター信号がＣＰＵから出力されず監視
回路が動作し、ＣＰＵに再起動がかかるためデータの消
去及び書き込みが出来ない問題があった。2. Description of the Related Art Conventionally, when a flash ROM is used as a control device, a monitoring circuit for monitoring the operation of the CPU is provided.
The monitor signal indicating the above operation is not output from the CPU, the monitoring circuit operates, and the CPU is restarted. Therefore, there is a problem that data cannot be erased or written.
【０００３】[0003]
【発明が解決しようとする課題】上記従来技術ではフラ
ッシュＲＯＭを備えても、外部からのデータの消去及び
書き込みが出来ずフラッシュＲＯＭを有効に使用できな
い問題があった。In the above-mentioned prior art, even if a flash ROM is provided, there is a problem that external data cannot be erased and written, and the flash ROM cannot be used effectively.
【０００４】本発明の目的は、フラッシュＲＯＭに対し
外部からのデータの消去及び書き込みを可能にすること
にある。An object of the present invention is to enable external data erasing and writing to a flash ROM.
【０００５】[0005]
【課題を解決するための手段】監視回路の動作を外部機
器から一時的に停止させ、ＣＰＵに再起動がかからない
ようにすることで、フラッシュＲＯＭに対し外部からの
データの消去及び書き込みを可能にすることが出来る。SUMMARY OF THE INVENTION The operation of the monitoring circuit is temporarily stopped from an external device so that the CPU is not restarted, so that external data can be erased and written to the flash ROM. You can do it.
【０００６】[0006]
【作用】上記構成により、フラッシュＲＯＭに対し外部
からのデータの消去及び書き込みが可能となる。According to the above configuration, external data can be erased and written to the flash ROM.
【０００７】[0007]
【実施例】以下、本発明の一実施例を図面を用いて説明
する。An embodiment of the present invention will be described below with reference to the drawings.
【０００８】図１は本発明の構成を示すブロック図であ
る。１はエンジン制御装置。２は上記エンジン制御装置
１によって制御されるエンジン。上記エンジン２には図
示してないが運転状態を示す様々なセンサがとりつけら
れており、上記センサからの信号がエンジン制御装置１
に入力される。エンジン制御装置１は上記センサからの
信号を波形処理する入力処理回路４と、このセンサ信号
を入力しエンジン２の最適運転状態を演算するＣＰＵ３
と、上記演算された結果を制御信号として受け、図示し
ていないがエンジン２に取り付けられている燃料噴射装
置や点火装置などのアクチュエータを駆動する出力回路
５から構成されている。上記ＣＰＵ３には制御用プログ
ラムに従い動作するＭＰＵ７と、このＭＰＵ７を動作さ
せるプログラムを格納するＲＯＭ８と、ＭＰＵ７の演算
結果を格納するＲＡＭ９と、前記入力処理回路４からの
信号を受け、また、出力回路５に制御信号を出力するＩ
／Ｏ６と、外部機器とのデータ通信用の通信回路１０が
内蔵されている。上記エンジン制御装置１は外部機器で
あるメモリ書換機１１と電気的に接続可能であり、ＣＰ
Ｕ３内の通信回路１０に接続される。ここで、上記ＲＯ
Ｍ８は特別な条件下で内容の消去及び書き込みが出来る
フラッシュＲＯＭである。１２はＣＰＵ３の動作を監視
する監視回路である。ＣＰＵ３の動作をモニター信号２
１で監視しており、モニター信号２１はメモリ書換機１
１からのモニター信号２１ａとCPU3からのモニター信号
２１ｂのＥＯＲで構成されている。監視回路１２は、モ
ニター信号２１が無くなると、ＣＰＵ３の異常と判定し
再起動信号２２によりＣＰＵ３に再起動をかける。FIG. 1 is a block diagram showing the configuration of the present invention. 1 is an engine control device. Reference numeral 2 denotes an engine controlled by the engine control device 1. Although not shown, the engine 2 is provided with various sensors for indicating an operation state, and signals from the sensors are transmitted to the engine control device 1.
Is input to The engine control device 1 includes an input processing circuit 4 that performs waveform processing on a signal from the sensor, and a CPU 3 that receives the sensor signal and calculates an optimal operation state of the engine 2.
And an output circuit 5 that receives the calculated result as a control signal and drives an actuator such as a fuel injection device or an ignition device attached to the engine 2 (not shown). The CPU 3 includes an MPU 7 operating according to a control program, a ROM 8 storing a program for operating the MPU 7, a RAM 9 storing an operation result of the MPU 7, a signal from the input processing circuit 4, and an output circuit. 5 which outputs a control signal to I
A communication circuit 10 for data communication with / O6 and an external device is built in. The engine control device 1 can be electrically connected to a memory rewriter 11 which is an external device.
It is connected to the communication circuit 10 in U3. Here, the RO
M8 is a flash ROM capable of erasing and writing contents under special conditions. A monitoring circuit 12 monitors the operation of the CPU 3. Monitor operation of CPU3
1 and the monitor signal 21 is the memory rewrite 1
1 is composed of the EOR of the monitor signal 21a from the CPU 1 and the monitor signal 21b from the CPU 3. When the monitor signal 21 disappears, the monitoring circuit 12 determines that the CPU 3 is abnormal, and restarts the CPU 3 with the restart signal 22.
【０００９】図２は信号のタイミングを示すチャート図
である。時間３０で電源がＯＮされるとＣＰＵ３が動作
してモニター信号２１ｂが出力され、ＥＯＲを介してモ
ニター信号２１が監視回路１２に入力される。時間３１
で外部機器１１からフラッシュＲＯＭ８へデータの消去
及び書き込みが始まると、ＣＰＵ３の動作が停止してモ
ニター信号２１ｂの出力が停止する。同時に、外部機器
１１からのモニター信号２１ａが出力され、ＥＯＲを介
してモニター信号２１が監視回路１２に入力される。時
間３２で外部機器１１からフラッシュＲＯＭ８へデータ
の消去及び書き込みが終わると、再びＣＰＵ３が動作し
てモニター信号２１ｂが出力され、EORを介してモニタ
ー信号２１が監視回路１２に入力される。以上の動作
で、監視回路１２からの再起動信号２２によりＣＰＵ３
に再起動をかけることなく、フラッシュＲＯＭ８へ外部
からデータの消去及び書き込みを行うことが出来る。FIG. 2 is a chart showing signal timings. When the power is turned on at time 30, the CPU 3 operates to output the monitor signal 21b, and the monitor signal 21 is input to the monitor circuit 12 via the EOR. Time 31
When the erasing and writing of data from the external device 11 to the flash ROM 8 are started, the operation of the CPU 3 stops and the output of the monitor signal 21b stops. At the same time, the monitor signal 21a is output from the external device 11, and the monitor signal 21 is input to the monitoring circuit 12 via the EOR. When erasure and writing of data from the external device 11 to the flash ROM 8 are completed at time 32, the CPU 3 operates again to output the monitor signal 21b, and the monitor signal 21 is input to the monitor circuit 12 via the EOR. With the above operation, the restart signal 22 from the monitoring circuit 12 causes the CPU 3
Data can be externally erased and written to the flash ROM 8 without restarting the flash ROM 8.
【００１０】[0010]
【発明の効果】本発明によれば、フラッシュＲＯＭ８に
対し外部からのデータの消去及び書き込みが可能とな
る。According to the present invention, external data can be erased and written to the flash ROM 8 from outside.
【図１】本発明の構成を示すブロック図である。FIG. 1 is a block diagram showing a configuration of the present invention.
【図２】信号のタイミングを示すチャート図である。FIG. 2 is a chart showing signal timings.
１…制御装置、２…エンジン、３…ＣＰＵ、４…入力処
理回路、５…出力回路、６…Ｉ／Ｏ、７…ＭＰＵ、８…
フラッシュＲＯＭ、９…ＲＡＭ、１０…通信回路、１１
…メモリ書換機、１２…監視回路。DESCRIPTION OF SYMBOLS 1 ... Control device, 2 ... Engine, 3 ... CPU, 4 ... Input processing circuit, 5 ... Output circuit, 6 ... I / O, 7 ... MPU, 8 ...
Flash ROM, 9 RAM, 10 communication circuit, 11
... memory rewriter, 12 ... monitoring circuit.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) F02D 45/00 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 6 , DB name) F02D 45/00
Claims (1)
能な不揮発性メモリーを有し、この不揮発性メモリーに
は制御用プログラム，データが記憶されており、また、
CPUの動作を監視しＣＰＵの動作に問題がある場合には
ＣＰＵに再起動をかける監視回路を備えた制御装置にお
いて、外部からのデータの消去及び書き込み時に監視回
路の動作を外部機器から一時的に停止させることを特徴
とする制御装置。A non-volatile memory capable of erasing and writing data from outside; a control program and data are stored in the non-volatile memory;
In a control device equipped with a monitoring circuit that monitors the operation of the CPU and restarts the CPU if there is a problem with the operation of the CPU, the operation of the monitoring circuit is temporarily stopped by an external device when data is externally erased and written. A control device characterized in that the control device is stopped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5264558A JP2891063B2 (en) | 1993-10-22 | 1993-10-22 | Control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5264558A JP2891063B2 (en) | 1993-10-22 | 1993-10-22 | Control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07119537A JPH07119537A (en) | 1995-05-09 |
| JP2891063B2 true JP2891063B2 (en) | 1999-05-17 |
Family
ID=17404953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5264558A Expired - Lifetime JP2891063B2 (en) | 1993-10-22 | 1993-10-22 | Control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2891063B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6144887A (en) | 1996-12-09 | 2000-11-07 | Denso Corporation | Electronic control unit with reset blocking during loading |
| JPH11237980A (en) | 1998-02-20 | 1999-08-31 | Hitachi Ltd | Device and method for generating object-orientated optimized code |
| JP3214469B2 (en) | 1998-11-13 | 2001-10-02 | 日本電気株式会社 | Method and apparatus for controlling writing of flash EEPROM by microcomputer |
| JP4516241B2 (en) * | 2001-07-06 | 2010-08-04 | 日立オートモティブシステムズ株式会社 | Engine control device |
-
1993
- 1993-10-22 JP JP5264558A patent/JP2891063B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07119537A (en) | 1995-05-09 |
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