JPS6014362A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simplify the structures of both hardware and software and to improve the general-purpose properties of a semiconductor memory, by using a threshold value setting circuit and a power supply voltage monitor circuit and actuating a read/write control circuit in response to the fall and rise of the power supply voltage. CONSTITUTION:The power supply voltage VCC of a system to which a memory is applied is fed to a power supply voltage monitor circuit 5. The circuit 5 detects the 1st threshold voltage for detection of break of power supply and the 2nd threshold voltage for detection of make of power supply which are applied from a threshold value setting circuit 6. In other words, the voltage VCC is detected when it falls less than the 1st threshold voltage and rises more than the 2nd threshold voltage respectively. Thus a read/write control circuit 4 is controlled. Then the circuit 4 reads out the contents of a buffer memory 3 when the break of the power supply is detected and writes them to a nonvolatile memory 2. Then the circuit 4 reads out the contents of the memory 2 when the make of the power supply is detected and writes them to the memory 3. In such a way, the threshold value is set to control the circuit 4. This can simplify the structures of both the hardware and software and improve the general-purpose properties of a semiconductor memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory used in, for example, an engine control device P't of an automobile or a nine-channel control device for front equipment, and particularly relates to a semiconductor memory having a built-in nonvolatile memory. Regarding memory.

[Technical background from origin 1] Conventional non-volatile memory uses MNOS in memory cells.
-FET (metal nitride oxide type r-
) is a static type MNOS-RAM (Random Access Memory) using a field-effect transistor with an insulating layer), which is a combination of RAM and E2FROM (programmable read-only memory whose memory contents can be electrically rewritten). be.

[Background: Problems with technology]

By the way, the former MNOS memory has complicated write timing and requires a dedicated controller IC for interface with a microprocessor. Also,
The current MNOS memory has 105 times of ingestion and erasure.
Since it is only guaranteed to a certain extent, it is not suitable if it is necessary to replace it within a relatively short period of time when it is used, since it will be difficult to maintain it.

On the other hand, the latter combination of RAM and ID FROM simplifies the interface with the microprocessor and is therefore easy to use. However, since a FROM is basically used, the number of erase operations is currently maintained at only about 5,000.

Therefore, taking into consideration the small number of times of programming as mentioned above, we devised a software solution to stop writing to nonvolatile memory cells in 4iJ when data is updated, and cut off one source of supply to the memory. In order to save the number of #writes, the number of #writes is saved by writing data into the nonvolatile memory cell only at the time of writing. However, in order to perform this kind of control, it is necessary to use a memo IJ (not a scale that requires a complicated program for the system to be used), but to detect when the power supply is cut off (such as when one river runs out, or when an interrupt is detected when the cut is detected). Since an interrupt generation circuit is required, the hardware becomes complicated, and the number of usable interrupt lines is reduced by one for the number of interrupts used.

[Purpose of departure [jl]]

The present invention has been made in view of the above-mentioned circumstances, and is intended to improve the electronic &i'! memory application system. j. It is an object of the present invention to provide a semiconductor memory that can simplify the hardware and software required to store data in a nonvolatile memory during downtime, and has great versatility.

[Six waves of the shield of the invention] 1:11 First, the semiconductor memory of the present invention is such that the power supply voltage reaches the first threshold (tl) based on the voltage specified by the threshold value setting circuit.
';', 'Fr, when it is detected that it has been exceeded, the contents of the buffer memory are written to the non-volatile memory, and γ
1): When it is detected that the source voltage has increased beyond the second threshold value, the read/write control circuit 1 is fully operated so that the contents of the nonvolatile memory are read out to the buffer memory. It is something.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the same song.

In the figure, J is a semiconductor memory formed on one chip, and inside this is a 4' non-holytic memory, ? , read/write buffer memory 3 consisting of RAM, read/write buffer memory 3,
A write control circuit 4, a power supply voltage monitoring circuit 5, and a threshold value setting circuit 6 are provided. The threshold setting circuit 6 generates a threshold voltage for determining the power supply voltage detection reference level of the power supply voltage monitoring circuit 5 in response to control data input from an external microprocessor (not shown). The illumination voltage monitoring circuit 5 is a system to which a memory is applied (
The power supply voltage Vce of the memory application system) is led as a monitoring input, and when this power supply voltage input drops beyond a first threshold voltage for power cutoff detection given from the threshold value setting circuit 6 and for power on detection. The read/write control circuit 4 is controlled by detecting when the voltage rises above the second threshold voltage for each. That is, when detecting a power-off, the content of the buffer memory 3 is read and stored in the non-volatile memory 2, and when detecting a power-on, the content of the non-volatile memory 5-2 is read and stored in the buffer memory 3. It is controlled so that it can be increased in size. ”2 Buffer memory 3
For example, it is connected to a microprocessor through a path 7, and data is normally read/written from/to the microprocessor under read/write control by the microprocessor.

The semiconductor memory described above automatically controls read/write between the buffer memory 3 and the nonvolatile memory 2 by detecting when the power is turned off and when the power is turned on in the system to which this memory is applied. He is responsible for the functions he performs. Therefore, the memory peripheral circuit that was conventionally required to realize this function is no longer necessary, and the memory and microprocessor can be directly connected via path 7, so the system hardware Configuration is simplified. Also, in terms of software, there is no need for interrupt control when power is cut off, making it easy to create system software.

6- 〔Effect of the invention〕 As mentioned above/thus by the live conductor memory of the present invention.

For example, the hardware and software for storing 4<1 data in the nonvolatile memory when the memory capacity y+1 system is connected/disconnected can be simplified, which has the advantage of increased versatility. Therefore, there is a need for a reduction in the number of parts and a simplification of interrupt processing when η■1 is disconnected.
Applying the unexploded J memory to the JT4 flj control system is very effective as it can improve the reliability of J1, Vf, and reduce costs.

[Brief explanation of the drawing]

FIG. ij'i+ is a configuration explanatory diagram showing an example of a half-column memory according to the present invention. 2...Nonvolatile memory, 3...J rough memory,
401. 1. Light control circuit, 5. Power supply voltage monitoring circuit, 6. Threshold value setting circuit. Applicant's agent Rishi I Suzue Takehiko 7-

Claims (1)

[Claims] A non-volatile memory, a buffer memory for read/write, a read/write control path for controlling these memories8]l, and a threshold value setting circuit for receiving a first llλ1 value voltage and a second λ1 value voltage. When the threshold voltage is given as the detection reference level, when the power supply voltage input drops beyond the above-mentioned 1.1 value voltage and when the power is cut off, the voltage rises above the second threshold voltage tW. The read/write control is configured to detect when the power is turned on, to read the contents of the buffer memory into the non-volatile memory upon detection when the power is turned off, and to read the contents of the non-volatile memory to the buffer memory upon detection when the Mr power is turned on. A semiconductor memory characterized by being completely equipped with a power supply voltage monitoring circuit for controlling the circuit.