JPS599768A - Initializing device of data processor - Google Patents
Initializing device of data processorInfo
- Publication number
- JPS599768A JPS599768A JP57118375A JP11837582A JPS599768A JP S599768 A JPS599768 A JP S599768A JP 57118375 A JP57118375 A JP 57118375A JP 11837582 A JP11837582 A JP 11837582A JP S599768 A JPS599768 A JP S599768A
- Authority
- JP
- Japan
- Prior art keywords
- main processor
- svp1
- turned
- flip
- svp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、主プロセツサとこの王プロセッサの初期設定
を行なうサービスプロセッサ(以下、SNPと略称する
。)と全備えたデータ処理装置の初期設定装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an initial setting device for a data processing apparatus, which includes a main processor and a service processor (hereinafter abbreviated as SNP) that performs initial settings for the main processor.
従来のこの種データ処理装置では、主プロセツサとSV
Pがそれぞれ独立の電源装置?有していても、両電源装
置は1つの電力系統に接続され、この電力系統の間両に
より、両電源装置の同時投入・遮断を行なっている。そ
のため、主プロセツサの電源投入とSVPの電源投入と
はタイミング的に等価であるとして設計され、5VP−
の電源が投入された時に主プロセツサに対する初期設定
動作を開始させることにより、自動初期設定機能全実現
している。In conventional data processing devices of this type, the main processor and the SV
Is each P an independent power supply? Even if the power supply device has one, both power supply devices are connected to one power system, and both power supply devices are turned on and off simultaneously through the power system. Therefore, the power-on of the main processor and the power-on of the SVP are designed to be equivalent in terms of timing, and the 5VP-
The automatic initial setting function is fully realized by starting the initial setting operation for the main processor when the power is turned on.
このような従来の初期設定方式では、通常の使用状態で
は全く正しく働くが、試験時、保守時などに、SVPの
電源だけ全遮断・投入すると、その電源投入毎に主プロ
セツサに対する初期設定動作が起動されてしまい、すで
にデータの設定が終っている主プロセツサの記憶装置を
再びクリアしてしまうという欠点があった。This conventional initialization method works perfectly correctly under normal usage conditions, but if the power to the SVP is completely shut off and then turned on during testing or maintenance, the initialization operations for the main processor will be performed each time the power is turned on. This has the drawback that the main processor's memory device, which has already been started and data has already been set, is cleared again.
本発明の目的は、SVPによる主プロセツサの初期設定
を、本来必要とされている場合に1回だけ行ない、主プ
ロセツサの記憶装置の内容を破壊してしまうなどの不都
合を防止した初期設定装置を提供することにある。An object of the present invention is to provide an initial setting device that performs the initial setting of the main processor by SVP only once when it is originally required, and prevents inconveniences such as destroying the contents of the main processor's storage device. It is about providing.
このような目的を達成するために、本発明では、王プロ
セッサが1度初期設定されたことを記憶するレジスタを
設け、SVPの電源投入時に、このレジスタの内容を識
別し、初期設定されていないことが識別された時のみ主
プロセツサの初期設定を行なうようにしたことに特徴が
ある。In order to achieve such an objective, the present invention provides a register that stores the information that the processor has been initialized once, and when the SVP is powered on, the contents of this register are identified and the contents of this register are identified and the contents of this register are checked to confirm that the processor has not been initialized. The main processor is initialized only when the main processor is identified.
以下、本発明の実施例を図面により詳細に説明する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第1図は本発明による初期設定装置を実現するデータ処
理装置の一実施例の構成図、第2図はSvP電源投入後
のSvPの処理の流れの一例を示すフローチャートであ
る。FIG. 1 is a configuration diagram of an embodiment of a data processing device that implements an initial setting device according to the present invention, and FIG. 2 is a flowchart showing an example of the flow of SvP processing after SvP power is turned on.
第1図において、lはSVPで、SVP中央処理装置1
1、svp電源装置12、ROM13、インタフェース
回路14、入出力レジスタ15および入力レジスタ16
からなっている。また、2は王プロセッサで、主プロセ
ツサ中央処理装置21、主プロセツサ電源装置22、イ
ンタフェース回路23、初期設定記憶用フリップフロッ
プ24からなっている。In FIG. 1, l is SVP, SVP central processing unit 1
1, svp power supply device 12, ROM 13, interface circuit 14, input/output register 15, and input register 16
It consists of Reference numeral 2 denotes a king processor, which includes a main processor central processing unit 21, a main processor power supply 22, an interface circuit 23, and a flip-flop 24 for storing initial settings.
さらに、31はS V P 1と主プロセツサ2との間
でやりとりされるデータ、32は8VP1からのセット
信号、33は主プロセツサ2の7リツププロツプ24の
出力信号、34および35は主プロセツサ2の電源装置
22からの状態信号およびリセット48号を示す。Further, 31 is data exchanged between the SVP 1 and the main processor 2, 32 is a set signal from the 8VP1, 33 is an output signal of the 7-lip prop 24 of the main processor 2, and 34 and 35 are the output signals of the main processor 2. Status signals from power supply 22 and reset 48 are shown.
第1図において、本発明で特徴的なことは、主プロセツ
サ2に初期設定記憶用フリップ70ツブ24ヲG’rf
、そのフリップフロップを主プロセツサ2の電源装置2
20投入時にリセット信号35によりリセットし、5V
P1のプログラム制御により発せられるセット信号32
によシセットするようになっている。また、このフリッ
プ70ツブ24のセット出力33をsvp iに送出す
るとともに、主プロセツサ2の電源装置22から電源の
投入・遮断状態を示す状態信号34’5SVP1に送出
している。In FIG. 1, the feature of the present invention is that the main processor 2 has an initial setting storage flip 70 and a G'rf
, the flip-flop is connected to the power supply 2 of the main processor 2.
Reset by reset signal 35 when 20 is turned on, 5V
Set signal 32 issued by program control of P1
It is designed to be set properly. Further, the set output 33 of the flip 70 knob 24 is sent to svpi, and the power supply 22 of the main processor 2 sends out a status signal 34'5SVP1 indicating the power on/off state.
いま、5VP1の電源装置12が投入されると、5VP
Iの自動スタート用のROM13に内蔵されたSVP自
身の初期化プログラムを動作させ、引き続いて、第2図
に示す、5vP1による主プロセツサ2の初期設定動作
を開始させる。Now, when the power supply device 12 of 5VP1 is turned on, the 5VP
The SVP's own initialization program built in the ROM 13 for automatic start of the SVP is operated, and subsequently, the initial setting operation of the main processor 2 by 5vP1 shown in FIG. 2 is started.
ところで、5vP1の電源投入時の主プロセツサ2の状
態は381類しかなく、第1は主プロセツサ2の電源装
置22の遮断状態、第2は主プロセツサ2の電源装置2
2は投入されているが、SVP 1による初期設定がい
まだ行なわれていない状態、第3は主プロセツサ2の電
源装置22は投入状態で、5VPlによる初期設定が以
前に済まされている状態である。By the way, there are only 381 states of the main processor 2 when the 5vP1 is powered on, the first being the cut-off state of the power supply 22 of the main processor 2, and the second being the state of the power supply 22 of the main processor 2.
2 is in a state where the power supply unit 22 of the main processor 2 is turned on, but the initial setting by SVP 1 has not yet been performed, and the third state is a state in which the power supply device 22 of the main processor 2 is in a state where it is turned on and the initial setting by 5VPl has been completed previously. .
SVP 1は、電源装置12の投入により、先ず始めに
、王プロセッサ2の電源装置22の投入・遮断状態を示
す状態信号34を入力し、それをレジスタ16を通して
読み込み、第1の条件分岐を行なう(ステップ41)。When the power supply device 12 is turned on, the SVP 1 first inputs the status signal 34 indicating the on/off state of the power supply device 22 of the processor 2, reads it through the register 16, and performs the first conditional branch. (Step 41).
ここで、主プロセツサ電源22が投入状態であれば、さ
らに、フリップフロップ24の出力信号33を入出力レ
ジスタ15を通して読み込み、第2の条件分岐を行なう
(ステップ42)。ここで、フリップフロップ24がリ
セット状態であれば、5vP1は生プロセッサ2の初期
設定が済んでいないと判断し、インタフェース回路14
.23を通してデータ31を送り、主プロセツサ2内の
電子回路(図示省略)の初期設定を行ない(ステップ4
3)、その後、入出力レジスタ15を通してフリップフ
ロップ240セツト信号32を発し、フリップフロップ
24をセットしくステップ44)、初期設定プログラム
の実行を終了する。Here, if the main processor power supply 22 is on, the output signal 33 of the flip-flop 24 is further read through the input/output register 15, and a second conditional branch is performed (step 42). Here, if the flip-flop 24 is in the reset state, the 5vP1 determines that the initial settings of the raw processor 2 have not been completed, and the interface circuit 14
.. The data 31 is sent through 23 to initialize the electronic circuit (not shown) in the main processor 2 (step 4).
3) After that, the flip-flop 240 set signal 32 is issued through the input/output register 15 to set the flip-flop 24 (step 44), and the execution of the initial setting program is completed.
また、第2の条件分岐の際に、フリップフロップ24が
セット状態である場合には、5vP1は主プロセツサ2
の初期設定済みと判断し、何もせずに初期設定プログラ
ムの実行を終了する。Furthermore, when the flip-flop 24 is in the set state at the time of the second conditional branch, 5vP1 is transferred to the main processor 2.
It is determined that the initial settings have been completed, and execution of the initial settings program ends without doing anything.
さらに、第1の条件分岐で、主プロセツサ電源22が遮
断状態であると識別されると、5VPIは主プロセツサ
電源22が投入されるまで待ちの状態となり(ステップ
45)、主プロセツサ2の電源投入後、前述したと同様
に、主プロセツサ2の初期設定(ステップ43)とフリ
ップフロップ24のセット(ステップ44)を行ない、
初期設定プログラムの実行を終了する。Further, when the first conditional branch identifies that the main processor power supply 22 is in a cut-off state, the 5VPI enters a waiting state until the main processor power supply 22 is turned on (step 45), and the main processor 2 is turned on. After that, the main processor 2 is initialized (step 43) and the flip-flop 24 is set (step 44) in the same way as described above.
Finish running the initialization program.
このようにして、5vP1はフリップ70ツブ24の状
態を判定することにより、主プロセツサが初期設定済み
かどうかを判定し、初期設定済みでない時に初期設定を
行なうことによシ、主プロセツサの初期設定の重複を避
けることができる。In this way, the 5vP1 determines whether the main processor has been initialized by determining the state of the flip 70 knob 24, and performs initialization when the initialization has not been completed. duplication can be avoided.
なお、上述した例では初期設定記憶用にフリップ70ツ
ブを設ける場合について示したが、それに限定されるも
のでなく、情報を記憶するレジスタであれば何でもよい
。Although the above-mentioned example shows a case where a flip 70 tab is provided for storing initial settings, the present invention is not limited thereto, and any register that stores information may be used.
また、この初期設定記憶用レジスタを主プロセツサ2側
に設ける例について説明したが、このレジスタをSVP
側に設けてもよいことは言う寸でもない。In addition, although an example has been described in which this initial setting storage register is provided on the main processor 2 side, this register is
There is no need to say that it can be installed on the side.
以上述べたように、本発明によれば、SVPの電源と主
プロセツサの電源とを全く独立のタイミングで投入・遮
断した場合にも、SVPによる主プロセツサの自動初期
設定が、必要な時にだけ、すなわち、主プロセツサの電
源投入後に1回だけ行なわれるようとすることが可能と
なり、初期設定の重複動作を避けることができ、主プロ
セツサの記憶装置をクリアしてしまうような不都合をな
くすことができる。As described above, according to the present invention, even when the SVP power supply and the main processor power supply are turned on and off at completely independent timings, automatic initialization of the main processor by the SVP is performed only when necessary. In other words, it is possible to perform the process only once after the power of the main processor is turned on, and it is possible to avoid duplication of initial settings and eliminate the inconvenience of clearing the memory of the main processor. .
第1図は本発明による初期設定方式を実現するデータ処
理装置の一実施例の構成図、第2図は第1図のSvPに
よる初期設定手順の一例を示すフローチャートである。FIG. 1 is a block diagram of an embodiment of a data processing apparatus that implements the initial setting method according to the present invention, and FIG. 2 is a flowchart showing an example of the initial setting procedure using SvP shown in FIG.
Claims (1)
自動的に行なう第2の処理装置とからなるデータ処理装
置において、上記第1および第2の処理装置のいずれか
一方に、上記第1の処理装置が初期設定されたかどうか
を記憶するレジスタ手段金偏え、上記第2の処理装置の
電源投入時に、上記レジスタ手段の内容全識別し、上記
第1の処理装置が初期設定されていないことが識別され
た時、上記第2の処理装置により、上記第1の処理装置
の初期設定を行なうとともに、上記レジスタ手段に初期
設定されたことを記憶するようにしたことを特徴とする
初期設定装置。1. In a data processing device consisting of a first processing device and a second processing device that fully automatically performs the initial setting of the first processing device, one of the first and second processing devices register means for storing whether or not the first processing device has been initialized; upon power-on of the second processing device, all contents of the register means are identified, and the first processing device is initialized; When it is determined that the first processing device is not set, the second processing device initializes the first processing device, and stores the initial setting in the register means. Initial setting device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57118375A JPS599768A (en) | 1982-07-09 | 1982-07-09 | Initializing device of data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57118375A JPS599768A (en) | 1982-07-09 | 1982-07-09 | Initializing device of data processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS599768A true JPS599768A (en) | 1984-01-19 |
Family
ID=14735141
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57118375A Pending JPS599768A (en) | 1982-07-09 | 1982-07-09 | Initializing device of data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS599768A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61131021A (en) * | 1984-11-29 | 1986-06-18 | Toshiba Corp | Initializing method of memory |
JPS62264317A (en) * | 1986-05-12 | 1987-11-17 | Mitsubishi Electric Corp | Initialization system for shared peripheral device |
JPH02222016A (en) * | 1989-02-23 | 1990-09-04 | Rinnai Corp | Controller for plural control circuits |
-
1982
- 1982-07-09 JP JP57118375A patent/JPS599768A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61131021A (en) * | 1984-11-29 | 1986-06-18 | Toshiba Corp | Initializing method of memory |
JPS62264317A (en) * | 1986-05-12 | 1987-11-17 | Mitsubishi Electric Corp | Initialization system for shared peripheral device |
JPH02222016A (en) * | 1989-02-23 | 1990-09-04 | Rinnai Corp | Controller for plural control circuits |
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