JPS63146471A - Manufacture of mis element - Google Patents
Manufacture of mis elementInfo
- Publication number
- JPS63146471A JPS63146471A JP29481487A JP29481487A JPS63146471A JP S63146471 A JPS63146471 A JP S63146471A JP 29481487 A JP29481487 A JP 29481487A JP 29481487 A JP29481487 A JP 29481487A JP S63146471 A JPS63146471 A JP S63146471A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- nitride film
- silicon
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 39
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 61
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、導電＠（Ｍ）−絶縁膜（Ｉ）−シリコン（Ｓ
）構造、いわゆるＭＩＳ構造における製造上の改良に関
し、特に絶縁膜（１）中にシリコン窒化膜を含むＭＫＳ
構造において当該シリコン窒化膜成長の際に形成される
ことあるピンホールを、製造完了の後ではなく、当該製
造過程中で既に将来の素子動作上、問題のないように処
理するための改良に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to conductive @(M)-insulating film (I)-silicon (S
) structure, the so-called MIS structure, in particular regarding manufacturing improvements in the
The present invention relates to an improvement for treating pinholes that may be formed during the growth of a silicon nitride film in a structure so as not to cause problems in future device operation during the manufacturing process, rather than after the manufacturing is completed.
〈従来の技術〉
近年、いわゆるＭＮＯＳ構造素子等に代表されるＭＩＳ
メモリや、もっと単純にＭＩＳキャパシタ等にあっては
、シリコンと導電膜との間に挟み込む絶縁膜はより一層
、？＃膜化の傾向を示している。<Conventional technology> In recent years, MIS represented by so-called MNOS structure elements, etc.
In the case of memories or, more simply, MIS capacitors, etc., the insulating film sandwiched between silicon and conductive film is even more important. #Shows a tendency to form a film.
こうした場合、当該絶縁膜にはその成長の過程でピンホ
ールが生ずることがある。In such cases, pinholes may occur in the insulating film during its growth process.
（発明が解決しようとする問題点〉
しかるに従来、絶縁膜中にシリコン窒化膜を含み、この
シリコン窒化膜にその成長の過程で上記のようにピンホ
ールが生じていた場合にも、それは素子の完成後におけ
る素子動作の不完全さで気が付くのみで、いったん、そ
うしたピンホールが生じていると、最早、修復の術がな
かった。(Problem to be solved by the invention) However, conventionally, when an insulating film includes a silicon nitride film, and pinholes are generated in the silicon nitride film during the growth process as described above, these pinholes can cause damage to the device. They were only noticed by imperfections in the device's operation after completion, and once such pinholes had occurred, there was no way to repair them.
ピンホールはもちろん、素子の収率の低下を来たす重要
な悪因の一つとなる。シリコン窒化膜に形成されてしま
ったピンホールが特にゲート電極等の導電膜下で、素子
動作に重要な領域、すなわち当該導電膜に電圧を印加し
た際等、その電界の影響下にある場合、例えピンホール
を介して導電膜材料が直接にシリコン窒化股下のシリコ
ン酸化膜またはシリコン領域に接触することはなくても
（接触することもある）、電界の集中が起こり、結局は
リークを起こす等するからである。Pinholes are, of course, one of the important causes of reduction in device yield. If a pinhole formed in a silicon nitride film is under the influence of an electric field, especially under a conductive film such as a gate electrode, in an area important for device operation, i.e. when a voltage is applied to the conductive film, Even if the conductive film material does not come into direct contact with the silicon oxide film or silicon region under the silicon nitride crotch through the pinhole (it may come into contact), electric field concentration will occur, eventually causing leakage, etc. Because it does.
ところが従来、そうしたシリコン窒化膜成長い際し、そ
もそもシリコン窒化膜の成長に関し、そうしたピンホー
ルを生じ難いような条件下での成長に限るとか、あるい
はまた、先のように薄膜化の要請があってもこれはある
程度犠牲にし、ピンホールが生じ難いような十分な厚さ
にまで、シリコン窒化膜を成長させるというような、言
わば受は身の対策しかなく、当該シリコン窒化膜にピン
ホールが生じてしまった場合には、これを簡単には回復
させる手段がなかった。However, in the past, when growing silicon nitride films, growth was limited to conditions in which such pinholes were unlikely to occur, or, as mentioned earlier, there was a demand for thinner films. However, the only solution is to sacrifice this to some extent and grow the silicon nitride film to a sufficient thickness so that pinholes are unlikely to form. If this happens, there is no easy way to recover from it.
本発明はこうした観点から成されたもので、特にＭＮＯ
Ｓメモリの改良等において認められるように、シリコン
窒化膜を薄膜化せねばならない要求があり、一方でその
ように薄膜化して行くとピンホールの生成をある程度容
認しなければならないような状況下にあっても、当該生
することあるピンホールを一連の製造工程下において回
復ないし修復し得、リークの問題をあらかじめ解決し得
る簡単かつ確実な手法を提供せんとするものである。The present invention has been made from this point of view, and in particular,
As seen in the improvement of S memory, there is a need to make the silicon nitride film thinner, but on the other hand, as the film becomes thinner, it becomes necessary to accept the formation of pinholes to some extent. Even if such pinholes occur, the present invention aims to provide a simple and reliable method that can recover or repair the pinholes that may occur during a series of manufacturing steps, and that can solve the leakage problem in advance.
〈問題点を解決するための手段〉
本発明は上記目的を達成するため、シリコン酸化膜また
はシリコン領域上に形成したシリコン窒化膜の上に導電
膜を形成する必要のあるＭＩＳ構造において、当該導電
膜形成の前にシリコン窒化膜表面をさらに酸化する工程
の賦与を提案する。<Means for Solving the Problems> In order to achieve the above object, the present invention provides an MIS structure in which a conductive film needs to be formed on a silicon oxide film or a silicon nitride film formed on a silicon region. We propose a step to further oxidize the silicon nitride film surface before film formation.
換言すれば、導電膜はこのようにして形成されたシリコ
ン酸化膜の上に形成するようにする。In other words, the conductive film is formed on the silicon oxide film thus formed.
〈作用および効果〉
上記のような本発明のＭＩＳ構造製造方法によも、当該
シリコン窒化膜の表面を酸化する工程により、もし仮に
そうしたピンホールがあれば、シリコン窒化膜が酸化さ
れる速度より、このピンホールを介して露呈しているシ
リコン領域表面またはシリコン酸化膜表面の酸化速度の
方が通かに早いという理屈により、自動的にこのピンホ
ール内をシリコン酸化物で充填することができる。<Operations and Effects> In the MIS structure manufacturing method of the present invention as described above, the process of oxidizing the surface of the silicon nitride film will cause the oxidation rate of the silicon nitride film to be faster than the rate at which the silicon nitride film is oxidized if such a pinhole exists. Based on the theory that the oxidation rate of the silicon region surface or silicon oxide film surface exposed through this pinhole is much faster, this pinhole can be automatically filled with silicon oxide. .
したがって従来のように、シリコン窒化膜上にそのまま
導電膜を形成すると、当該導電膜材料がピンホール内に
侵入してシリコン領域との間で短絡を起こすとか、望ま
しくない電界の集中効果を起こすようなおそれは未然に
、しかも素子製造工程の途中で簡単に回避され、もって
素子の収率を高めることができる。Therefore, if a conductive film is directly formed on a silicon nitride film as in the past, the conductive film material may enter the pinhole and cause a short circuit with the silicon region or cause an undesirable electric field concentration effect. Incidentally, this can be easily avoided before it happens, and moreover, during the device manufacturing process, thereby increasing the yield of devices.
〈実 施 例〉
第１図は本発明の製造方法を適用した結果、得られたＭ
ＩＳ構造例を示していて、ピンホール内にシリコン酸化
物ＩＯが自動的に形成された模様が良く示されているが
、便宜上、この素子の製造工程自体は第２図に即して説
明する。<Example> Figure 1 shows the M obtained as a result of applying the manufacturing method of the present invention.
An example of the IS structure is shown, and the pattern in which silicon oxide IO is automatically formed within the pinhole is clearly shown, but for convenience, the manufacturing process itself of this device will be explained with reference to Figure 2. .
シリコン領域１は基板でも、あるいはまた基板上の薄膜
であっても良いが、当該シリコン領域１の上には第２図
（Ａ）に示されるように、この実施例の場合、例えばＭ
ＮＯＳ構造素子の動作原理に従うに適当なような極めて
薄いシリコン酸化膜２が形成されている。The silicon region 1 may be a substrate, or alternatively a thin film on a substrate; in this embodiment, for example, M is provided on the silicon region 1, as shown in FIG.
An extremely thin silicon oxide film 2 is formed, which is suitable for following the operating principle of the NOS structure element.
しかるに、この上にさらに電荷のトラップを有するよう
なシリコン窒化膜３を成長させると、一般にそれが最初
は島状に成長する結果、模式的に示されているように、
当該シリコン窒化膜３にはピンホール８が生ずることが
ある。特にこのシリコン窒化膜３自体も薄くしたい場合
にそうなることが多い。However, when a silicon nitride film 3 having charge traps is grown on top of the silicon nitride film, it generally grows in the form of an island at first, as shown schematically.
Pinholes 8 may occur in the silicon nitride film 3 . This often happens especially when it is desired to make the silicon nitride film 3 itself thin.
こうなると当然、シリコン窒化膜の下のシリコン酸化膜
２は少なくとも露出するし、場合によっては図示されて
いないがシリコン酸化膜２にもピンホールが生じている
ことがあり、したがってたまたま、シリコン窒化膜３に
生成したピンホール８と、このシリコン酸化膜２にでき
たピンホールとが位置的に整合すると、結局、最下層の
シリコン領域１の表面までもが露出することになる。Naturally, in this case, at least the silicon oxide film 2 under the silicon nitride film will be exposed, and in some cases, although not shown, pinholes may also be formed in the silicon oxide film 2. When the pinhole 8 formed in the silicon oxide film 3 and the pinhole formed in the silicon oxide film 2 are aligned in position, even the surface of the lowermost silicon region 1 is exposed.
しかし、本発明においては、シリコン窒化膜３の上に第
１図示の導電膜ないしゲート電極７を形成する前に、シ
リコン窒化膜３の表面を酸化する工程を導・入する。However, in the present invention, before forming the conductive film or gate electrode 7 shown in the first figure on the silicon nitride film 3, a step of oxidizing the surface of the silicon nitride film 3 is introduced.
このようにすると、シリコン窒化膜３の表面が酸化され
、シリコン酸化膜９が形成されるのはもとよりであるが
、ピンホール８のできている部位ではシリコン領域１の
表面またはシリコン酸化膜２の表面が露呈しているため
、シリコン窒化膜３の酸化速度よりも一桁以上も早い速
度でそうした露出表面が酸化され、結局、第２図（Ｂ）
に示されているように、当該ピンホール８の内部はシリ
コン酸化物ｌＯで埋められてこれが塞がるようになる。By doing this, the surface of the silicon nitride film 3 is naturally oxidized and the silicon oxide film 9 is formed. Since the surface is exposed, the exposed surface is oxidized at a rate that is more than an order of magnitude faster than the oxidation rate of the silicon nitride film 3, and as a result, as shown in FIG. 2(B).
As shown in FIG. 2, the inside of the pinhole 8 is filled with silicon oxide 1O and becomes closed.
こうしたことから、この後にゲート電極等の導電膜７の
形成のため、シリコン酸化膜３の上に金属、ポリシリコ
ン、その他適当なる導電性物質を形成して第１図示のよ
うに素子を完成しても、薄いシリコン窒化膜３に発生し
易いピンホール８を介してのリークの問題は、上記のよ
うに、あらかじめその素子の製造工程の途中において完
全に解消されていることになる。For this reason, metal, polysilicon, or other suitable conductive material is then formed on the silicon oxide film 3 to form a conductive film 7 such as a gate electrode, and the device is completed as shown in the first diagram. However, the problem of leakage through the pinholes 8, which is likely to occur in the thin silicon nitride film 3, is completely resolved in advance during the manufacturing process of the device, as described above.
また得るべき素子が不揮発性半導体メモリの場合には、
第１図に併示されているように、ゲート７の下にそれぞ
れ一部重なり、互いには離間したソース５、ドレイン６
を設けて、記憶内容の読出しを容易にした構造とするこ
とができる。In addition, if the element to be obtained is a nonvolatile semiconductor memory,
As shown in FIG. 1, a source 5 and a drain 6 partially overlap each other under the gate 7 and are spaced apart from each other.
A structure can be provided in which the memory contents can be easily read.
なお、こうした動作に関しては、ピンホール自体は微小
であるため、これを上記のようにして埋めさえすれば、
このような不揮発性半導体メモリにおける記憶情報の書
込みはピンホール８の発生した個所の周りのシリコン窒
化膜中のトラップにて行なわれるので、記憶素子として
の機能自体は何等、損われることがない。Regarding these operations, the pinhole itself is minute, so if you fill it as described above,
Since the writing of storage information in such a nonvolatile semiconductor memory is carried out in the traps in the silicon nitride film around the location where the pinhole 8 is generated, the function as a storage element itself is not impaired in any way.
また、素子がＭＩＳキャパシタのような場合には、シリ
コン窒化膜３の酸化速度は非常に遅いので、本発明によ
り結果として得られる多層膜構造も、ピンホール以外の
部分では極めて薄く形成することが可能であり、したが
って大きな容量値を持つ素子を収率良く得ることができ
る。Furthermore, when the device is a MIS capacitor, the oxidation rate of the silicon nitride film 3 is very slow, so the multilayer structure obtained as a result of the present invention can also be formed extremely thin in areas other than pinholes. Therefore, elements with large capacitance values can be obtained with good yield.
第１図は本発明を適用して得られたＭＩＳ素子構造の一
例を示す断面図、第２図は第１図示素子の製造工程中の
説明図、である。
図中、１はシリコン領域、２はシリコン酸化膜、３はシ
リコン窒化膜、７は導電膜、８はシリコン窒化膜に生成
し得るピンホール、９はシリコン窒化膜表面を酸化して
形成されるシリコン酸化膜、１０はシリコン窒化膜酸化
工程中にピンホール内に成長するシリコン酸化物、であ
る。
才１図FIG. 1 is a cross-sectional view showing an example of a MIS element structure obtained by applying the present invention, and FIG. 2 is an explanatory view of the manufacturing process of the element shown in FIG. In the figure, 1 is a silicon region, 2 is a silicon oxide film, 3 is a silicon nitride film, 7 is a conductive film, 8 is a pinhole that can be formed in the silicon nitride film, and 9 is formed by oxidizing the surface of the silicon nitride film. The silicon oxide film 10 is silicon oxide that grows inside the pinhole during the silicon nitride film oxidation process. 1 figure
Claims (1)
にシリコン窒化膜を形成し、さらにその上に導電膜を形
成するＭＩＳ構造において；上記シリコン窒化膜の形成
後、上記導電膜の形成の前に、該シリコン窒化膜表面を
酸化する工程を含んで成るＭＩＳ構造の製造方法。In an MIS structure in which a silicon nitride film is formed on a silicon region or a silicon oxide film on a silicon region, and a conductive film is further formed on the silicon nitride film; after the formation of the silicon nitride film and before the formation of the conductive film, A method for manufacturing an MIS structure comprising a step of oxidizing the surface of a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29481487A JPS63146471A (en) | 1987-11-20 | 1987-11-20 | Manufacture of mis element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29481487A JPS63146471A (en) | 1987-11-20 | 1987-11-20 | Manufacture of mis element |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56122635A Division JPS5823483A (en) | 1981-08-05 | 1981-08-05 | Nonvolatile semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63146471A true JPS63146471A (en) | 1988-06-18 |
Family
ID=17812598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29481487A Pending JPS63146471A (en) | 1987-11-20 | 1987-11-20 | Manufacture of mis element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63146471A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555587A (en) * | 1991-08-22 | 1993-03-05 | Nec Corp | Mos device and its manufacture |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5231628A (en) * | 1975-06-14 | 1977-03-10 | Fujitsu Ltd | Semiconductor non-volatile memory unit |
| JPS538088A (en) * | 1976-07-12 | 1978-01-25 | Hitachi Ltd | Production of semiconductor device |
| JPS5587490A (en) * | 1978-12-25 | 1980-07-02 | Toshiba Corp | Non-voratile semiconductor memory device |
-
1987
- 1987-11-20 JP JP29481487A patent/JPS63146471A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5231628A (en) * | 1975-06-14 | 1977-03-10 | Fujitsu Ltd | Semiconductor non-volatile memory unit |
| JPS538088A (en) * | 1976-07-12 | 1978-01-25 | Hitachi Ltd | Production of semiconductor device |
| JPS5587490A (en) * | 1978-12-25 | 1980-07-02 | Toshiba Corp | Non-voratile semiconductor memory device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555587A (en) * | 1991-08-22 | 1993-03-05 | Nec Corp | Mos device and its manufacture |
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