JPH01289171A - Manufacture of non-volatile semiconductor storage device - Google Patents
Manufacture of non-volatile semiconductor storage deviceInfo
- Publication number
- JPH01289171A JPH01289171A JP12033588A JP12033588A JPH01289171A JP H01289171 A JPH01289171 A JP H01289171A JP 12033588 A JP12033588 A JP 12033588A JP 12033588 A JP12033588 A JP 12033588A JP H01289171 A JPH01289171 A JP H01289171A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon oxide
- silicon
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、半導体基板上に絶縁膜を介してフローティン
グゲートを設ける不揮発性半導体記憶装置であって、上
記フローティングゲート下の上記絶縁膜は、シリコン酸
化膜−シリコン窒化膜−シリコン酸化膜の３層で構成さ
れてなる不揮発性半導体記憶装置の製造方法に関するも
のである。Detailed Description of the Invention <Industrial Application Field> The present invention provides a nonvolatile semiconductor memory device in which a floating gate is provided on a semiconductor substrate via an insulating film, the insulating film under the floating gate comprising: The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device composed of three layers: silicon oxide film, silicon nitride film, and silicon oxide film.
〈従来の技術〉
フローティングゲートに電荷を注入するトンネル絶縁膜
として、シリコン酸化膜−シリコン窒化膜−シリコン酸
化膜の３層の絶縁膜を使用することは先行技術とし存在
しく特願昭６２−３１１２５２）、また、フローティン
グゲート、コントロールケート間の絶縁膜として、シリ
コン酸化膜、シリコン窒化膜等よＶ成る多層膜を用いる
ことは公知である（％公昭６２−６３４８）。<Prior art> The use of a three-layer insulating film of silicon oxide film-silicon nitride film-silicon oxide film as a tunnel insulating film for injecting charges into a floating gate is known as prior art and is disclosed in Japanese Patent Application No. 311252/1986. ), It is also known to use a multilayer film made of V such as a silicon oxide film, a silicon nitride film, etc. as an insulating film between a floating gate and a control gate (% Publication No. 62-6348).
〈発明が解決しようとする課題〉
トンネル絶縁膜及びフローティングゲート、コントロー
ルゲート間の絶縁膜ともに同様のシリコン酸化膜−シリ
コン窒化膜−シリコン酸化膜の構造となるが、通常の構
造（第２図）では、トンネル絶縁膜がフローティングゲ
ート下にあるため同時に形成することができない。<Problems to be Solved by the Invention> The tunnel insulating film, the floating gate, and the insulating film between the control gates have the same silicon oxide film-silicon nitride film-silicon oxide film structure, but they have a normal structure (Figure 2). In this case, since the tunnel insulating film is under the floating gate, it cannot be formed at the same time.
く課題を解決するための手段〉
フローティングゲートとコントロールゲートとは電気的
に容量結合していれば十分であり、必ずしもフローティ
ングゲート上にコントロールゲートがある必要はない。Means for Solving the Problems> It is sufficient that the floating gate and the control gate are electrically capacitively coupled, and the control gate does not necessarily need to be provided on the floating gate.
そこで、１層目のポリシリコンでコントロールゲートを
作成し、次に、シリコン酸化膜−シリコン窒化膜−シリ
コン酸化膜よＶ成る絶縁膜を、一部はフローティングゲ
ート、コントロールゲート間の絶縁膜として、一部はト
ンネル絶縁膜として同時に形成することで工程を略する
ことが可能となる０
〈実施例〉
以下、本発明の実施例を図面に基づいて説明するＯ
第１図（ａ）〜（ｄ）は本発明の一実施例を示す概略工
程断面図である。Therefore, a control gate was created using the first layer of polysilicon, and then an insulating film consisting of silicon oxide film, silicon nitride film, silicon oxide film, and V was used as a floating gate and an insulating film between the control gates. It is possible to omit the process by forming a part of the tunnel insulating film at the same time.Example: Examples of the present invention will be described below based on the drawings. ) is a schematic process sectional view showing an embodiment of the present invention.
ｆＪＳＩ図（ａ）―於いて、シリコン基板ｌ上にフィー
ルド酸化膜２を形成して素子領域を分離し、素子領域に
イオン注入層３を形成した後、該素子領域に約３０ＯＡ
の厚さのゲート酸化膜４、フィールド酸化膜２上に、リ
ンをドープした％１多結晶シリコン膜から成るコントロ
ールゲート５を形成する０
次に、ｇＩ２１図（ｂ）に示すように、ゲート酸化膜４
の一部を開孔し、トンネル絶縁膜の下層シリコン酸化膜
６を熱酸化により４０〜８０Ａ形成する。fJSI diagram (a) - After forming a field oxide film 2 on a silicon substrate l to isolate the element region, and forming an ion implantation layer 3 in the element region, approximately 30 OA is applied to the element region.
A control gate 5 made of %1 polycrystalline silicon film doped with phosphorus is formed on the gate oxide film 4 and field oxide film 2 with a thickness of 0. Next, as shown in FIG. membrane 4
A hole is opened in a part of the hole, and a lower silicon oxide film 6 of the tunnel insulating film is formed by thermal oxidation to a thickness of 40 to 80 Å.
このとき、コントロールゲート５上にも熱酸化によるシ
リコン酸化膜７が形成される。この酸化膜７は、リンを
ドープした多結晶シリコン上に形成されるため、増速酸
化のため１２０〜２４０Ａ程度生成される０
その後、第１図（ｃ）に示すように、シリコン窒化膜８
をＬＰＣＶＤにより６０〜８０χ形収し、その上に、ウ
ェット雰、囲気中で上層シリコン酸化膜９を１５〜５０
Ａ程度形成し、更に、リンをドープした第２多結晶シリ
コン膜１０を気相成長させる０
次に、第１図（ｄ）に示すように、第２多結晶シリコン
膜、３層絶縁膜を、フォトレジスト、マスク全使用し、
エツチングを行ない、フローティングゲート１０’ と
する。At this time, a silicon oxide film 7 is also formed on the control gate 5 by thermal oxidation. Since this oxide film 7 is formed on polycrystalline silicon doped with phosphorus, the oxidation rate is about 120 to 240 A. Thereafter, as shown in FIG. 1(c), a silicon nitride film 8
A 60 to 80 χ shape is collected by LPCVD, and an upper silicon oxide film 9 of 15 to 50 χ is formed on top of it in a wet atmosphere.
A second polycrystalline silicon film 10 doped with phosphorus is formed by vapor phase growth.Next, as shown in FIG. 1(d), a second polycrystalline silicon film and a three-layer insulating film are formed. , using all photoresists and masks.
Etching is performed to form a floating gate 10'.
その後、従来のＥＥＦＲＯＭと同様に、ソース。Then, like conventional EEFROM, the source.
ドレイン領域の生成、メタル電極生成等により最終形状
を得る。The final shape is obtained by forming the drain region, metal electrode, etc.
〈発明の効果〉
以上詳細に説明したように、本発明によれば、トンネル
絶縁膜及びフローティングゲート、コントロールゲート
間の絶縁膜を、シリコン酸化膜−シリコン窒化膜−シリ
コン酸化膜の３層で同時に形成することが可能となり、
工程を減少させることが可能となるものである。<Effects of the Invention> As described above in detail, according to the present invention, the tunnel insulating film and the insulating film between the floating gate and the control gate are simultaneously formed of three layers: silicon oxide film, silicon nitride film, and silicon oxide film. It becomes possible to form
This makes it possible to reduce the number of steps.
第１図（ａ）乃至（ｄ）は本発明の一実施例を示す概略
工程断面図、第２図は通常のＥＥＰＲＯＭの構造を示す
断面図である。
符号の説明
ｌ：シリコン基板、２：フィールド酸化膜、３：イオン
注入層、４：ゲート酸化膜、５：コントロールゲート、
６：トンネル絶縁膜を構成する下層シリコン酸化膜、７
：フローティングゲート、コントロールゲート間の絶縁
膜を構成する下層シリコン酸化膜、８：絶縁膜を構成す
るシリコン窒化膜、９：絶縁膜全構成する上層シリコン
酸化膜、１０：第２多結晶シリコン膜、ｌＯ′ ：フロ
ーティングゲート。FIGS. 1(a) to 1(d) are schematic process cross-sectional views showing one embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the structure of an ordinary EEPROM. Explanation of symbols 1: silicon substrate, 2: field oxide film, 3: ion implantation layer, 4: gate oxide film, 5: control gate,
6: Lower silicon oxide film constituting the tunnel insulating film, 7
: lower layer silicon oxide film forming the insulating film between the floating gate and control gate, 8: silicon nitride film forming the insulating film, 9: upper silicon oxide film forming the entire insulating film, 10: second polycrystalline silicon film, lO': Floating gate.
Claims (1)
トを設ける不揮発性半導体記憶装置であって、上記フロ
ーティングゲート下の上記絶縁膜は、シリコン酸化膜−
シリコン窒化膜−シリコン酸化膜の３層で構成されてな
る不揮発性半導体記憶装置の製造方法に於いて、 所定領域にコントロールゲートを形成する工程と、 基板上及び上記コントロールゲート上に上記シリコン酸
化膜−シリコン窒化膜−シリコン酸化膜の３層で構成さ
れる絶縁膜を形成する工程と、 上記絶縁膜上にフローティングゲートを形成する工程と
を 有することを特徴とする、不揮発性半導体記憶装置の製
造方法。[Claims] 1. A nonvolatile semiconductor memory device in which a floating gate is provided on a semiconductor substrate via an insulating film, wherein the insulating film under the floating gate is a silicon oxide film.
A method for manufacturing a nonvolatile semiconductor memory device composed of three layers of silicon nitride film and silicon oxide film, which includes the steps of: forming a control gate in a predetermined region; and depositing the silicon oxide film on the substrate and on the control gate. - Manufacturing a nonvolatile semiconductor memory device characterized by comprising a step of forming an insulating film composed of three layers: a silicon nitride film and a silicon oxide film, and a step of forming a floating gate on the insulating film. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12033588A JPH01289171A (en) | 1988-05-16 | 1988-05-16 | Manufacture of non-volatile semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12033588A JPH01289171A (en) | 1988-05-16 | 1988-05-16 | Manufacture of non-volatile semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01289171A true JPH01289171A (en) | 1989-11-21 |
Family
ID=14783715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12033588A Pending JPH01289171A (en) | 1988-05-16 | 1988-05-16 | Manufacture of non-volatile semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01289171A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03181178A (en) * | 1989-12-11 | 1991-08-07 | Toshiba Corp | Nonvolatile semiconductor memory device and its manufacture |
| JPH0465169A (en) * | 1990-07-05 | 1992-03-02 | Toshiba Corp | E2prom device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06171160A (en) * | 1992-12-08 | 1994-06-21 | Seiko Epson Corp | Printing information processor |
| JPH0937062A (en) * | 1995-07-14 | 1997-02-07 | Canon Inc | Device and method for processing image |
-
1988
- 1988-05-16 JP JP12033588A patent/JPH01289171A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06171160A (en) * | 1992-12-08 | 1994-06-21 | Seiko Epson Corp | Printing information processor |
| JPH0937062A (en) * | 1995-07-14 | 1997-02-07 | Canon Inc | Device and method for processing image |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03181178A (en) * | 1989-12-11 | 1991-08-07 | Toshiba Corp | Nonvolatile semiconductor memory device and its manufacture |
| JPH0465169A (en) * | 1990-07-05 | 1992-03-02 | Toshiba Corp | E2prom device |
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