JPS63145325U - - Google Patents

Info

Publication number
JPS63145325U
JPS63145325U JP3754487U JP3754487U JPS63145325U JP S63145325 U JPS63145325 U JP S63145325U JP 3754487 U JP3754487 U JP 3754487U JP 3754487 U JP3754487 U JP 3754487U JP S63145325 U JPS63145325 U JP S63145325U
Authority
JP
Japan
Prior art keywords
semiconductor wafer
sides
view
alignment
sectional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3754487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3754487U priority Critical patent/JPS63145325U/ja
Publication of JPS63145325U publication Critical patent/JPS63145325U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る装置の実施例を示す正面
説明図、第2図はマーキング棒の配置状態を示し
た平面断面図、第3図は目合わせの要領を示す平
面説明図、第4図は目合わせ用のマークを形成し
た半導体ウエーハの概略要部拡大縦断面図、第5
図は本考案の他の実施例を示す正面説明図、第6
図はレジスト膜に目合わせ用のマークを形成した
半導体ウエーハの概略要部拡大縦断面図である。
第7図は半導体ウエーハの拡大縦断面図、第8図
は従来の目合わせの要領を説明するための半導体
ウエーハの平面説明図である。 1……半導体ウエーハ、6……主面、8……他
主面、11a,11b……マーク形成手段、19
,20……目合わせ用マーク。
Fig. 1 is a front explanatory view showing an embodiment of the device according to the present invention, Fig. 2 is a plan sectional view showing the arrangement of marking rods, Fig. 3 is a plan explanatory view showing the method of alignment, and Fig. 4 The figure is a schematic enlarged vertical cross-sectional view of the main part of a semiconductor wafer on which marks for alignment have been formed.
Figure 6 is a front explanatory view showing another embodiment of the present invention.
The figure is an enlarged vertical cross-sectional view of a schematic essential part of a semiconductor wafer in which alignment marks are formed on a resist film.
FIG. 7 is an enlarged vertical sectional view of a semiconductor wafer, and FIG. 8 is a plan view of the semiconductor wafer for explaining the conventional alignment procedure. DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 6... Main surface, 8... Other main surface, 11a, 11b... Mark forming means, 19
, 20... mark for alignment.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 両面にパターンが形成される半導体ウエーハの
両面の対応位置に、対をなす複数の目合わせ用マ
ークを形成するマーク形成手段を対設したことを
特徴とする半導体製造装置。
1. A semiconductor manufacturing apparatus comprising mark forming means for forming a plurality of pairs of alignment marks at corresponding positions on both sides of a semiconductor wafer having patterns formed on both sides.
JP3754487U 1987-03-13 1987-03-13 Pending JPS63145325U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3754487U JPS63145325U (en) 1987-03-13 1987-03-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3754487U JPS63145325U (en) 1987-03-13 1987-03-13

Publications (1)

Publication Number Publication Date
JPS63145325U true JPS63145325U (en) 1988-09-26

Family

ID=30848968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3754487U Pending JPS63145325U (en) 1987-03-13 1987-03-13

Country Status (1)

Country Link
JP (1) JPS63145325U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9115245B2 (en) 2002-10-11 2015-08-25 Boston Scientific Scimed, Inc. Implantable medical devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9115245B2 (en) 2002-10-11 2015-08-25 Boston Scientific Scimed, Inc. Implantable medical devices

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