JPH0187528U - - Google Patents

Info

Publication number
JPH0187528U
JPH0187528U JP18457587U JP18457587U JPH0187528U JP H0187528 U JPH0187528 U JP H0187528U JP 18457587 U JP18457587 U JP 18457587U JP 18457587 U JP18457587 U JP 18457587U JP H0187528 U JPH0187528 U JP H0187528U
Authority
JP
Japan
Prior art keywords
mark
semiconductor substrate
inspecting
utility
sides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18457587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18457587U priority Critical patent/JPH0187528U/ja
Publication of JPH0187528U publication Critical patent/JPH0187528U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案による一実施例の検査パターン
図、第2図は同実施例にシフト分を考慮した検査
パターン図、第3図及び第4図は同検査パターン
の使用状態図である。 a,a……パターン、b,b……間隔
、C,C……線パターン。
FIG. 1 is a diagram of a test pattern of an embodiment of the present invention, FIG. 2 is a diagram of a test pattern of the same embodiment with a shift taken into consideration, and FIGS. 3 and 4 are diagrams of how the same test pattern is used. a 1 , a 2 ... pattern, b 1 , b 2 ... interval, C 1 , C 2 ... line pattern.

Claims (1)

【実用新案登録請求の範囲】 半導体基板上に形成されたパターンを検査する
マークにおいて、 半導体基板に対向させる透明基板面に、対向す
る間隔が不連続なステツプ状に変化する平行な2
辺をもつマークを形成してなることを特徴とする
半導体ウエハーの検査マーク。
[Claims for Utility Model Registration] In a mark for inspecting a pattern formed on a semiconductor substrate, two parallel marks are formed on the surface of a transparent substrate facing the semiconductor substrate, and the opposing distance changes in discontinuous steps.
A semiconductor wafer inspection mark characterized by forming a mark with sides.
JP18457587U 1987-12-02 1987-12-02 Pending JPH0187528U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18457587U JPH0187528U (en) 1987-12-02 1987-12-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18457587U JPH0187528U (en) 1987-12-02 1987-12-02

Publications (1)

Publication Number Publication Date
JPH0187528U true JPH0187528U (en) 1989-06-09

Family

ID=31475926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18457587U Pending JPH0187528U (en) 1987-12-02 1987-12-02

Country Status (1)

Country Link
JP (1) JPH0187528U (en)

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