JPS63141330A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS63141330A
JPS63141330A JP61289341A JP28934186A JPS63141330A JP S63141330 A JPS63141330 A JP S63141330A JP 61289341 A JP61289341 A JP 61289341A JP 28934186 A JP28934186 A JP 28934186A JP S63141330 A JPS63141330 A JP S63141330A
Authority
JP
Japan
Prior art keywords
aluminum
pad electrode
aluminium
out conductor
slit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61289341A
Other languages
Japanese (ja)
Other versions
JPH0519982B2 (en
Inventor
Atsushi Kishi
岸　淳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61289341A priority Critical patent/JPS63141330A/en
Publication of JPS63141330A publication Critical patent/JPS63141330A/en
Publication of JPH0519982B2 publication Critical patent/JPH0519982B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To absorb any mechanical stress imposed during bonding process to shorten the distance between an aluminium pad electrode and inner aluminium wiring group arranged adjacently thereto by a method wherein slit type throughholes are made in one of a bonding surface of aluminium pad electrode and an aluminium leading out conductor or both of them. CONSTITUTION:Slit type throughholes 6 arranged in parallel with inner aluminium wiring group 4 and an insulation-protective film 7 of aluminium pad electrode are provided on the surface of an aluminium leading out conductor 5. When a bonding wire is bonded on an aluminium pad electrode 3 by thermocompression, a part of bonding stress imposed is propagated above the aluminium leading out conductor 5 in the direction making a right angle with the inner wiring group 4 to be absorbed by deforming said slit type throughholes 6. Through these procedures, the extension of aluminium leading out conductor 5 in the direction of lateral axis can be reduced markedly to shorten the distance to adjoining inner aluminium wiring down to 1/2 or 1/3 or conventional distance.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体集積回路装置に関し、特にアルミ・パッ
ド電極の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of an aluminum pad electrode.

（従来の技術） 従来、半導体集積回路装置のパッド電極にはアルミ材が
多用され、・また、半導体基板上では内部アルミ配線群
と隣接して設けられる。周知の通りパッド電極は半導体
集積回路装置の外部取出電極であって半導体基板の最上
層に位置し組立ての際この面上にポンディング・ワイヤ
が熱圧着される。(Prior Art) Conventionally, aluminum material is often used for pad electrodes of semiconductor integrated circuit devices, and they are provided adjacent to internal aluminum wiring groups on a semiconductor substrate. As is well known, a pad electrode is an external electrode of a semiconductor integrated circuit device, and is located on the top layer of a semiconductor substrate, and a bonding wire is bonded by thermocompression onto this surface during assembly.

この熱圧着の際、アルミ・パッド電極および内部アルミ
配線との接続部を形成するアルミ引出導体部はボンディ
ング応力の伝ばん方向にそれぞれ伸長するので内部アル
ミ配線との接触を回避する必要上アルミ引出導体部は隣
接する内部アルミ配線と２０〜３０μ常程度離間される
。During this thermocompression bonding, the aluminum lead conductors that form the connections with the aluminum pad electrodes and internal aluminum wiring expand in the direction of propagation of bonding stress, so it is necessary to avoid contact with the internal aluminum wiring, so The conductor portion is usually separated from the adjacent internal aluminum wiring by about 20 to 30 μm.

（発明が解決しようとする問題点） しかしながら、微細加工技術が進み半導体装置の高密度
化および高速化が今日のように進展して来ると、能動素
子を含む電子回路の縮小化の達成度に比ベアルミ・パッ
ド電極周辺の遅れが目立つようになシその対策が望まれ
ている。すなわち、通常の内部アルミ配線の相互間距離
が僅か３〜４μｍにすぎないのにパッド電極の離間距離
がその１０倍にも達していることが注目され始めており
この縮小化が望まれている。(Problems to be Solved by the Invention) However, as microfabrication technology progresses and semiconductor devices become more dense and faster than they are today, the degree of miniaturization of electronic circuits including active elements is becoming increasingly difficult. The delay around aluminum pad electrodes has become noticeable compared to other countries, and countermeasures are desired. That is, although the distance between normal internal aluminum wirings is only 3 to 4 .mu.m, attention is beginning to be paid to the fact that the distance between pad electrodes is ten times that distance, and there is a desire to reduce this distance.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記の情況に鑑み、隣接する内部アル
ミ配線との離間距離を縮小化し得るアルミ・パッド電極
構造を備えた半導体集積回路装置を提供することである
。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device having an aluminum pad electrode structure that can reduce the distance between adjacent internal aluminum wiring lines.

〔発明の構成〕[Structure of the invention]

本発明によれば、半導体集積回路装置は、半導体基板と
、前記半導体基板のフィールド絶縁膜上に互いに隣接し
て形成されるアルミ・バンド電極および内部アルミ配線
群と、前記内部アルミ配線群の少なくとも一つと電気接
続されるアルミ・パッド電極のアルミ引出導体部と、前
記アルミ・パッド電極および或いはアルミ引出導体部の
面上にボンディング応力の伝ばん方向と対面する向きに
それぞれ配設されるスリット状の貫通孔とを備えること
を含む。According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, an aluminum band electrode and an internal aluminum wiring group formed adjacent to each other on a field insulating film of the semiconductor substrate, and at least one of the internal aluminum wiring group. an aluminum lead-out conductor portion of an aluminum pad electrode to be electrically connected to the aluminum pad electrode, and a slit-shaped slit provided on the surface of the aluminum pad electrode and/or the aluminum lead-out conductor portion in a direction facing the bonding stress propagation direction. and a through hole.

〔問題点を解決するための手段〕[Means for solving problems]

すなわち１本発明によれば、アルミ・パッド電極および
アルミ引出導体部の何れか一方または両方の面上にスリ
ット状の貫通孔がボンティングの際発生する応力の伝ば
ん方向と対面する向きにそれぞれ配設される。具体的に
はこれらの貫通孔はアルミ引出導体部上では隣接する内
部アルミ配線群と平行に、また、アルミ・パッド電極上
ではアルミ引出導体部と対向する縁端面の一部または電
極面の縁端部を通る円周に沿って円周状に配設される。In other words, according to the present invention, slit-like through holes are formed on either or both surfaces of the aluminum pad electrode and the aluminum lead conductor in a direction facing the propagation direction of stress generated during bonding. will be placed. Specifically, these through holes are placed parallel to the adjacent internal aluminum wiring group on the aluminum lead conductor, and on a part of the edge surface facing the aluminum lead conductor or the edge of the electrode surface on the aluminum pad electrode. They are arranged circumferentially along the circumference passing through the end.

〔作用〕[Effect]

ここで、配設され次スリット状の貫通孔はアルミ・パッ
ド電極またはアルミ引出導体部の面上を伝ばんするボン
ディング応力を受けて変形しこれを吸収してパッド電極
全体の伸長を緩和するよう作用する。従って、アルミ引
出導体部と隣接する内部アルミ配線との離間距離は従来
の１／２〜１／３に縮小される。この際、配設する貫通
孔の形状は矩形に限らず円形、だ円形その他任意の形に
設定することも可能である。以下図面を参照して本発明
の詳細な説明する。Here, the slit-shaped through hole that is provided is deformed by the bonding stress that propagates on the surface of the aluminum pad electrode or the aluminum lead-out conductor part, absorbing this stress, and mitigating the expansion of the entire pad electrode. act. Therefore, the distance between the aluminum lead-out conductor and the adjacent internal aluminum wiring is reduced to 1/2 to 1/3 of the conventional one. At this time, the shape of the through hole to be provided is not limited to a rectangular shape, but can also be set to a circular shape, an oval shape, or any other arbitrary shape. The present invention will be described in detail below with reference to the drawings.

〔実施例〕〔Example〕

第１図（ａｌおよび（ｂｌは本発明の一実施例を示すア
ルミ・バット電極近傍の平面図およびそのＡ−Ａ’断面
図である。本実施例によれば、本発明の半導体集積回路
装置は、半導体基板１と、このフィールド絶縁膜２上に
互いに隣接して形成されるアルミ・パッド電極３および
内部アルミ配線群４と、内部アルミ配線の一つと電気接
続されるアルミ・パッド電極のアルミ引出導体部５と、
このアルミ引出導体部５の面上に内部アルミ配線群４と
平行に配設されたスリット状の貫通孔６と、アルミ・パ
ッド電極の絶縁保護膜７とを含む。FIG. 1 (al and (bl) are a plan view of the vicinity of an aluminum butt electrode and a sectional view thereof taken along the line A-A' showing one embodiment of the present invention. According to this embodiment, the semiconductor integrated circuit device of the present invention is a semiconductor substrate 1, an aluminum pad electrode 3 and an internal aluminum wiring group 4 formed adjacent to each other on this field insulating film 2, and an aluminum pad electrode electrically connected to one of the internal aluminum wirings. A drawer conductor part 5,
This aluminum lead-out conductor portion 5 includes a slit-shaped through hole 6 arranged parallel to the internal aluminum wiring group 4 on the surface thereof, and an insulating protection film 7 for the aluminum pad electrode.

本実凡例によれば、アルミ・パッド電極３上にボンディ
ング・ワイヤが熱圧着された除虫じるホンディング応力
の一部はアルミ引出溝体部５上を内部アルミ配線群４と
直角方向に伝ばんするがこの勢力はスリット状の貫通孔
６を変形することによって消費される。従って、アルミ
引出導体部５の横軸方向の伸長は著しく緩和されるので
隣接する内部アルミ配線との離間距離りを従来の１／２
〜１／３に縮小化し得る。According to this legend, a part of the bonding stress caused by thermocompression bonding of the bonding wire on the aluminum pad electrode 3 is applied to the aluminum lead groove 5 in a direction perpendicular to the internal aluminum wiring group 4. However, this force is consumed by deforming the slit-shaped through hole 6. Therefore, the extension of the aluminum lead-out conductor section 5 in the horizontal axis direction is significantly reduced, so that the separation distance from the adjacent internal aluminum wiring can be reduced to 1/2 of that of the conventional one.
It can be reduced to ~1/3.

第２図（ａｌおよび（ｂｌは本発明にかかるスリット状
貫通孔のボンディング応力吸収状況図でボンディング工
程の開始前および終了後にそれぞれ対応しており、スリ
ット状の貫通孔５が応力を吸収した際変形する様子を示
したものでおる。FIG. 2 (al and (bl) are diagrams of the bonding stress absorption situation of the slit-like through-hole according to the present invention, which correspond to before and after the start and end of the bonding process, respectively, and when the slit-like through-hole 5 absorbs stress. This shows how it transforms.

第３図および第４図は本発明の他の実施例をそれぞれ示
すアルミ・パッド電極近傍の平面図である。これら２つ
の実施例図には絶縁保護膜７が省略された以外は全て前
実九例と共通符号が付されている。ここで、スリット状
の貫通孔６は第３図の実施例ではアルミ引出導体５と対
向する位置のアルミ・パッド電極の縁端面上に形成され
、また第４図の実施例ではアルミ引出導体５の面上と共
にアルミ・パッド電極３の縁端面に対して円周状にそれ
ぞれ配設される。この場合、何れの実施例においてもス
リット状貫通孔６はボンディング応力を有効に吸収して
アルミ・パッド電極全体の伸長を著しく緩和し得る。特
に第４図の実施例の如くパッド電極および引出導体部の
両方に配設するとその伸長緩和効果はよシ一層顕著とな
る。3 and 4 are plan views of the vicinity of aluminum pad electrodes showing other embodiments of the present invention, respectively. These two embodiment drawings have the same reference numerals as the previous nine embodiments, except that the insulating protective film 7 is omitted. Here, in the embodiment shown in FIG. 3, the slit-shaped through hole 6 is formed on the edge surface of the aluminum pad electrode at a position facing the aluminum lead-out conductor 5, and in the embodiment shown in FIG. They are arranged circumferentially on the surface of the aluminum pad electrode 3 as well as on the edge surface of the aluminum pad electrode 3. In this case, in any of the embodiments, the slit-like through holes 6 can effectively absorb the bonding stress and can significantly reduce the expansion of the entire aluminum pad electrode. In particular, when it is provided on both the pad electrode and the lead-out conductor portion as in the embodiment shown in FIG. 4, the elongation relaxation effect becomes even more remarkable.

以上の実施例はもちろん本発明の単なる例示にすぎない
ので、スリット状貫通孔６の形状、配設の仕方および組
合せの選択は個々の半導体装置に合わせ適宜決定するこ
とが可能である。また、アルミ引出導体部５の大きさを
多少広げる必要が生じるが内部アルミ配線群４との離間
距離りの縮小化には全く関係をもたないので特に問題と
なることはない。Of course, the above-described embodiments are merely illustrative of the present invention, and the shape, arrangement, and combination of the slit-like through holes 6 can be appropriately determined in accordance with each individual semiconductor device. Further, although it becomes necessary to increase the size of the aluminum lead-out conductor portion 5 to some extent, this does not cause any particular problem since it has no relation to reducing the distance from the internal aluminum wiring group 4.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、アルミ・
パッド電極のボンディング面およびアルミ引出導体部の
何れか一方または両方にスリット状の貫通孔を配設する
ことによシボンディングの除虫じる機械的応力を吸収し
てアルミ・パッド電極全体の伸長を有効に緩和し得るの
で、アルミ・パッド電極とこれに隣接配置される内部ア
ルミ配線群との離間距離を従来の１／２〜１／３に短縮
せしめ得る。すなわち、電子回路の微細化技術と相俟っ
てパッド電極周辺の縮小化も達成することができるので
集積度の向上に顕著なる効果を奏し得る。As explained in detail above, according to the present invention, aluminum
By providing a slit-like through hole in either or both of the bonding surface of the pad electrode and the aluminum lead-out conductor, the mechanical stress caused by bonding is absorbed and the entire aluminum pad electrode extends. Since the distance between the aluminum pad electrode and the internal aluminum wiring group arranged adjacent thereto can be reduced to 1/2 to 1/3 of the conventional distance. That is, in conjunction with electronic circuit miniaturization technology, the area around the pad electrode can be reduced, which can have a significant effect on improving the degree of integration.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）および（ｂ）は本発明の一実施例を示すア
ルミ・パッド電極近傍の平面図およびそのＡ−Ａ’断面
図、第２図（ａ）およびｔｂ＋は本発明にかかるスリッ
ト状貫通孔のボンディング応力吸収状況図、第３図およ
び第４図は本発明の他の実施例を示すアルミ・パッド電
極近傍の平面図である。 ｌ・・・半導体基板、２・・・フィールド絶縁膜、３・
・・アルミ・パッド電極、４・・・内部アルミ配線群、
５・・・アルミ引出導体部、６・・・スリット状の貫通
孔、７・・・絶縁保護膜、Ｌ・・・離間距離。 （αン ｃｂ） 茅　１　　図 ４　：　　ｖｆ４１１１リレミｋｔ１ｇＲｔ　　：　　
Ｒｙ、’Ｔｙｒ＝：Ａｉ茅　３　図 斧　４　凶 第　２　刀FIGS. 1(a) and (b) are a plan view of the vicinity of an aluminum pad electrode and its AA' cross-sectional view showing one embodiment of the present invention, and FIGS. 2(a) and tb+ are slits according to the present invention. 3 and 4 are plan views of the vicinity of aluminum pad electrodes showing other embodiments of the present invention. l...Semiconductor substrate, 2...Field insulating film, 3.
...Aluminum pad electrode, 4...Internal aluminum wiring group,
5... Aluminum lead-out conductor portion, 6... Slit-shaped through hole, 7... Insulating protective film, L... Separation distance. (αn cb) Kaya 1 Figure 4: vf4111 reremi kt1gRt:
Ry, 'Tyr=: Ai Kaya 3 Ax 4 Evil 2nd sword

Claims (4)

【特許請求の範囲】[Claims] （１）半導体基板と、前記半導体基板のフィールド絶縁
膜上に互いに隣接して形成されるアルミ・パッド電極お
よび内部アルミ配線群と、前記内部アルミ配線群の少な
くとも一つと電気接続されるアルミ・パッド電極のアル
ミ引出導体部と、前記アルミ・パッド電極および或いは
アルミ引出導体部の面上にボンディング応力の伝はん方
向と対面する向きにそれぞれ配設されるスリット状の貫
通孔とを備えることを特徴とする半導体集積回路装置。(1) A semiconductor substrate, an aluminum pad electrode and an internal aluminum wiring group formed adjacent to each other on a field insulating film of the semiconductor substrate, and an aluminum pad electrically connected to at least one of the internal aluminum wiring group. An aluminum lead-out conductor portion of the electrode, and slit-like through holes respectively arranged on the surface of the aluminum pad electrode and/or the aluminum lead-out conductor portion in a direction facing the bonding stress propagation direction. Features of semiconductor integrated circuit devices. （２）前記スリット状の貫通孔が前記アルミ引出導体部
面上に内部アルミ配線群と平行して配設されることを特
徴とする特許請求の範囲第（１）項記載の半導体集積回
路装置。(2) The semiconductor integrated circuit device according to claim (1), wherein the slit-shaped through hole is arranged on the surface of the aluminum lead-out conductor portion in parallel with the internal aluminum wiring group. . （３）前記スリット状の貫通孔が前記アルミ・パッド電
極の縁端面上にアルミ引出導体部と対向して配設される
ことを特徴とする特許請求の範囲第（１）項記載の半導
体集積回路装置。(3) The semiconductor integrated circuit according to claim (1), wherein the slit-shaped through hole is arranged on the edge surface of the aluminum pad electrode so as to face the aluminum lead-out conductor part. circuit device. （４）前記スリット状の貫通孔が前記アルミ・パッド電
極の縁端面上に円周状に配設されることを特徴とする特
許請求の範囲第（１）項記載の半導体集積回路装置。(4) The semiconductor integrated circuit device according to claim (1), wherein the slit-shaped through holes are arranged circumferentially on the edge surface of the aluminum pad electrode.
JP61289341A 1986-12-03 1986-12-03 Semiconductor integrated circuit device Granted JPS63141330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61289341A JPS63141330A (en) 1986-12-03 1986-12-03 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61289341A JPS63141330A (en) 1986-12-03 1986-12-03 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS63141330A true JPS63141330A (en) 1988-06-13
JPH0519982B2 JPH0519982B2 (en) 1993-03-18

Family

ID=17741946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61289341A Granted JPS63141330A (en) 1986-12-03 1986-12-03 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS63141330A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804883A (en) * 1995-07-13 1998-09-08 Samsung Electronics Co., Ltd. Bonding pad in semiconductor device
WO2006046302A1 (en) * 2004-10-29 2006-05-04 Spansion Llc Semiconductor device and manufacturing method therefor
JP2007208209A (en) * 2006-02-06 2007-08-16 Fujitsu Ltd Semiconductor device and method for fabrication thereof
US7514790B2 (en) 2005-06-02 2009-04-07 Seiko Epson Corporation Semiconductor device and method of manufacturing a semiconductor device
JP2009111073A (en) * 2007-10-29 2009-05-21 Elpida Memory Inc Semiconductor device
KR100903696B1 (en) * 2007-05-22 2009-06-18 스펜션 엘엘씨 Semiconductor device and manufacturing method therefor
JP2012160633A (en) * 2011-02-02 2012-08-23 Lapis Semiconductor Co Ltd Wiring structure of semiconductor device and method of manufacturing the same
JP2013157390A (en) * 2012-01-27 2013-08-15 Kyocera Corp Wiring board and electronic apparatus
JPWO2012073302A1 (en) * 2010-11-29 2014-05-19 トヨタ自動車株式会社 Semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804883A (en) * 1995-07-13 1998-09-08 Samsung Electronics Co., Ltd. Bonding pad in semiconductor device
GB2434917B (en) * 2004-10-29 2010-05-26 Spansion Llc Semiconductor device and maufacturing method therefor
WO2006046302A1 (en) * 2004-10-29 2006-05-04 Spansion Llc Semiconductor device and manufacturing method therefor
GB2434917A (en) * 2004-10-29 2007-08-08 Spansion Llc Semiconductor device and maufacturing method thereof
JPWO2006046302A1 (en) * 2004-10-29 2008-05-22 スパンション エルエルシー Semiconductor device and manufacturing method thereof
JP4777899B2 (en) * 2004-10-29 2011-09-21 スパンション エルエルシー Semiconductor device
US7514790B2 (en) 2005-06-02 2009-04-07 Seiko Epson Corporation Semiconductor device and method of manufacturing a semiconductor device
JP2007208209A (en) * 2006-02-06 2007-08-16 Fujitsu Ltd Semiconductor device and method for fabrication thereof
KR100903696B1 (en) * 2007-05-22 2009-06-18 스펜션 엘엘씨 Semiconductor device and manufacturing method therefor
JP2009111073A (en) * 2007-10-29 2009-05-21 Elpida Memory Inc Semiconductor device
JPWO2012073302A1 (en) * 2010-11-29 2014-05-19 トヨタ自動車株式会社 Semiconductor device
JP2012160633A (en) * 2011-02-02 2012-08-23 Lapis Semiconductor Co Ltd Wiring structure of semiconductor device and method of manufacturing the same
JP2013157390A (en) * 2012-01-27 2013-08-15 Kyocera Corp Wiring board and electronic apparatus

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