JPS63283041A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63283041A JPS63283041A JP11845687A JP11845687A JPS63283041A JP S63283041 A JPS63283041 A JP S63283041A JP 11845687 A JP11845687 A JP 11845687A JP 11845687 A JP11845687 A JP 11845687A JP S63283041 A JPS63283041 A JP S63283041A
- Authority
- JP
- Japan
- Prior art keywords
- pad electrode
- hole
- bonding
- lead
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 37
- 229910052782 aluminium Inorganic materials 0.000 abstract description 37
- 230000000644 propagated effect Effects 0.000 abstract description 2
- 239000004411 aluminium Substances 0.000 abstract 3
- 230000006835 compression Effects 0.000 abstract 2
- 238000007906 compression Methods 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に係シ、特にアルミニウム
・パッド電極に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices, and particularly to aluminum pad electrodes.
第４図（ａ）、第４図（ｂ）、第４図（Ｃ）は、従来の
半導体集積回路装置をそれぞれ示す平面図、断面図。FIG. 4(a), FIG. 4(b), and FIG. 4(C) are a plan view and a cross-sectional view, respectively, showing a conventional semiconductor integrated circuit device.
ボンディング後の断面図である。第４図（ａ） 、 （
ｂ）において、半導体基板１上に、フィールド絶縁膜２
が形成され、さらにアルミニウム［株］パッド電極３、
アルミニウム引出導体部５、内部アルミニウム配 ・
線群４が形成され、表面保護膜７が形成される。FIG. 3 is a cross-sectional view after bonding. Figure 4(a), (
In b), a field insulating film 2 is formed on the semiconductor substrate 1.
is formed, and furthermore, an Aluminum [Co., Ltd.] pad electrode 3,
Aluminum lead-out conductor part 5, internal aluminum wiring
Line groups 4 are formed, and a surface protection film 7 is formed.
次に第４図（Ｃ）に示すように、ボンディングワイヤ８
を熱圧着する。この際、導体部５が坤長されて、アルミ
ニウム配線群４と電気的に短絡する事故が生じる。Next, as shown in FIG. 4(C), the bonding wire 8
Heat and press. At this time, the conductor portion 5 is elongated, causing an electrical short circuit with the aluminum wiring group 4.
このような半導体集積回路装置のパッド電極３には、ア
ルミニウム材が多用され、また半導体基板１上では内部
アルミニウム配線群４と隣接して設けられる。The pad electrode 3 of such a semiconductor integrated circuit device is often made of aluminum, and is provided adjacent to the internal aluminum wiring group 4 on the semiconductor substrate 1.
このパッド電極３は、半導体集積回路装置の外部取出電
極であって、組立ての際この面上にボンディング・ワイ
ヤ８が熱圧着される。This pad electrode 3 is an electrode taken out to the outside of the semiconductor integrated circuit device, and a bonding wire 8 is thermocompressed onto this surface during assembly.
この熱圧着の際、アルミニウム・パッド電極３、および
内部アルミニウム配線との接続部を形成するアルミニウ
ム引出導体部５は、ボンディング応力の伝ばん方向にそ
れぞれ伸長するので、内部アルミニウム配線群４との接
触事故が生じ、これを回避するため、アルミニウム引出
導体部５は、隣接する内部アルミニウム配線群４と２０
μｍ乃至３０μｍ程度離間される。During this thermocompression bonding, the aluminum pad electrode 3 and the aluminum lead-out conductor portion 5 that forms the connection portion with the internal aluminum wiring extend in the direction of propagation of bonding stress, so that contact with the internal aluminum wiring group 4 In order to avoid accidents, the aluminum lead-out conductor section 5 is connected to the adjacent internal aluminum wiring groups 4 and 20.
They are spaced apart by about μm to 30 μm.
微細加工技術が進み、半導体装置の高密度化および高速
化が今日のように進展して来ると、能動素子を含む電子
回路の縮小化の達成度に比べ、アルミニウム・パッド電
極周辺の遅れが目立つようになシ、その対策が強く望ま
れている。As microfabrication technology progresses and the density and speed of semiconductor devices progress as they do today, there is a noticeable lag in the area around aluminum pad electrodes compared to the degree of miniaturization of electronic circuits including active elements. There is a strong need for countermeasures against this problem.
すなわち、通常の内部アルミニウム配線の相互間距離が
、わずか３μｍ乃至４μｍにすぎないのに、パッド電極
の離間距離が、その１０倍にも達していることが注目さ
れ始めておシ、この縮少化が望まれている。In other words, although the distance between normal internal aluminum interconnects is only 3 μm to 4 μm, attention has begun to be paid to the fact that the distance between pad electrodes is ten times that distance. is desired.
本発明の目的は、前記問題点が解決され、パッド電極３
上の高集積化を可能とする半導体集積回路装置を提供す
ることにある。It is an object of the present invention to solve the above-mentioned problems and to
An object of the present invention is to provide a semiconductor integrated circuit device that enables high integration as described above.
本発明の構成は、半導体基板と、前記半導体基板のフィ
ールド絶縁膜上に互いに隣接して形成されるパッド電極
および内部配線群と、前記ベッド電極および内部配線群
上の表面保護膜と、前記内部配線群の少なくとも１つと
電気接続されるパッド電極の引出導体部とを備えた半導
体集積回路装置において、前記引出導体部に重複する様
に、ボンディング応力の伝ばん方向と対面するような向
きに配置される貫通孔を前記表面保護膜に備えたことを
特徴とする。The structure of the present invention includes a semiconductor substrate, a pad electrode and an internal wiring group formed adjacent to each other on a field insulating film of the semiconductor substrate, a surface protection film on the bed electrode and the internal wiring group, and a surface protection film on the bed electrode and internal wiring group, and In a semiconductor integrated circuit device comprising a lead-out conductor portion of a pad electrode that is electrically connected to at least one of the wiring groups, the lead-out conductor portion is arranged so as to overlap with the lead-out conductor portion and face the propagation direction of bonding stress. The surface protection film is characterized in that the surface protection film is provided with a through-hole.
次に図面を参照しながら本発明の詳細な説明する０
第１図（ａ）、第１図（ｂ）、第１図ＦＣ）は本発明の
一実施例の半導体集積回路装置を示すアルミ、パッド電
極近傍の平面図、そのＡ−Ｂ断面図、ボンディング後の
断面図である。Next, the present invention will be described in detail with reference to the drawings. Figures 1(a), 1(b), and 1FC) show an aluminum semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a plan view of the vicinity of a pad electrode, a cross-sectional view taken along the line A-B, and a cross-sectional view after bonding.
まず、第１図（ａ）、第１図（ｂ）において、本実施例
の半導体集積回路装置は、半導体基板１と、この上に形
成されたフィールド絶縁膜２上に互いに隣接して形成さ
れるアルミニウム・パッド電極３、および内部アルミニ
ウム配線群４と、内部アルミニウム配線群４の１つと電
気的に接続されるアルミニウム・パッド電極のアルミニ
ウム引出導体部５と、表面保護膜７に設けられたアルミ
ニウム・パッド電極３上の外部アルミニウム配線接合用
の貫通孔及びアルミニウム引出導体部５にオーバーラツ
プされたスリット状の貫通孔６を含み、構成される。First, in FIGS. 1(a) and 1(b), the semiconductor integrated circuit device of this embodiment is formed adjacent to each other on a semiconductor substrate 1 and a field insulating film 2 formed thereon. the aluminum pad electrode 3 provided on the internal aluminum wiring group 4, the aluminum lead conductor portion 5 of the aluminum pad electrode electrically connected to one of the internal aluminum wiring groups 4, and the aluminum provided on the surface protection film 7. - Contains a through hole for bonding external aluminum wiring on the pad electrode 3 and a slit-shaped through hole 6 overlapping the aluminum lead conductor portion 5.
本実施例によれば、第１図（Ｃ）に示すように、アルミ
ニウムーハ、ンド電極３上にボンディングワイヤ８が熱
圧着された際、生じるボンディング応力の一部は、アル
ミニウム引出導体部５上を内部アルミ配線群４と直角方
向に伝搬するが、この勢力は表面保護膜７のスリットで
、ストレスが貫通孔方向にもかがシ軽減される。According to this embodiment, as shown in FIG. 1(C), when the bonding wire 8 is thermocompression bonded onto the aluminum lead conductor 3, a part of the bonding stress generated is transferred to the aluminum lead conductor 5. Although this force is propagated in a direction perpendicular to the internal aluminum wiring group 4, the stress is also reduced in the direction of the through hole due to the slit in the surface protection film 7.
従って、アルミニウム引出導体部５の横軸方向の伸長は
著しく緩和されるので、隣接する内部アルミニウム配線
との離間距離りを従来の１７２乃至１／３に縮小化し得
る。Therefore, the extension of the aluminum lead-out conductor portion 5 in the horizontal axis direction is significantly relaxed, so that the distance between the aluminum lead-out conductor portion 5 and the adjacent internal aluminum wiring can be reduced to 172 to 1/3 of the conventional distance.
すなわち本実施例によれば、アルミ引出導体部５上で、
表面保護膜７にスリット状の貫通孔６が、ボンディング
の際発生する応力の伝搬方向と対面する向きに配置され
る。That is, according to this embodiment, on the aluminum lead-out conductor section 5,
A slit-shaped through hole 6 is arranged in the surface protection film 7 in a direction facing the propagation direction of stress generated during bonding.
具体的には、これらの保護膜７の貫通孔６は、引出導体
部５上では隣接する配線群４と平行に配設される。Specifically, these through-holes 6 of the protective film 7 are arranged in parallel with the adjacent wiring group 4 on the lead-out conductor portion 5 .
ここで配設された保護膜７のスリット状の貫通孔６はパ
ッド電極３または引出導体部５の面上を伝搬するボンデ
ィング応力を受けて変形するアルミニウムを吸い上げ、
パッド電極３全体の伸長を緩和するよう作用する。The slit-shaped through holes 6 of the protective film 7 provided here suck up aluminum deformed by the bonding stress propagating on the surface of the pad electrode 3 or the lead-out conductor portion 5.
It acts to alleviate the expansion of the pad electrode 3 as a whole.
尚、配設される貫通孔６の形状は第１図（ａ）に示す矩
形に限らず、円形（第２図）やだ円形、Ｌ字形（第３図
）、コの字形、その他任意の形に設定することも可能で
ある。Note that the shape of the through hole 6 provided is not limited to the rectangular shape shown in FIG. It is also possible to set the shape.
第２図、第３図はいずれも本発明の他の実施例をそれぞ
れ示すパッド電極３近傍の平面図である。2 and 3 are plan views of the vicinity of the pad electrode 3, respectively, showing other embodiments of the present invention.
ここで第２図では、表面保護膜７の貫通孔６は引出導体
部５の上に円形で多数設けている。Here, in FIG. 2, a large number of circular through holes 6 of the surface protection film 7 are provided above the lead-out conductor portion 5. As shown in FIG.
又第３図では表面保護膜７の貫通孔６は、アルミニウム
電極３上の外部接続の為の貫通孔と一体となして設けら
れている。Further, in FIG. 3, the through-hole 6 of the surface protection film 7 is provided integrally with the through-hole for external connection on the aluminum electrode 3.
以上説明した様に、本発明によれば、表面保護膜のスリ
ット状の貫通孔を配設することによシ、ボンディングの
除虫じる機械的応力を吸収して、パッド電極近傍の伸長
を有効に緩和し得るので、パッド電極とこれに隣接配置
される内部アルミ配線群との離間距離を従来の１／２〜
１／３に短縮せしめ、電子回路の微細化技術と相まって
パッド電極周辺の縮小化も達成することができ、集積度
の向上に寄与する効果がある。As explained above, according to the present invention, by providing the slit-like through holes in the surface protective film, the mechanical stress caused by bonding is absorbed and the elongation near the pad electrode is suppressed. Since the relaxation can be effectively achieved, the distance between the pad electrode and the internal aluminum wiring group placed adjacent to it can be reduced to 1/2 to 1/2 of the conventional distance.
By reducing the size to 1/3, and in combination with electronic circuit miniaturization technology, it is possible to achieve a reduction in the area around the pad electrode, which has the effect of contributing to an improvement in the degree of integration.
第１図（ａ）は本発明の一実施例の半導体集積回路装置
のアルミニウム・パッド電極近傍の平面図、第１図（ｂ
）は第１図（ａ）のＡ−Ｂ線に沿って切断して見た断面
図、第１図（Ｃ）は第１図（ｂ）においてボンディング
した状態を示す断面図、第２図、第３図はいずれも本発
明の他の実施例の半導体集積回路装置パッド電極近傍の
平面図、第４図（ａｌは従来の半導体集積回路装置のパ
ッド電極近傍の平面図、第４図（ｂ）は第４図（ａ）の
Ａ−Ｂ線に沿って切断して見た断面図、第４図（Ｃｌは
第４図（ｂ）におけるボンディング番ワイヤ熱圧着後を
示す断面図である。
１・・・・・・半導体基鈑、２・・・・・・フィールド
絶縁膜、３・・・・・・アルミニウム拳パッド電極、４
・・・・・・内部アルミ配線群、５・・・・・・アルミ
引出導体部、６・・・・・・表面保護膜スリット状の貫
通孔、７・・・・・・表面保護膜、８・・・・・・熱圧
着後のボンディングワイヤ、Ｌ・・・・・・離間距離。FIG. 1(a) is a plan view of the vicinity of an aluminum pad electrode of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG.
) is a sectional view taken along line A-B in FIG. 1(a), FIG. 1(C) is a sectional view showing the bonded state in FIG. 1(b), FIG. 3 is a plan view near the pad electrode of a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 4 (al is a plan view near the pad electrode of a conventional semiconductor integrated circuit device, and FIG. ) is a cross-sectional view taken along the line A-B in FIG. 4(a), and FIG. 4 (Cl is a cross-sectional view showing the bonding wire after thermocompression bonding in FIG. 4(b)). 1... Semiconductor substrate, 2... Field insulating film, 3... Aluminum fist pad electrode, 4
...Internal aluminum wiring group, 5...Aluminum lead-out conductor section, 6...Surface protection film slit-shaped through hole, 7...Surface protection film, 8... Bonding wire after thermocompression bonding, L... Separation distance.
Claims (1)
互いに隣接して形成されるパッド電極および内部配線群
と、前記パッド電極および内部配線群上の表面保護膜と
、前記内部配線群の少なくとも１つと電気接続されるパ
ッド電極の引出導体部とを備えた半導体集積回路装置に
おいて、前記引出導体部に重複する様に、ボンディング
応力の伝搬方向と対面するような向きに配置される貫通
孔を前記表面保護膜に備えたことを特徴とする半導体集
積回路装置。a semiconductor substrate, a pad electrode and an internal wiring group formed adjacent to each other on a field insulating film of the semiconductor substrate, a surface protection film on the pad electrode and internal wiring group, and at least one of the internal wiring group; In a semiconductor integrated circuit device having a lead-out conductor portion of a pad electrode to be electrically connected, a through-hole is formed on the surface of the semiconductor integrated circuit device, and the through-hole is arranged in a direction facing the bonding stress propagation direction so as to overlap with the lead-out conductor portion. A semiconductor integrated circuit device comprising a protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11845687A JPS63283041A (en) | 1987-05-14 | 1987-05-14 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11845687A JPS63283041A (en) | 1987-05-14 | 1987-05-14 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63283041A true JPS63283041A (en) | 1988-11-18 |
| JPH0586064B2 JPH0586064B2 (en) | 1993-12-09 |
Family
ID=14737094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11845687A Granted JPS63283041A (en) | 1987-05-14 | 1987-05-14 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63283041A (en) |
-
1987
- 1987-05-14 JP JP11845687A patent/JPS63283041A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0586064B2 (en) | 1993-12-09 |
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