JPS5984552A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce floating capacitance between mutually adjacent metallic wirings largely by forming an insulating film as a spacer to the lower section of one part of the metallic wirings and preventing positionings on the same plane of the adjacent metallic wirings. CONSTITUTION:The silicon oxide films 203, 204 are formed selectively on a thick field silicon oxide film 202 fomed on a silicon substrate 201 in approximately the thickness of Al wiring films through a vapor growth method, the Al wirings 205-207 are each formed on the vapor growth silicon oxide film 203, the field silicon oxide film 202 and the vapor growth silicon oxide film 204, and an insulating film 208 as a surface protective film is formed from the wirings. Consequently, the adjacent Al wirings 205, 206 and 206, 207 are each positioned on different planes, and capacitance among the adjacent Al wirings are made largely smaller than the Al wirings are formed on the same plane. Accordingly, the degree of integration is improved, and the working speed of the integrated circuit device can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and particularly to the structure of metal wiring that electrically connects elements.

In recent years, the elements incorporated in integrated circuit devices have been increasingly miniaturized, and the operating speed of the elements has also increased significantly.

On the other hand, as high density and large scale integration are becoming more prominent,
Metal wiring connecting elements is becoming extremely long.

For this reason, even if the operating speed of the multi-element itself becomes faster, the time constant due to the resistance value of the metal wiring and the stray capacitance of the metal wiring becomes faster, the time required for a signal to propagate through the metal wiring and exit the integrated circuit device is However, there was a problem in that the speed was limited by the time constant of the wiring. In order to reduce this time constant, one way is to reduce the resistance value of the metal wiring.
Therefore, it is necessary to reduce stray capacitance.

Stray capacitance includes the capacitance between metal wiring and the substrate, and the capacitance between metal wiring, but as integrated circuits become denser and the wiring spacing becomes narrower, the capacitance between wiring increases rapidly, and the signal transmission time increases. A big problem has arisen in that the process is delayed at the edge of the board due to the capacitance between the wiring lines.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an integrated circuit device in which the stray capacitance between metal wirings is reduced and the above-mentioned problems are eliminated.

The integrated circuit device of the present invention is characterized in that it has a structure in which adjacent metal wires are not located on the same plane. Since the wires are located on different planes, the side surfaces of adjacent wires do not directly oppose each other, which has the effect of greatly reducing stray capacitance between wires. For this reason, even if the wiring length increases as the density and integration of integrated circuit devices increases, the time it takes for a signal whose potential is 9 to 10 to propagate through the wiring is significantly shorter. This has the great advantage of making it possible to significantly increase the operating speed.

Next, the present invention will be explained using drawings in order to better understand the present invention.

FIG. 1 is a cross-sectional view for explaining the wiring portion of a conventional integrated circuit device. In a conventional integrated circuit device, a thick silicon oxide film 10 is formed on a silicon substrate 101.
The structure is such that aluminum (Al) wirings 103 and 104 run over the wirings 2, and an insulating film 105 as a surface protection film is formed over the wirings. This AJ wiring xoa
7to and a have a structure in which they run in parallel on the same plane, which is the surface of the thick silicon oxide film 102, and their side surfaces directly face each other. For this reason, as integrated circuit devices become denser and the Al wiring spacing becomes less than a few μm, 1 μ0
The capacitance between matching wires increases rapidly, and the stray capacitance of the wires increases. Therefore, for example, Al wiring 103.104
is initially at a low potential, and when the wiring 103 is subsequently set to a high potential and the signal is transmitted to the outside, time is required to charge up the stray capacitance. 1μ, which has the major drawback of being slow.

FIG. 2 is a sectional view of an integrated circuit device for explaining the present invention in detail. In the integrated circuit device of the present invention, a silicon oxide film 203 is selectively formed on a thick field silicon oxide film 202 formed on a silicon substrate 201.・2
04 was formed by a vapor phase growth method to approximately the thickness of the Al wiring film described later, and A! The interconnections 205, 206, 207 are separated by a vapor phase grown silicon oxide film 203. Field silicon oxide film 202, vapor grown silicon oxide film 20
4, and an insulating film 20 as a surface protection film is applied from above.
It has a structure that forms 8. In this integrated circuit device by Akira Kinen, the adjacent Al wiring 2o5. and 206.20.
6 and 207 are located on different planes, and are arranged so that their side surfaces do not face each other. Therefore, Al wiring 2
The capacitance between 05 and 206 and Aj2 wiring 206 and 207 is greatly reduced compared to the case where Al wiring is formed on the same plane. In particular, as element microfabrication technology progresses and the spacing between Al interconnects becomes about the same as their thickness, that is, 18 m or less, the capacitance between interconnects becomes extremely large when adjacent interconnects face each other. Therefore, the integrated circuit device of the present invention is very important for achieving high speed.

FIG. 3 is a sectional view for explaining an integrated circuit device according to a second embodiment of the present invention. In the second embodiment, -c is a field silicon oxide film 302 on a silicon substrate 301.
The upper vapor-grown oxide films 303 and 304 are Al wiring, 305
, 306C) It is formed so that one side of the side surface is raised and is covered with a surface protection film 307.

Also in this second embodiment of the present invention, A/distribution #30
The side surfaces of 5 and 306 do not face each other, and the inter-wiring capacitance is greatly reduced as in the first embodiment.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining a conventional integrated circuit device, and FIGS. 2 and 3 are an integrated circuit device set 1 of the present invention. FIG. 3 is a cross-sectional view for explaining a second embodiment. In the plan view, 101.201.3o1...Silicon substrate b 102,202,302...
Field silicon oxide film, 103, 104, 205° 206.207, 305, 306...M wiring,
203.204.303.304...Vapor-phase grown silicon oxide film, 105,2.08,307...Insulating film for surface protection. yty, s n relaxation /ρ4'-47Figure 2〃5 2ρ6 aka a72? figure

Claims (1)

[Claims] An insulating film serving as a spacer is formed under at least a portion of the metal wirings that are formed adjacent to each other in parallel, and the side surfaces of the metal wirings that run adjacent to each other are formed so that they do not face each other. Features of integrated circuit devices.