JPH0693455B2 - Semiconductor integrated circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit having multi-layered metal wiring.

[Technical background of the invention and its problems]

The degree of integration of semiconductor integrated circuits is increasing year by year. Especially MO
In the field of S dynamic RAM (dRAM), high integration of 4 times was achieved in 3 years, and now mass production is progressing from 64KdRAM to 256KdRAM. When considering further increasing the capacity in the future,
It is considered that a technique for forming metal wiring in multiple layers is essential. For example, in order to reduce the delay of the word line signal due to the lengthening of the word line, one layer of metal wiring is added to short-circuit the word lines in some places to reduce the word line resistance as a whole, or the signal wiring is reduced. This is because it is indispensable to increase the degree of freedom of wiring by adding a low resistance metal wiring that intersects with. To do this, one layer
It is necessary to make the Al wiring into two or more layers. The most proven metal wiring material to date is Al, and using it for multilayer wiring is the safest method in terms of reliability.

However, it is known that when the Al wiring is multi-layered, a protrusion called a hillock is generated on the surface of the lower Al wiring, and due to this, the breakdown voltage between the upper and lower Al wirings is deteriorated. In gate arrays and the like, it has been practiced to use multilayer Al wiring by devising a technique such as making the interlayer insulating film sufficiently thick, but in the field of dRAM where leakage is a problem, use multilayer Al wiring. Things have been difficult until now. To avoid such hillock problems, lower Al
A method of coating the surface of the wiring with a refractory metal film such as Ti is known, but this has a drawback that the process becomes complicated.

[Object of the Invention]

The present invention has been made in view of the above points, and effectively prevents the occurrence of hillocks in a simple process,
An object of the present invention is to provide a semiconductor integrated circuit that realizes a highly reliable multilayer metal wiring structure that can reduce the influence of surface effects when a high-frequency current flows.

[Outline of Invention]

The multi-layer metal wiring in the present invention is provided with a slit in a direction in which a current flows in the lower metal wiring in a region where the upper metal wiring and the lower metal wiring intersect with each other and the lower metal wiring in the portion where the slit is provided. , A set of a plurality of fine lines having a width of 2 μm or less.

〔The invention's effect〕

The present invention positively proposes the novel fact found by the present inventor that hillocks with a high height (hereinafter simply referred to as hillocks), which cause a problem when the Al wiring is as thin as 1 to 2 μm or less, hardly occur. I'm using it. That is, according to the present invention, by forming the lower metal wiring in a region where it intersects with the upper metal wiring, so to speak, it is possible to effectively prevent hillock generation on the surface of the lower metal wiring in this region. Therefore, according to the present invention, it is possible to realize an integrated circuit having a highly reliable multi-layer metal wiring structure without deterioration of breakdown voltage or leakage between wiring layers due to hillocks. Especially when applied to dRAM, it is highly effective in preventing malfunction and improving yield.

Moreover, in the present invention, the slit can be formed in the lower metal wiring at the same time as the wiring patterning step, so that the manufacturing process is not complicated at all. Further, by forming the slit only in the intersecting region with the upper metal wiring and in the direction in which the current flows, the increase in wiring resistance can be made sufficiently small.

Further, according to the present invention, since the slits are present not only in the intersections of the wirings but also in other regions, it is possible to reduce the influence of the skin effect when a high frequency current flows.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows a plan view of an intersection of two-layer Al wiring in an integrated circuit of one embodiment, and FIG. 2 shows a sectional view taken along the line AA '. Reference numeral 1 is a semiconductor substrate such as Si, on which elements constituting a dRAM circuit are formed, for example. A first layer Al wiring 2 and a second layer Al wiring 3 are formed on the substrate 1 separated by an interlayer insulating film 5. The first layer Al wiring 2 is provided with a plurality of slits 4 as shown in the crossing portion with the second layer Al wiring 3 and other portions, and this portion has a width of 1 to 2 μm or less. It is a set of multiple thin lines. This slit 4 is simultaneously formed in the patterning process of the first layer Al wiring 2.

With such a configuration, the slit 4 of the first-layer Al wiring 2
The hillocks are prevented from being generated in the heating process in the portion where the is provided. This is because the stress distribution of the Al polycrystal in the thermal process is effectively performed. Therefore, the first layer Al wiring 2 and the second layer
The withstand voltage between the Al wirings 3 is sufficiently high, and reliability is improved.

Further, it is not necessary to add a special process to form the slit 4 in the first layer Al wiring 2, and for example, to prevent hillocks.
The process is simpler than the conventional method of coating the Ti film. Moreover, since the slit 4 is formed along the direction in which the current of the wiring flows, the provision of the slit 4 has almost no effect on the increase of the wiring resistance.

Further, according to the present embodiment, since the slits 4 are present at the portions other than the intersection of the first-layer Al wiring and the second-layer Al wiring, it is possible to reduce the influence of the skin effect when a high frequency current flows. . The effect is that the wiring width is the skin effect thickness, that is, If ρ is larger than the specific resistance [Ω · cm] and f is the frequency [MHz], it will be recognized for the first time by setting it as a set of thin lines. Therefore, as in the present embodiment, if the thinning is extended not only to the intersection of the first layer wiring and the second layer wiring but also to other regions, the resistance increase due to the skin effect can be prevented more effectively, and the integration It enables high-speed signal propagation in the circuit.

The present invention is not limited to the above embodiments, and various modifications can be carried out without departing from the spirit of the present invention. For example, even in the case of a multilayer wiring structure having three or more layers, similar effects can be obtained by providing slits in the lower wiring between adjacent wiring layers as in the above-described embodiment. Further, the metal wiring material is not limited to Al, and the present invention can be effectively applied as long as hillocks are generated in the heating process.

[Brief description of drawings]

FIG. 1 is a plan view showing a wiring structure in an integrated circuit of an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA 'in FIG. 1 ... Semiconductor substrate, 2 ... First layer Al wiring, 3 ... Second layer
Al wiring, 4 ... Slit, 5 ... Interlayer insulating film.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having multi-layered metal wiring, a slit is provided in a lower metal wiring in a direction in which a current flows in a region where an upper metal wiring and a lower metal wiring intersect with each other, and this slit is provided. A semiconductor integrated circuit, characterized in that the lower metal wiring of the open portion is a set of a plurality of fine lines having a width of 2 μm or less.