JPS63138780A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To enable a pattern of insulating film with excellent insulating characteristics to be formed doing no damage to a crystalline substrate by a method wherein an insulating film directly covering a substrate is formed using ECR plasma CVD process. CONSTITUTION:First insulating films 46A, 46B formed on the surface of substrate 40 whereon a resist pattern 44 is formed by ECR plasma CVD process to form the second insulating film 48 on the first insulating films 46A, 46B. Next, the second insulating film 48 on the substrate and the flat surface of resist pattern is removed to leave the second insulating film 60 only on the sidewall or resist pattern 44. In such a state, ion is implanted to form a source region 52 and a drain region 54. Furthermore, the resist pattern 44 and the first insulating film 46A thereon are removed to form the first insulating film 46B with an opening 56 by ECR plasma CVD process further forming a gate electrode 58 on the substrate 40 in the opening 56. Through these procedures, an insulating pattern can be formed doing no damage to the substrate 40 as the primary layer of an insulating film to be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a gate electrode of a field effect transistor, and more particularly, to a method for manufacturing an insulating film pattern for forming a gate electrode used in a manufacturing process of a field effect transistor. Regarding the forming method.

BACKGROUND OF THE INVENTION FIG. 2 is a process diagram illustrating part of a typical manufacturing process for a conventional Schottky gate field effect transistor.

As shown in FIG. 2(a), 81 is placed on the semiconductor substrate 10.
A protective insulating film 12 such as 3N is formed, and a three-layer resist consisting of a resist 14, an insulating film 16 such as 8102, and a resist 18 is further formed. Next, the uppermost resist 18 is patterned, and the insulating film 16 is etched using the resist pattern 18A as a mask to form an insulating film pattern 16A, as shown in FIG. 2(b). After that, resist 18 is applied by 0□ashing etc.
At the same time as removing the resist pattern 14, the resist pattern 14 is etched using the insulating film pattern 16A as a mask.
Form A. Then, using the insulating film pattern 16A and the resist pattern 14A as masks, ions are implanted as shown by arrows 20 in FIG. 2(C) to form a source region 2OA and a drain region 20B.

Thereafter, as shown in FIG. 2(d), a 5in2 film 24 is formed on the entire surface by sputtering or the like, and then the resist pattern 14A is removed by etching and lift-off is performed, as shown in FIG. 2(e). , an inverted pattern 24A of 5in2 film is formed.

Further, as shown in FIG. 2(f), after forming ohmic electrodes 26A and 26B on the source region 2OA and drain region 20B, a three-layer resist 28 is again formed on the entire surface.

Next, the uppermost resist layer of the three-layer resist 28 is patterned to have an opening corresponding to the gate electrode.
Using the resulting uppermost layer resist pattern as a mask, the intermediate layer insulating film of the three-layer resist 28 is etched, and the lowermost resist layer of the three-layer resist 28 is selectively removed using the insulating film pattern as a mask. Then, the second
As shown in Figure (g), a pattern of three-layer resist 28 is formed.

Then, using the pattern of the three-layer resist 28 as a mask, the insulating film 12 is etched, for example, by reactive ion etching.
By removing a portion of the insulating film 12, as shown in FIG. 2, an insulating film 12 having an opening 30 is obtained. Furthermore, three-layer resist 2
Using the pattern 8 as a mask, a gate electrode material is deposited, and then the pattern of the three-layer resist 28 is removed or removed to form the gate electrode 3 as shown in FIG. 2(1).
It formed 2.

Problems to be Solved by the Invention However, in the conventional method, the insulating film 12 provided in direct contact with the semiconductor substrate 10 is removed using a reactive ion etching method. Therefore, the substrate directly below the ion-etched insulating film 12, that is, the substrate inside the opening 30, is damaged. Further, there is a problem in that foreign matter adheres during the etching and subsequent cleaning steps. The substrate portion within the opening 30 will become a channel region when the gate N'4 is formed therein, and damage will cause deterioration of the characteristics of the field effect transistor. Further, when a Schottky electrode is provided on a portion of the substrate that is damaged or has foreign matter attached to it, the electrical characteristics of the Schottky gate are deteriorated.

Furthermore, although the conventional manufacturing process described above can provide a field effect transistor in which the gate electrode is self-aligned with the source and drain regions, the number of manufacturing steps is too large.

Further, the channel region directly under the gate electrode is in direct contact with the highly doped source region and drain region, respectively. Therefore, as the gate length is shortened, a short channel effect occurs. Even if the dummy gate is made into a T-shape and offset, the short channel effect similarly occurs.

SUMMARY OF THE INVENTION Accordingly, a first object of the present invention is to form a pattern of an insulating film having good insulating properties without damaging the crystal substrate that is the base of the insulating film to be removed in a method of manufacturing a field effect transistor. It provides:

A second object of the present invention is to provide a method for manufacturing a field effect transistor that can manufacture a field effect transistor having a structure in which short channel effects can be suppressed even when the gate length is short.

Means for Solving the Problems As a result of intensive study and research in order to solve the above-mentioned conventional problems, the present inventors have developed the electron cyclotron (ECR) resonance plasma CVD method (hereinafter referred to as the "ECR resonance plasma CVD method"). The inventors have discovered a method by which an insulating film pattern can be formed without damaging the substrate underlying the insulating film to be removed.

That is, according to the present invention, a resist pattern corresponding to the gate region is formed on a semiconductor substrate, and a first resist pattern is formed on the substrate by electron cyclotron resonance plasma CVD.
forming an insulating film, forming a second insulating film on the first insulating film, and removing the second insulating film so as to leave the second insulating film on the sidewall of the resist pattern; A source region and a drain region are formed by ion implantation into the substrate, and the resist pattern and the first insulating film thereon are removed by lift-off to form a pattern of the first insulating film having an opening. There is also provided a method for manufacturing a field effect transistor, characterized in that a self-aligned gate electrode is formed in the opening.

Function: In the method for manufacturing a field effect transistor according to the present invention described above, the first insulating film is formed by the electron cyclotron resonance plasma CVD method, and the second insulating film is further formed thereon. An insulating film formed by an electron cyclotron resonance plasma CVD method and an insulating film formed by a conventional method such as a sputtering method are different in manufacturing conditions and etching characteristics.

Since the ECR plasma CVD method allows film formation at low temperatures, it does not alter the quality of the resist or the like. When an insulating film is formed using a conventional method such as sputtering, the resist underneath changes in quality and becomes difficult to dissolve with a solvent. In addition, when the ECR plasma CVD method is used, since the directivity of the plasma toward the substrate is excellent, a film is not formed in areas other than the direction from the plasma to the substrate, that is, on the side surfaces of the substrate and pattern. Therefore, lift-off can be performed extremely easily compared to other film forming methods such as CVD.

Furthermore, by changing the etching conditions, it is possible to completely remove only the insulating film formed by the electron cyclotron resonance plasma CVD method, or completely remove only the insulating film formed by conventional methods such as sputtering. . In this respect as well, the above-described first insulating film and second insulating film
One of the insulating films can be selectively removed.

In addition, the resulting film has good film quality, is highly resistant to etching, does not peel off even after annealing at approximately 800°C, and has excellent properties that can suppress the diffusion of constituent elements such as Ga and 8S in compound semiconductors. ing.

Therefore, by forming a first insulating film by the electron cyclotron resonance plasma CVD method and forming a second insulating film on the first insulating film, by selecting an etching method, the resist pattern can be etched. The second insulating film can be removed so as to leave the second insulating film on the sidewall.

In this state, by implanting ions into the semiconductor substrate, a source region and a drain region can be formed.

Further, by removing the resist pattern and the first insulating film thereon by lift-off, it is possible to form a pattern of the first insulating film having openings corresponding to the resist pattern described above. Then, if a gate electrode is formed in the opening, the gate electrode is aligned with the source region and the drain region. That is,
A self-aligned gate electrode can be formed.

In addition, by forming the source and drain regions by ion implantation while the second insulating film remains on the sidewalls of the resist pattern, LDD (lightly doped
d drain) structure can be formed.

In the method for manufacturing a field effect transistor according to the present invention described above, since the insulating film that directly covers the substrate is formed using the ECR plasma CVD method, patterning of the insulating film can be easily performed by lift-off. There is no need to use reactive ion etching for removal.

Therefore, the substrate, which is the base for providing the gate electrode, etc., is not damaged, so the contact resistance between the electrode and the substrate is reduced, and there is no possibility of foreign matter adhering during etching.

In the embodiment of the present invention, the second insulating film is formed by bias sputtering, and the second insulating film is removed by reactive ion etching. Even if reactive ion etching is used to remove the second insulating film in this way, the substrate itself is covered with the first insulating film, so it will not be damaged.

Furthermore, in one embodiment, after forming a pattern of the first insulating film having the opening, the substrate is annealed to activate the ion-implanted layer, and the ion-implanted layer is activated on the substrate within the opening. A heat-resistant Schottky gate electrode is then formed. However, when forming a non-heat resistant Schottky gate electrode, the gate electrode is formed after forming the source electrode and the drain electrode and further annealing.

Further, in a preferred embodiment of the present invention, the first insulating film is a silicon nitride film, and the second insulating film is one of a silicon nitride film, a silicon oxide film, and a silicon nitride oxide film. The semiconductor substrate may be a ■-■ group compound semiconductor such as GaAs, or a single semiconductor such as Sl.

Further, the method for manufacturing a field effect transistor according to the present invention described above can be satisfactorily used even when the gate length is on the order of submicrons, and is particularly suitable for manufacturing a high performance field effect transistor with a short gate length. However,
In the case of submicron dimensions, if a PM embedded structure is used in combination, it is effective in preventing the short channel effect.

EXAMPLES Hereinafter, a method for manufacturing a field effect transistor according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 illustrates a part of the process of the method for manufacturing a field effect transistor according to the present invention, and the present invention is not particularly limited thereto.

FIG. 1(a) shows that a lightly doped shallow active layer 42 is formed on a part of the surface area of a substrate 400, and a resist pattern 4 corresponding to a future gate electrode is formed on the active layer 42.
4 is shown.

ECR plasma CVD is applied to the surface of the substrate 40 in such a state.
As shown in FIG. 1(b), the first insulating film 46 is
A and 46B are formed. This first insulating film is ECR
Due to the directional characteristics of the plasma CVD method, it is hardly formed on the sides of the resist pattern. Therefore, it is divided into an insulating film 46A on the resist pattern 44 and an insulating film 46B on the substrate 40.

Thereon, a second insulating film 48 is formed by sputtering or the like as shown in FIG. 1(C).

Next, the second insulating film 48 on the flat surfaces of the substrate and resist pattern is removed using a directional etching method such as RIE etching, as shown in FIG.
As shown in d), the second insulating film 50 is left only on the sidewalls of the resist pattern 44.

In this state, ions are implanted to form a source region 52 and a drain region 54 as shown in FIG. 1(e).

Thereafter, the second insulating film 50 on the side wall of the resist pattern 44 is removed by slide etching as shown in FIG. 1(f).

Furthermore, the resist pattern 44 and the first insulating film 46A thereon are removed by lift-off to form an ECR plasma CVD first insulating film 46B having an opening 56 as shown in FIG. 1(g). .

Then, as shown in FIG. 1, a gate electrode 58 is formed on the substrate 40 within the opening 56.

The ECR plasma CVD method used in the method for manufacturing a field effect transistor according to the present invention described above is described in the Japanese Journal of Applied Physics.
Plied Physics Letters),
vol, 22. Na3゜ppL210-L212.
1983, “ECR plasma CVD equipment that can grow thin films at room temperature and causes little damage to substrates” Nikkei Micro Devices,
It is disclosed in Spring 1985 issue 1ρp93-100.

An ECR plasma CVD apparatus has a plasma chamber and a reaction chamber. The plasma chamber is connected to the microwave waveguide via a microwave-transparent partition plate, and an electromagnet is installed around it to establish ECR (electron cycloton resonance) conditions with the microwave inside the plasma chamber. , which can form a diverging magnetic field for drawing out plasma within the reaction chamber. This plasma chamber is connected to the reaction chamber via a plasma extraction window, and plasma is accelerated and guided by a divergent magnetic field toward a sample placed on a sample stage inside the reaction chamber.

According to this device, N2, NH3,0□,
Ar or a mixed gas thereof is sent, and the gas turned into plasma is guided by a divergent magnetic field and sent to the reaction chamber. On the other hand, there is a substrate placed on a sample stage in the reaction chamber, and raw material gases for forming an insulating film such as 5iH4, S12 Hg, and Sia Ha are supplied to the reaction chamber, and are excited and activated by the plasma. A reaction occurs and a predetermined reaction product is deposited on the substrate.

As the insulating film formed by ECR plasma CVD method, Si3N film is currently formed, but SIO
2. A silicon nitride oxide film can also be formed.

Next, specific examples of the method for manufacturing a field effect transistor of the present invention will be described in detail, but the present invention is not limited thereto.

Example 1 According to the process of the present invention as shown in FIG. 1, an insulating film pattern and a gate electrode for a field effect transistor were formed on a substrate as follows.

First, a GaAs substrate 40 was used as a semiconductor substrate, and a photoresist film (AZ-1400) was coated on the entire surface thereof, exposed to light in a predetermined pattern, and then developed to form a resist pattern. Next, using the resist formed on the substrate as a mask, 21131+ was lightly doped at an accelerating voltage of 30 to 70 KV to form an N-type active layer 42. Then,
The resist pattern was removed, and a photoresist film (AZ-1400) was again applied to the entire surface of the substrate 40.
Another predetermined pattern was exposed and developed to form a resist pattern 44 as shown in FIG. 1(a).

Next, as shown in Fig. 1 et al.), SiH<, NH3 and N
3 by ECR plasma CVD method using a mixed gas of 2.
i3N, the film 46 was formed to a thickness of 1000 to 2000 nm.

Furthermore, as shown in FIG. 1(C), the 5102 film 48 is formed by bias sputtering with good coverage on the side surfaces.
was formed to a thickness of 1,000 to 2,000 people.

Next, the flat portion of Sl is etched by RIE etching.

The N.sub.2 film 48 was removed, leaving the S.sub.r 02 film 50 only on the sidewalls of the resist pattern 44, as shown in FIG. 1(d).

In this state, 283i* is set to an accelerating voltage of 150 to 200
N-type source region 52 and drain region 54 are implanted at KV with an implantation concentration of about 3X1013/c++f.
was formed as shown in FIG. 1(e).

Thereafter, the 5iO9 film 50 on the side wall of the resist pattern 44 is removed by slide etching with buffered hydrofluoric acid diluted with NH and F, as shown in FIG. , the first Si3N film 46A on the resist pattern 44
The ECR plasma CVD Sl layer has an opening 56 as shown in FIG. 1 ((a)).

An N4 film 46B was formed.

Next, such a substrate was annealed in an AsH atmosphere at a temperature of about 800° C. for 30 minutes.

The reason why this annealing is performed in an As H3 atmosphere is to prevent As from dissipating from the GaAs substrate. Therefore, when providing an annealing protective film over the entire surface of the substrate, annealing can also be performed in an inert atmosphere such as N2.

Then, a resist pattern having an opening that matches the opening 56 and is larger than the opening 56 is formed on the substrate, a Ti/Pt/Au based electrode material is deposited on the entire surface, and then the resist pattern is removed. Then, a gate electrode was formed as shown in the first opening by a lift-off method.

Thereafter, source and drain electrodes were provided in the source and drain regions using a conventionally known method, and the mutual conductance (g,) was measured to be 230 m5/m.
It was m.

As is clear from the description, the above embodiment is a method of manufacturing a Schottky gate field effect transistor. However, an MO3 field effect transistor can also be manufactured by adding a step of forming a thin insulating film on the substrate.

Effects of the Invention According to the method for manufacturing a field effect transistor according to the present invention described above, the substrate surface on which the gate electrode is formed is not damaged, and the gate electrode is self-aligned with the source region and the drain region. Therefore, a field effect transistor having good electrical characteristics can be manufactured.

Further, according to the method for manufacturing a field effect transistor according to the present invention, a field effect transistor in which the gate electrode is self-aligned with the source region and the drain region can be manufactured with fewer manufacturing steps than in the past.

According to the method for manufacturing a field effect transistor of the present invention described above, an LDD structure in which the gate electrode is self-aligned can be realized. If such an LDD structure is adopted, even if the gate length is shortened, the speed can be increased without causing a short channel effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the steps of a method for manufacturing a field effect transistor according to the present invention. FIG. 2 is a diagram showing the steps of a conventional method for manufacturing a field effect transistor. (Main reference numbers) 10...Semiconductor substrate, 12...Protective insulating film, 14.1
8...Resist, 16...Insulating film, 2OA, 20B...
Ion implantation region, 24A... Inverted pattern insulating film, 26A, 26B... Ohmic electrode, 28... Three-layer resist, 30... Opening, 32... Gate electrode 32. 40...Semiconductor substrate, 42...Active layer, 44...Resist pattern, 46...First insulating film formed by ECR plasma CVD method, 48...Second insulating film, 50...Side wall of resist pattern The second insulating film remaining on the

Claims (8)

[Claims] (1) Form a resist pattern corresponding to a gate region on a semiconductor substrate, form a first insulating film on the substrate by electron cyclotron resonance plasma CVD, and
A second insulating film is formed on the insulating film, the second insulating film is removed so as to leave the second insulating film on the sidewalls of the resist pattern, and ions are implanted into the substrate to form a source. forming a region and a drain region, removing the resist pattern and the first insulating film thereon by lift-off to form a pattern of the first insulating film having an opening, and forming a self-aligned gate in the opening. A method for manufacturing a field effect transistor, the method comprising forming an electrode. (2) The method for manufacturing a field effect transistor according to claim (1), wherein the second insulating film is formed by bias sputtering. (3) The second insulating film is removed by reactive ion etching.
) or (2). (4) After forming a pattern of the first insulating film having the opening, the substrate is annealed to activate the ion implantation layer, and a heat-resistant Schottky gate is formed on the substrate within the opening. The method for manufacturing a field effect transistor according to any one of claims (1) to (3), characterized in that an electrode is formed. (5) The method for manufacturing a field effect transistor according to any one of claims (1) to (4), wherein the first insulating film is a silicon nitride film. . (6) The second insulating film is any one of a silicon nitride film, a silicon oxide film, and a silicon nitride oxide film. A method for manufacturing a field effect transistor according to any one of the items. (7) Claims (1) to (6) characterized in that the semiconductor substrate is a III-V compound semiconductor.
) The method for manufacturing a field effect transistor according to any one of items up to item 1. (8) The method for manufacturing a field effect transistor according to claim (7), wherein the III-V compound semiconductor is GaAs.