JPH0793324B2 - Method for manufacturing field effect transistor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a gate electrode of a field effect transistor, and more specifically, to a gate electrode forming insulating film pattern used in a manufacturing process of a field effect transistor. It relates to a forming method.

2. Description of the Related Art FIG. 2 is a process diagram illustrating a part of a typical manufacturing process of a conventional Schottky gate field effect transistor.

As shown in FIG. 2 (a), Si ₃ N _{4 is formed} on the semiconductor substrate 10.
A protective insulating film 12 such as
A three-layer resist consisting of an insulating film 16 such as O ₂ and a resist 18 is formed. Next, the uppermost resist 18 is patterned, and the insulating film 16 is etched using the resist pattern 18A as a mask as shown in FIG. 2 (b).
The insulating film pattern 16A is formed. After that, the resist 18 is removed by O ₂ ashing or the like and the insulating film pattern
The resist 14 is etched using 16A as a mask to form a resist pattern 14A. And the insulating film pattern 1
Using 6A and the resist pattern 14A as a mask, ion implantation shown by an arrow 20 in FIG.
And a drain region 20B is formed.

After that, as shown in FIG. 2 (d), a SiO ₂ film 24 is formed on the entire surface by a sputtering method or the like, and then the resist pattern 14A is removed by etching to perform lift-off, as shown in FIG. 2 (e). In addition, the reverse pattern of the SiO ₂ film
Form 24A.

Further, as shown in FIG. 2F, after forming ohmic electrodes 26A and 26B on the source region 20A and the drain region 20B, a three-layer resist 28 is formed on the entire surface again.

Then, the uppermost resist of the three-layer resist 28 is patterned so that the gate has an opening corresponding to an electrode,
The resulting uppermost resist pattern is used as a mask to etch the intermediate insulating film of the three-layer resist 28, and the insulating film pattern is used as a mask to selectively remove the lowermost resist of the three-layer resist 28. Then, as shown in FIG. 2G, a pattern of the three-layer resist 28 is formed.

Then, using the pattern of the three-layer resist 28 as a mask, a part of the insulating film 12 is removed by, for example, reactive ion etching, and an opening 30 is formed as shown in FIG. 2 (h).
An insulating film 12 having is obtained. Further, the gate electrode material is deposited using the pattern of the three-layer resist 28 as a mask, and then the gate electrode 32 as shown in FIG. 2 (i) is formed by lift-off for removing the pattern of the three-layer resist 28. It was

Problems to be Solved by the Invention However, in the above-mentioned conventional method, the semiconductor substrate
Since the insulating film 12 provided in direct contact with 10 is removed by using the reactive ion etching method, the substrate immediately below the ion-etched insulating film 12, that is, in the opening 30 due to ion bombardment. Damage the board. In addition, there is a problem that foreign matter adheres in the etching process and the subsequent cleaning process. The substrate portion in the opening 30 is a portion that becomes a channel region when the gate electrode is formed therein, and the damage causes deterioration of the characteristics of the field effect transistor. Further, when the Schottky electrode is provided on the substrate portion where such damage or foreign matter is attached, the electrical characteristics of the Schottky gate are deteriorated.

Furthermore, although the field effect transistor in which the gate electrode is self-aligned with the source region and the drain region can be obtained by the conventional manufacturing process described above, the number of manufacturing steps is too large.

Further, the channel region directly below the gate electrode is in direct contact with the high-concentration source region and the high-concentration drain region. Therefore, when the gate length is shortened, a short channel effect occurs. Even if the dummy gate is formed in a T shape and offset is used, the short channel effect similarly occurs.

Therefore, a first object of the present invention is a method for forming a pattern of an insulating film having good insulating characteristics without damaging a crystal substrate which is a base of the insulating film to be removed in a method for manufacturing a field effect transistor. Is provided.

A second object of the present invention is to provide a method of manufacturing a field effect transistor capable of manufacturing a field effect transistor having a structure capable of suppressing the short channel effect even if the gate length is short.

Means for Solving the Problems As a result of intensive studies and researches for solving the above-mentioned conventional problems, the present inventors have found that an electron cyclotron (ECR) resonance plasma CVD method (hereinafter, referred to as ECR resonance plasma CVD method) is used. We have found a method by which an insulating film pattern can be formed without damaging the substrate that is the base of the insulating film to be removed.

That is, according to the present invention, the step of forming a resist pattern corresponding to the gate region on the semiconductor substrate, and the first insulation by electron cyclotron resonance plasma CVD method only on the surface of the substrate and the top surface of the resist pattern. Forming a film, forming a second insulating film on the side wall of the resist pattern and on the first insulating film, and leaving the second insulating film on the side wall of the resist pattern. A step of removing the second insulating film, a step of implanting ions into the substrate to form a source region and a drain region, and removing the resist pattern and the first insulating film on the resist pattern by lift-off to form an opening. A step of forming a pattern of the first insulating film having a portion and a step of forming a self-aligned gate electrode in the opening. That the method of manufacturing the field effect transistor is provided.

Action In the above-described method for manufacturing a field effect transistor according to the present invention, the first insulating film is formed by the electron cyclotron resonance plasma CVD method, and the second insulating film is further formed thereon. Electron cyclotron resonance plasma CV
The insulating film formed by the D method and the insulating film formed by the conventional method such as the sputtering method have different manufacturing conditions and etching characteristics.

Since the film can be formed at a low temperature by using the ECR plasma CVD method,
Does not deteriorate the resist. When the insulating film is formed by a conventional method such as a sputtering method, the resist thereunder is deteriorated and becomes difficult to dissolve in a solvent. In addition, ECR plasma CVD
When the method is used, since the directivity of the plasma to the substrate is excellent, the film is not formed on a portion other than the direction from the plasma to the substrate, that is, the side surface of the substrate or the pattern. Therefore, lift-off can be performed extremely easily as compared with other film forming methods such as CVD.

Further, by changing the etching conditions, it is possible to completely remove only the insulating film formed by the electron cyclotron resonance plasma CVD method or only the insulating film formed by the conventional method such as the sputtering method. Also in this respect, one of the first insulating film and the second insulating film can be selectively removed.

Also, the quality of the formed film is good, it is rich in etching resistance, does not peel off even when annealed at about 800 ° C., and has excellent characteristics that can suppress diffusion of constituent elements such as Ga and As in the compound semiconductor. There is.

Therefore, the first insulating film is formed by the electron cyclotron resonance plasma CVD method, the second insulating film is formed on the first insulating film, and then the etching method is selected, whereby the resist pattern is formed. The second insulating film can be removed so that the second insulating film remains on the sidewall.

In such a state, the source region and the drain region can be formed by implanting ions into the reaction substrate.

Further, by removing the resist pattern and the first insulating film on the resist pattern by lift-off, it is possible to form the pattern of the first insulating film having an opening corresponding to the resist pattern. When the gate electrode is formed in the opening, the gate electrode is aligned with the source region and the drain region. That is,
A self-aligned gate electrode can be formed.

Further, an LDD (lightly doped drain) structure can be formed by forming a source region and a drain region by ion implantation with the second insulating film remaining on the sidewall of the resist pattern.

In the method for manufacturing a field effect transistor according to the present invention described above, since the insulating film that directly covers the substrate is formed by using the ECR plasma CVD method, the patterning of the insulating film can be easily performed by lift-off, and the insulating film There is no need to use reactive ion etching for removal. Therefore, the substrate, which is the base for providing the gate electrode and the like, is not damaged, so that the contact resistance between the electrode and the substrate is reduced, and foreign substances are not attached during etching.

In the embodiment of the present invention, the second insulating film is formed by bias sputtering, and the second insulating film is removed by reactive ion etching. Thus, even if the reactive ion etching is used for removing the second insulating film, the substrate itself is covered with the first insulating film, and therefore is not damaged.

Further, in one embodiment, after the pattern of the first insulating film having the opening is formed, the substrate is annealed to activate the ion implantation layer, and the ion implantation layer is activated on the substrate in the opening. A heat resistant Schottky gate electrode is formed on. However, when forming a non-heat-resistant Schottky gate electrode, the gate electrode is formed after forming the source electrode and the drain electrode and further annealing.

Further, in a preferred embodiment of the present invention, the first insulating film is a silicon nitride film, and the second insulating film is a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. The semiconductor substrate is made of GaAs
It may be a III-V group compound semiconductor or a simple semiconductor such as Si.

Further, the above-described method of manufacturing a field effect transistor according to the present invention can be sufficiently used even when the gate length is on the order of submicrons, and is particularly suitable for manufacturing a high performance field effect transistor having a short gate length. However,
In the case of submicron, if the P layer embedded structure is used together, it is effective in preventing the short channel effect.

EXAMPLES Hereinafter, a method for manufacturing a field effect transistor according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 illustrates a part of the steps of the method for manufacturing a field effect transistor according to the present invention, and the present invention is not limited to this.

In FIG. 1A, a weakly doped shallow operating layer 42 is formed on a part of the surface region of a substrate 40, and a resist pattern 44 corresponding to a future gate electrode is formed on the operating layer 42. It shows the state.

As shown in FIG. 1B, the first insulating films 46A and 46B are formed on the surface of the substrate 40 in this state by the ECR plasma CVD method.
To form. The first insulating film is hardly formed on the side surface of the resist pattern due to the directivity characteristic of the ECR plasma CVD method. Therefore, it is divided into an insulating film 46A on the resist pattern 44 and an insulating film 46B on the substrate 40.

A second insulating film 48 is formed thereon by sputtering or the like as shown in FIG. 1 (c).

Then, the second insulating film 48 on the flat surface of the substrate and the resist pattern is removed by an etching method such as RIE etching which has a directionality of etching, and FIG.
The second insulating film 50 is left only on the side wall of the resist pattern 44 as shown in FIG.

In this state, ion implantation is performed as shown in FIG. 1E to form the source region 52 and the drain region 54.

After that, by light etching, resist pattern
The second insulating film 50 on the sidewall of 44 is removed as shown in FIG.

Further, the resist pattern 44 and the first insulating film 46A on the resist pattern 44 are removed by lift-off, and the first insulating film for ECR plasma CVD having an opening 56 as shown in FIG.
Form 46B.

Then, as shown in FIG. 1H, a gate electrode 58 is formed on the substrate 40 in the opening 56.

The ECR plasma CVD method used in the method for manufacturing a field-effect transistor according to the present invention described above, Japanese Journal of Applied Physics Letters, v
No. 22, No. 4, ppL210-L212, 1983, and "ECR plasma CVD apparatus capable of growing thin films at room temperature with less substrate damage", Nikkei Microdevice, Spring 1985, pp93-100, etc.

The ECR plasma CVD apparatus has a plasma chamber and a reaction chamber. The plasma chamber is connected to the microwave waveguide through the partition plate with microwave permeability, while an electromagnet is provided around the plasma chamber, and EC
The R (electron cycloton resonance) condition is established so that a divergent magnetic field for drawing plasma in the reaction chamber can be formed. This plasma chamber is connected to the reaction chamber through a plasma extraction window, and plasma is accelerated and guided by a divergent magnetic field toward a sample placed on a sample table in the reaction chamber.

According to this apparatus, the plasma chamber ECR condition is set by the microwave and the magnetic _{field, N 2, NH 3, O} 2, Ar or and mixtures of these gases are sent, plasma gas is divergent magnetic field Is guided by and sent to the reaction chamber. On the other hand, there is a substrate placed on the sample table in the reaction chamber, and
A raw material gas for forming an insulating film such as H ₄ , Si ₂ H ₆ , and Si ₃ H ₈ is supplied to the reaction chamber, which is excited and activated by the plasma to cause a reaction, and a predetermined reaction product is deposited on the substrate. To do.

As an insulating film formed by the ECR plasma CVD method, Si ₃ N
_Four films are currently formed, but SiO ₂ , silicon oxynitride film, etc. can also be formed.

Next, specific examples of the method for manufacturing the field effect transistor of the present invention will be described in detail, but the present invention is not limited to these.

Example 1 According to the process of the present invention as shown in FIG. 1, a pattern of an insulating film for a field effect transistor and a gate electrode were formed on a substrate as follows.

First, a GaAs substrate 40 was used as a semiconductor substrate, a photoresist film (AZ-1400) was applied over the entire surface, a predetermined pattern was exposed, and then a phenomenon was formed to form a resist pattern. Next, using the resist formed on the substrate as a mask
²⁸ Si ⁺ was lightly doped at an accelerating voltage of 30 to 70 KV to form an N-type operating layer 42. Then, the resist pattern is removed, a photoresist film (AZ-1400) is applied again on the entire surface of the substrate 40, another predetermined pattern is exposed and developed, and as shown in FIG. 1 (a). A resist pattern 44 was formed.

Next, as shown in FIG. 1 (b), a Si ₃ N ₄ film 46 is formed by ECR plasma CVD using a mixed gas of SiH ₄ , NH ₃ and N _2.
Formed to a thickness of 0 to 2000Å.

Furthermore, as shown in FIG. 1 (c), the SiO ₂ film 48 is 1000
Formed to a thickness of ~ 2000Å.

Then, the Si ₃ N ₄ film 48 on the flat portion was removed by RIE etching, and the SiO ₂ film 50 was left only on the side wall of the resist pattern 44 as shown in FIG. 1D.

In such a state, ²⁸ Si ⁺ is ion-implanted at an accelerating voltage of 150 to 200 KV and an N-type source region having an implantation concentration of about 3 × 10 ¹³ / cm ³ is implanted.
52 and a drain region 54 were formed as shown in FIG.

After that, the SiO ₂ film 50 on the side wall of the resist pattern 44 is removed by light etching with buffered hydrofluoric acid diluted with NH ₄ F as shown in FIG. 1 (f), and the resist pattern is removed with acetone. The first Si ₃ N ₄ film 46A on the resist pattern 44 is removed by the ECR plasma CVD having the opening 56 as shown in FIG. 1 (g).
A Si ₃ N ₄ film 46B was formed.

Then, such a substrate is heated in an AsH ₃ atmosphere at a temperature of about
It was annealed at 800 ° C. for 30 minutes. This anneal is AsH
_The reason for performing in ₃ atmospheres is to prevent As from being dissipated from the GaAs substrate. Therefore, when the annealing protection film is provided on the entire surface of the substrate, the annealing can be performed in an inert atmosphere such as N ₂ .

Then, a resist pattern having an opening larger than the opening 56 and corresponding to the opening 56 is formed on the substrate, a Ti / Pt / Au-based electrode material is vapor-deposited on the entire surface, and then the resist pattern is removed. Then, a gate electrode was formed by the lift-off method as shown in FIG.

Then, the source and drain electrodes were provided in the source region and the drain region by a conventionally known method, and the mutual conductance (g _m ) was measured and found to be 230 mS / mm.

The embodiment described above is a method of manufacturing a Schottky gate field effect transistor, as is clear from the description. However, a MOS field effect transistor can also be manufactured by adding a step of forming a thin insulating film on the substrate.

EFFECTS OF THE INVENTION According to the method for manufacturing a field effect transistor of the present invention described above, the surface of the substrate on which the gate electrode is formed is not damaged, and the gate electrode is self-aligned with the source region and the drain region. Therefore, a field effect transistor having good electric characteristics can be manufactured.

Further, according to the method of manufacturing a field effect transistor of the present invention, it is possible to manufacture a field effect transistor in which a gate electrode is self-aligned with a source region and a drain region with a smaller number of manufacturing steps than in the conventional case.

According to the method for manufacturing a field effect transistor of the present invention described above, an LDD structure in which the gate electrodes are self-aligned can be realized. If such an LDD structure is adopted, even if the gate length is shortened, the speed can be increased without causing the short channel effect.

[Brief description of drawings]

FIG. 1 is a diagram showing steps of a method for manufacturing a field effect transistor according to the present invention. FIG. 2 is a diagram showing steps of a conventional method for manufacturing a field effect transistor. (Main reference numbers) 10 …… Semiconductor substrate, 12 …… Protective insulating film, 14,18 …… Resist, 16 …… Insulating film, 20A, 20B …… Ion implantation area, 24A …… Inversion pattern insulating film, 26A , 26B ... Ohmic electrode, 28 ... Trilayer resist, 30 ... Opening, 32 ... Gate electrode 32, 40 ... Semiconductor substrate, 42 ... Operating layer, 44 ... Resist pattern, 46 ... ECR plasma First insulating film formed by the CVD method, 48 ... Second insulating film, 50 ... Second insulating film left on the side wall of the resist pattern, 52 ... Source region, 54 ... Drain region, 56 ... … Apertures 56, 58 …… Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/336 29/78 29/812

Claims (8)

[Claims] 1. A step of forming a resist pattern corresponding to a gate region on a semiconductor substrate, and forming a first insulating film only on a surface of the substrate and a top surface of the resist pattern by an electron cyclotron resonance plasma CVD method. And a step of forming a second insulating film on the side wall of the resist pattern and on the first insulating film, and the second insulating film so as to leave the second insulating film on the side wall of the resist pattern.
Removing the insulating film, and forming a source region and a drain region by ion implantation into the substrate,
Removing the resist pattern and the first insulating film on the resist pattern by lift-off to form a pattern of the first insulating film having an opening; and forming a self-aligned gate electrode in the opening. A method for manufacturing a field effect transistor, comprising: 2. The method for manufacturing a field effect transistor according to claim 1, wherein the second insulating film is formed by bias sputtering. 3. The method of manufacturing a field effect transistor according to claim 1, wherein the second insulating film is removed by reactive ion etching. 4. After forming a pattern of the first insulating film having the opening, the substrate is annealed to activate the ion-implanted layer, and a heat resistant shot is formed on the substrate in the opening. A method of manufacturing a field effect transistor according to any one of claims (1) to (3), characterized in that a key gate electrode is formed. 5. The field effect transistor according to claim 1, wherein the first insulating film is a silicon nitride film. Production method. 6. The second insulating film is any one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film, as claimed in any one of claims (1) to (5). A method of manufacturing a field effect transistor according to any one of items 1 to 8 above. 7. The field effect transistor according to claim 1, wherein the semiconductor substrate is a III-V group compound semiconductor. Production method. 8. The method for manufacturing a field effect transistor according to claim 7, wherein the III-V compound semiconductor is GaAs.