JPS63137942U - - Google Patents
Info
- Publication number
- JPS63137942U JPS63137942U JP3056187U JP3056187U JPS63137942U JP S63137942 U JPS63137942 U JP S63137942U JP 3056187 U JP3056187 U JP 3056187U JP 3056187 U JP3056187 U JP 3056187U JP S63137942 U JPS63137942 U JP S63137942U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- metal layer
- layer
- substrate
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の第一の実施例を示す集積回路
装置の斜視図、第２図ａ，ｂはそれぞれ本考案の
第二の実施例を説明するための集積回路装置の要
部斜視図および要部平面図、第３図は従来の一例
を説明するための集積回路装置の平面図である。
１…ＧａＡｓ基板、２…格子配線、３…ＧＮＤ
電位の金属層、４…配線層、５…集積回路基板。
FIG. 1 is a perspective view of an integrated circuit device showing a first embodiment of the present invention, and FIGS. 2 a and b are perspective views of essential parts of the integrated circuit device, respectively, for explaining a second embodiment of the present invention. FIG. 3 is a plan view of an integrated circuit device for explaining a conventional example. 1...GaAs substrate, 2...grid wiring, 3...GND
Potential metal layer, 4... wiring layer, 5... integrated circuit board.
Claims (1)
成した配線層と、前記基板上の前記集積回路の周
囲に形成した所定電位保持金属層と、前記金属層
に接続され且つ前記配線層上に空気を介して隔絶
するように立体的に配設した格子配線とを備えた
ことを特徴とする集積回路装置。 A wiring layer formed on the top layer of an integrated circuit consisting of multiple layers on a substrate, a metal layer for holding a predetermined potential formed around the integrated circuit on the substrate, and a metal layer connected to the metal layer and on the wiring layer. 1. An integrated circuit device comprising grid wiring arranged three-dimensionally so as to be isolated through air.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3056187U JPH064590Y2 (en) | 1987-03-02 | 1987-03-02 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3056187U JPH064590Y2 (en) | 1987-03-02 | 1987-03-02 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63137942U true JPS63137942U (en) | 1988-09-12 |
| JPH064590Y2 JPH064590Y2 (en) | 1994-02-02 |
Family
ID=30835485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3056187U Expired - Lifetime JPH064590Y2 (en) | 1987-03-02 | 1987-03-02 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH064590Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0399460A (en) * | 1989-09-12 | 1991-04-24 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0685175A (en) * | 1992-08-31 | 1994-03-25 | Mitsubishi Electric Corp | Semiconductor device |
-
1987
- 1987-03-02 JP JP3056187U patent/JPH064590Y2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0399460A (en) * | 1989-09-12 | 1991-04-24 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0685175A (en) * | 1992-08-31 | 1994-03-25 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH064590Y2 (en) | 1994-02-02 |