JPS63136150A - Memory control device - Google Patents

Abstract

PURPOSE:To perform an access at a high speed to a memory device by detecting immediately an address change via an address latch detecting circuit and sampling an address via an address detecting circuit. CONSTITUTION:An address latch detecting circuit 21 detects an address signal 11 delivered from the computer side when an address signal 12 has a change and then outputs an address sampling signal after the end of the signal 11. An address detecting circuit 27 detects whether an address signal is designating the corresponding memory device or not. If so, an address detecting signal is outputted. A matrix generating circuit 23 detects that a memory read signal 13b or a memory write signal 13a is outputted during input of the address detecting signal. Then both row and column signals are outputted simultaneously to a dynamic random access memory 24 when the signal 13b is outputted. While the matrix signal is outputted to the memory 24 in an output mode of a data signal when the signal 13a is outputted respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory control device used in a system in which peripheral input/output devices are controlled by a computer.

2. Description of the Related Art A conventional memory control device detects an address bus, a data bus, a memory write signal and a memory read signal, and confirms that the address signal specifies the memory device in question among multiple peripheral devices. The memory device was configured to be accessed only after the memory device was accessed. In this way, even a conventional memory control device can perform memory write and memory read.

Problems to be Solved by the Invention However, in the conventional memory control device described above, the memory device is accessed after detecting a memory write signal and a memory read signal, which is an obstacle to shortening processing time.

The present invention solves these conventional problems,
An object of the present invention is to provide an excellent memory control device that can perform high-speed access to a memory device. Means for Solving the Problems The present invention provides an address latch detection circuit and an address detection circuit. The address latch detection circuit quickly detects a change in the address, and the address detection circuit samples the address.

Therefore, according to the present invention, the memory device can be accessed earlier than the memory write signal and the memory read signal.Embodiment FIG. 1 shows the memory control according to the embodiment of the present invention. A block diagram of the apparatus and FIG. 2 are signal waveform diagrams of the same embodiment.

In FIGS. 1 and 2, 1o is a memory device such as an optical file system, 11 is an address latch signal that is output at the same time as the address signal changes, 12 is an address signal that is output via an address bus, and 13a is an address latch signal that is output at the same time as the address signal changes. a memory write signal 13 specifying data writing in the memory device 1o;
b is a memory read signal specifying reading of data from the memory device 10, and 14 is a data signal input/output via the data bus.

21 is an address latch detection circuit that detects the address latch signal 11 and outputs the address sampling signal 26 at that time; 22 is an address detection circuit that inputs the address signal 12; and this address detection circuit 22 inputs the address sampling signal 26. When the address signal 1
2 is accessing the memory device 1o, and if the memory device 1o is being accessed, an address detection signal 27 and a reset signal 26 are output. If the memory device 10 is not accessed yet, the address detection circuit 22 does not output the address detection signal 2 completion, but outputs only the reset signal 26, and ends the process.

23 is a RAS, CAS generation circuit (Row Address
ssSselect , Column Address
This RAS, CAS generation circuit 23 inputs an address detection signal 27, and at this time inputs a part 28 of the address on the path, multiplexes it, and multiplexes it to a DRAM (dynamic random access memory) 24. Txed address signal 30
This outputs the following.

Next, the operation of the above embodiment will be explained.

In FIGS. 1 and 2, when the address latch signal 11 is output from the computer side at the same time as the address signal 12 changes (timing 16), the address latch detection circuit 21 detects the address latch signal 11. When the address latch signal 11 rises (at timing 16, the address signal 12 is changing and has not yet been determined. Then, when the address launch signal 11 falls and the address signal 12 is determined (timing 17), the address detection circuit 2
2 inputs the address signal 12 and outputs an address detection signal 27 when the memory device 10 is being accessed. When this address detection signal 27 is input to the RAS and CAS generation circuit 23, it is detected at timing 18 that either the memory write signal 13ai or the memory read signal 13b is output, and if it is the memory read signal 13b, it is detected at timing 18. RAS, CAS signal 29 to DRA
If it is the memory write signal 13a, the RAS and CAS signals 29 are output to the DRAM 24 at timing 19. At that time, the address signal 12 is generated by multiplexing a part 28 of the address on the bus in the RAS and CAS generation circuit 23, outputting the multiplexed address signal 30 to the DRAM 24, and outputting the data signal 12 to the DRAM 24.
4 is recorded and reproduced in the DRAM 24.

Conventionally, the data signal 14 was input/output from timing 1B onward, but in this embodiment, the data signal 14 is input/output from timing 17, so that the processing speed of the memory device 10 can be improved.

Effects of the Invention As is clear from the above embodiments, the present invention uses an address latch detection circuit to detect an address launch signal generated when an address changes, and the address detection circuit detects whether the address signal specifies the memory device in question. Since the configuration is such that this is detected early and accessed using an address signal to record and reproduce data, the memory device can be accessed earlier than the memory write signal or memory write signal. have an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory control device according to an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of the same embodiment. DESCRIPTION OF SYMBOLS 10...Memory device, 21...Address latch detection circuit, 22...Address detection circuit, 23...RAS, CAS (matrix) generation circuit, 24 ...RAM0 Name of agent Patent attorney Toshio Nakao and 1 other person 2nd
figure

Claims (1)

[Claims] An address latch detection circuit detects an address latch signal output on the computer side when the address signal changes, and outputs an address sampling signal after the end of this address latch signal. an address detection circuit that detects whether or not the signal specifies the memory device, and outputs an address detection signal when the signal specifies the memory device; and a memory read signal while inputting the address detection signal;
It detects that either one of the memory write signals is output, and if it is a memory read signal, it simultaneously outputs the row and column signals to the dynamic random access memory, and if it is a memory write signal, it outputs the matrix signal to the dynamic random access memory when the data signal is output. A memory control device equipped with a matrix generation circuit that outputs to an access memory.