JPS60250454A - Memory controller - Google Patents

Abstract

PURPOSE:To access a CPU to a memory with no queuing time by staring quickly the memory when the address signal fed from the CPU changes to use effectively the access time of the memory. CONSTITUTION:The change of an address signal caused on an address bus A1 is detected by an address change detecting circuit 35. Then a signal ST showing the change of the address signal is sent to a memory control signal generating circuit 31. Then the circuit 31 accesses to a memory 2. In such a case, the circuit 31 starts its operation before a signal showing the selectin of the memory 2 is supplied from an address decoder 32. Then a memory control signal -CS is outputted from the memory 2.

Description

[Detailed description of the invention]

(Technical field) The present invention is directed to
cessingtJnit) to the system. (Prior art) Fig. 4 is a block diagram showing an example of a system using a conventional CPU. u i,'
, main memory 2. The main controller is an interface between the CPLJ 1 and the memory 2, and includes an input/output device 4 and a clock generator 5. CPU
1, the memory serial control device 3, and the input/output device 4 are connected to an address bus A1, an f-tabus D1.1, and an address bus D1.1, respectively. The memory 2 and the memory control unit U3 are connected by a system control signal line C1, and the memory address bus A2. It is coupled by a memory data bus D2 and a memory control signal line C2. -'cCPU from the clock generator 5 via the signal line C3
A clock signal CLK is supplied to the CPU 1 and the memory control device 33, and the CP'U1 operates in synchronization with this clock signal.The memory control device 3 controls the memory 2 from the control signal from the CPU 1 and the clock signal CLK. Create a signal. FIG. 5 is a time chart showing an example of the operation of the memory control device 3. In this time chart, (a)
is the clock signal CLK, and (b) and (c) 4
1 Both are C)) Address output from U 1 (3
Δl, ) R and the door address confirmation signal AS, which is synchronized with the clock signal CLK. (d)

[Yome7 control signal + C (memory select (・1) C8, address (f
It is created by logically multiplying the i No. ADR (de: 1-decode CHINOKU MEMORY SELECT) and the address confirmation signal by 3. Further, here, the clock signal CLK is sampled at the rising edge of the clock signal CLK to generate the control number σf4 of the memo 1. This means that if the address signal ΔD R is decoded and the logical product of the address confirmation number @N1 is AND, if the address signal data]-1- takes a long time, the address confirmation number 1 is The time relationship with 3 is different,
This is to prevent glitches from occurring on the memory control signal surface. In the conventional memory control device J3 that operates in this way, the address is determined because the 1 in the MARI control signal is generated by the AND of the decoded address signal and the address confirmation signal AS. After that, the read/write operation of the memory 2 is started due to the memory control ill signal U being turned off, which takes about 41 to 04 hours. Therefore, there is a problem that a waiting time is added to CP tJ 1 due to the memory having a slow access time or due to this 1] time. (Purpose of the Invention) The present invention has been made in view of the above points, and its purpose is to activate the memory immediately when the address signal from the CPU changes, and to make the access time of the memory effective. The object of the present invention is to realize a memory control device in which the CPo can access the memory without waiting time even if a slow memory is used. (Structure of the Invention) The present invention, which achieves the above four objects, includes an address decoder which is coupled to the CPtJ via an address bus and notifies that a memory has been selected, and an address decoder which is coupled to the address bus and which addresses the address decoder on the address bus. an address change detection circuit that detects a change in a signal; a signal from the address decoder;
Enter the message y-3 and change the address 1')'! A:; from the output circuit is input, and at this time, the memory becomes ac 1?
The present invention is characterized by comprising a control signal light circuit for outputting a control signal for outputting a control signal to the memory. Example) Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. Fig. 1 is a block diagram of the configuration of an example of a device according to the present invention. 32 is an address decoder coupled to the address bus A1 and the control signal line C1 and notifies that MET has been selected; 33 is an address on the address bus A1; F=@ADR A converter for converting R into a memory address signal, 34 t, l A bidirectional data bus control section provided between the data bus D1 and the memory data bus D2, 35 is a converter for converting the address bus △1. The detection signal from the address change detection circuit is applied to the memory control signal generation circuit 31. In the device configured in this way, the address bus A
When the address signal changes in IJ:, this change in the address signal is detected by the address change detection circuit 35, and the address signal changes! ,: Indicating that, a signal @S is sent to the memory control signal generation circuit 31. When the digital control signal generating circuit 31 receives this signal ST, it starts an operation for accessing the memory 2. That is, the memory control signal generating circuit 31 starts operating before the address decoder 32 selects the memory 2 and applies the signal 3, and causes the memory 2 to output the memory control unit signal O8. The memory control signal C8 at this time is a signal that does not destroy the contents of the memory 2, and is used to speed up access to the memory 2. Figure 2 shows DRAM (D ynam) as memory 2.
FIG. 2 is a configuration block diagram showing another example of the memory control device of the present invention applied to a system using icRandom Access Memory. In this device, Ii! is connected to control line 13 C1! i combined, C)) LJ
An address change detection inhibit IJ-circuit 36 is provided to detect address uncertainty time (at the end of access from 1)), and a signal from this is applied to the address change detection circuit 35 and is applied to CI]U1. A selector 37 is provided to switch between the address on the address bus A1 connected to the memory control signal generation circuit 31 and the address on the refreshed address bus A2 connected to the memory control signal generation circuit 31, and the address selected by the selector 37 is set as the I) II A M address. This is what is output as. In this device, the address decoder 32 receives the address signal A sent from CP (J1).
It decodes DR and notifies the control signal generation circuit 31 that the memory 2 has been selected. The address change detection circuit 35 notifies the memory control signal generation circuit 31 that the address signal has changed when the prohibition signal is not output from the address change detection inhibition circuit ζ36. When the memory control signal generation circuit 31 receives this signal, it performs DR toward the memory 2, and also outputs the signal to the selector 33.
7, the CPUlh days 11~res signal and the reflex 1~res signal switching (Ni number and lower address and the 2nd column 71~res switching number 13 are output.Furthermore,
A control signal for controlling the bidirectional data bus is output to the data bus control unit (buffer 1) ζ34. Also, DR
During AM refresh, a refresh address signal is output to the selector 37. Fig. 3 is a time chart 1 showing an example of the operation of the device shown in Fig. 2.
It's to. In this figure, (a) is the clock signal CL
It shows K. Also, ([1) is DR to the address signal output from CPU1, and (c) is the address confirmation signal As.
Both are synchronized with the clock signal CLK. In FIG. 2, the address change detection inhibition circuit 36 is (c)
The address confirmation signal As shown in (a) is sampled by the clock signal CLK''C shown in (a), and the address confirmation signal
Detects that the address becomes high level and the address becomes uncertain, and inhibits (IN'HIBIT) shown in (d).
Signal to address change detection port v! Output to J35. This address change detection circuit 35
-1- When the level goes up, that's it! F) J works are prohibited] L is prohibited. In response to (d), the address change detection circuit 35 detects a change in address at the falling edge of the clock signal CLK when the input signal is at a high level, and outputs the address change to the main control signal generation circuit 3.1. The detection signal (memory start signal) is passed. The memory control signal generation circuit 31 receives this detection signal (J) and outputs the RAS signal as shown in (Bo) to the memory (DR).
AM) 2, and D□RAM takes in the row address and starts one operation. In the address decoder 32, the address signal △ shown in (b)
DR decode and address confirmation signal A shown in (c)
By taking the logical product of s - (Memory 2 is wrong <≧
・Detects that the memory has been selected, and sends a detection signal to the memory control 8 control circuit 31. Memory control No. 3 output circuit 31
By this, we can show (to) 4'(0△S Ii
The column address is generated and sent to the memory (DRAM) 2, which takes in the column address and performs the actual memory read or write operation. In addition, the memory control signal generation circuit 31 outputs a switching signal for refresh of the memory 2, access from the CPU, and a 1=th switching signal for switching the row address and column address as shown in (G) 1. 37, and also outputs a control signal for controlling the bidirectional data bus to the data bus control section 34. In addition, although Fig. 2 shows a platform using I) RAM as the memory 2, SRΔM (3tatic random
ACCe55M 0IIlOrl/) may be used. (Effects of the Invention) As explained above, the present invention provides an address change detection circuit coupled to the address bus (here, c2"; detects as soon as the address signal from u changes,
The present invention is designed to quickly start up the memory, and according to the present invention, even when using fast memory such as DRAM, it is possible to realize a memory control device that allows even a samurai to access the memory in no time. .

[Brief explanation of the drawing]

1 and 2 show an example of the device according to the present invention, and FIG. 3 shows an example of the operation of the device in FIG. An example of the operation of 416 is shown in FIG. 179, and FIG. 1...CP jJ 2...Mail control 3''I...Mail control illumination J31...Mail control (M '>': Start [circuit 3)
2... Horn trest 1-g 35)... Address (Reduction detection circuit 1 Fig. 3 1 pa... )

Claims (1)

[Scope of Claims] An address decoder coupled to CI" tJ via an address bus to inform that a memory is selected l, =; and an address decoder coupled to the address bus to cause an address signal on the address bus to change. 1.: an address change detection circuit for detecting that the address change detection circuit inputs a signal from the address decoder and a signal from the address change detection circuit; A memory control device comprising a memory control signal generation circuit that outputs a memory control signal to the memory in the direction tJ.