JPS63135007A - Method for forming electrode pattern - Google Patents

Method for forming electrode pattern

Info

Publication number
JPS63135007A
JPS63135007A JP28123586A JP28123586A JPS63135007A JP S63135007 A JPS63135007 A JP S63135007A JP 28123586 A JP28123586 A JP 28123586A JP 28123586 A JP28123586 A JP 28123586A JP S63135007 A JPS63135007 A JP S63135007A
Authority
JP
Japan
Prior art keywords
substrate
bake
electrode pattern
static electricity
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28123586A
Other languages
Japanese (ja)
Inventor
Takehiko Sone
竹彦 曽根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP28123586A priority Critical patent/JPS63135007A/en
Publication of JPS63135007A publication Critical patent/JPS63135007A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent damage to a photomask and a substrate by forming a metallic film to both faces of the substrate prior to the photolithography process so as to decrease static electricity caused due to the temperature rise/decrease attended with a pre-bake or post-bake. CONSTITUTION:Prior to the pre-bake process, a metallic film 2 and an electrode layer 3 are formed to both faces of a substrate 1. Since the partial existence of electric charges generated in the substrate 1 generated in substrate 1 in the heat of the pre-bake process is canceled by a metallic plate 2 and an electrode film 3, the generation of static electricity is suppressed, no photomask 5 is attracted to the substrate 1 in the succeeding exposure process and the damage to the photomask 5 and the substrate 1 is prevented. Since the production of static electricity is suppressed in the succeeding post-bake process, dust floating in air is not stuck to the substrate 1 during the manufacture process.

Description

【発明の詳細な説明】 「技術分野」 本発明は、例えば弾性表面波素子のすだれ状電極や反射
器などの形成に適した電極パターンの形成方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for forming an electrode pattern suitable for forming, for example, interdigital electrodes and reflectors of surface acoustic wave devices.

「従来技術およびその問題点」 近年、各種電子部品の製造に際し、基板面に形成された
電極膜などのパターン化にフォトリソグラフィが盛んに
利用されている。
"Prior Art and its Problems" In recent years, photolithography has been widely used for patterning electrode films formed on substrate surfaces in the manufacture of various electronic components.

このフォトリソグラフィーの一般的な工程を弾性表面波
素子の電極パターンの形成方法を例にとつ説明すると、
第3図に示すように、まず圧電基板を研磨、洗浄しくS
l)、この基板面に電極膜を形成する(S2)。そして
レジスト膜中布しくS3)、プリベークを行ない(S4
)、フォトマスクを被せで露光しくS5)、現像および
必要に応じてリンスを行ない(S6)、ポストベークを
しくS7)、エツチングを行ない(S8)、最後にレジ
ストを剥離する(S9)工程を経で、基板面上に所定の
電極パターンを形成しでいる。
The general process of photolithography will be explained using the method of forming an electrode pattern of a surface acoustic wave device as an example.
As shown in Figure 3, first the piezoelectric substrate is polished and cleaned.
l), forming an electrode film on this substrate surface (S2); Then, the resist film is laid down (S3) and prebaked (S4).
), exposing with a photomask (S5), developing and rinsing if necessary (S6), post-baking (S7), etching (S8), and finally removing the resist (S9). A predetermined electrode pattern is then formed on the substrate surface.

この工程の中で、レジスト塗布工程(S3)でレジスト
を塗布した基板は、次のプリベーク工程(S4)でレジ
スト膜中の溶媒を揮発させ、接着力を強めるために通常
オーブン等の中で70℃〜90°C位に加熱される。ま
た、現像の工程(S6)が鞍了すると、ボストベーク工
程(S7)において現像、リンスによっで膨潤、軟化し
たレジストの接着力、耐薬品性を向上させるために再び
オーブン等の中で加熱される。
In this process, the substrate coated with resist in the resist coating process (S3) is usually placed in an oven for 70 minutes to volatilize the solvent in the resist film and strengthen the adhesive strength in the next pre-baking process (S4). It is heated to about 90°C. When the development step (S6) is completed, the resist, which has been swollen and softened by development and rinsing, is heated in an oven or the like again in the post-bake step (S7) to improve its adhesive strength and chemical resistance. Ru.

ところが、基板の材料が例えばニオブ酸リチウムやタン
タル酸リチウム等のような焦電性単結晶であると、この
基板の温度を変化させる工程(前記したブリヘーク、ポ
ストヘーク)で基板表面に静電気か発生しでしまう。こ
の静電気のため、例えばプリベーク工程(S4)の後の
露光工程(S5)で、マスクに基板面が吸着されてしま
い、基板が剥がれに<<<なつ、基板を破損したり、マ
スクを損傷したつするという問題点があった。また、こ
の静電気のため、空気中に浮遊している像細なゴミなど
が基板に付着しやすくなるという問題点があった。した
かっで、基板に発生する静電気により、歩留りが大幅に
低下してしまうという結果を招いていた。
However, if the substrate material is a pyroelectric single crystal such as lithium niobate or lithium tantalate, static electricity is generated on the substrate surface during the process of changing the temperature of the substrate (the above-mentioned pre-hake and post-hake). It's gone. Due to this static electricity, for example, during the exposure step (S5) after the pre-bake step (S4), the substrate surface is attracted to the mask, causing the substrate to peel off, damaging the substrate, or damaging the mask. There was a problem with this. Furthermore, due to this static electricity, there is a problem in that fine particles floating in the air tend to adhere to the substrate. As a result, static electricity generated on the substrate resulted in a significant drop in yield.

「発明の目的」 本発明の目的は、このような基板を加熱する工程で発生
する静電気に起因する種々の問題点を解決するようにし
た電極パターンの製造方法を提供することにある。
[Object of the Invention] An object of the present invention is to provide a method for manufacturing an electrode pattern that solves various problems caused by static electricity generated in the process of heating a substrate.

「発明の構成J 本発明による電極パターンの形成方法は、焦電性単結晶
から成る基板上に電極パターンをフォトリソグラフィに
より形成する方法であって、2オリソ工程の前に前記基
板の両面に金属膜を形成しておくことを特徴とする。
“Structure of the Invention J” The method for forming an electrode pattern according to the present invention is a method of forming an electrode pattern on a substrate made of a pyroelectric single crystal by photolithography, and the method includes forming an electrode pattern on both sides of the substrate before a 2-ortho process. It is characterized by forming a film.

このように、フォトリソ工程の前に基板の両面に金属膜
を形成してあくことにより、フォトリソ工程中の温度の
昇降により基板内で発生する電荷の偏在は、基板の両面
に形成された金属膜によって中和あるいは解消され、静
電気現象を減少させることができる。このため、露光時
に基板に被せるマスクに基板が吸着されることがなくな
り、また、突気中に浮遊している微細なゴミ等が基板に
付着することも少なくなる。したがって、基板に発生す
る静電気に起因する不良品の発生がなくなり、歩留りを
大幅に向上させることができる。
In this way, by forming a metal film on both sides of the substrate before the photolithography process, uneven distribution of charges generated within the substrate due to temperature rises and falls during the photolithography process can be prevented by forming metal films on both sides of the substrate. can be neutralized or eliminated, reducing static electricity phenomena. For this reason, the substrate is not attracted to the mask placed over the substrate during exposure, and fine particles floating in the air are less likely to adhere to the substrate. Therefore, the generation of defective products due to static electricity generated on the substrate is eliminated, and the yield can be significantly improved.

本発明の電極パターンの形成方法は、二オフ酸リチウム
やタンタル酸リチウム等の焦電性単結晶を材料とする基
板に対して特に効果的な方法である。上記のような焦電
性単結晶を材料とする基板を用いるものとしては、例え
ば弾性表面波素子などが挙げられる。
The method for forming an electrode pattern of the present invention is particularly effective for substrates made of pyroelectric single crystals such as lithium dioffate and lithium tantalate. Examples of devices using a substrate made of a pyroelectric single crystal as described above include surface acoustic wave devices.

「発明の実施例」 第1図には、本発明による電極パターンの形成方法の一
実施例か示されでいる。第1図中(a)は工程に従って
示した基板の断面図であり、第1図中(b)はそのフロ
ーチャートである。
"Embodiment of the Invention" FIG. 1 shows an embodiment of the method for forming an electrode pattern according to the present invention. (a) in FIG. 1 is a cross-sectional view of the substrate shown according to the steps, and (b) in FIG. 1 is a flowchart thereof.

ます、角形および丸型のニオブ酸リチウム基板1を研磨
、洗浄しくSl)、この基板1の電極パターン形成面裏
面に、基板1の温度を上昇させない方法によりCr、■
1等の高融点金1を用いた第1の金属膜2を成膜する(
S2)、次に、電極パターン形成面にAIの電極膜3を
全面形成しくS3)、この電極膜3上にレジスト4を所
定の厚さでスピンコードする(S4)、その後、スピン
コードしたレジスト4の膜中の溶媒を揮発させ、接着力
を強めるために70℃〜90℃位で一定時間オーブンで
加熱しくS5)、電極パターン形成面上に所定のマスク
パターンを有するフォトマスク5を被せ、紫外線L!2
秒間位照射し、露光を行なう(S6)。次に、現像液に
60秒間浸漬し、現像を行ない(S7)、基板1上に成
膜された電極膜3上に現像されたレジスト4を形成する
。ざらに、このレジスト4の現像工程(こおいで膨潤、
軟化したレジスト4の接着力、耐薬品性を向上させるた
めに140℃〜150℃位で一定時間オーブンで加熱し
くS8)、リン酸系エツチング液に浸漬して露出した部
分を溶解し、最賛的に電極パターンを形成する(S9)
。そして、最後に、エツチング液を十分に流水中で洗浄
し乾燥後、指定の剥離液を用いてレジスト4を除去しく
5IO)、所定の電極パターンが形成された弾性表面波
素子を作成した(Sl+)。なお、この後、基板1の裏
面に形成された第1の金R膜2をエツチング除去しても
よい。上記においで、本発明におけるフォトリソ工程と
は、レジスト塗布工程(S4)、プリベーク工程(S5
)、露光工程(S6)、現像工程(S7)およびボスト
ベーク工程(S8)を示しでおり、プリベーク工程(S
5)およびボストベーク工程(S8)においで基板1の
加熱がなされる。
First, the square and round lithium niobate substrates 1 are polished and cleaned (Sl), and Cr,
A first metal film 2 is formed using high melting point gold 1 of the 1st grade (
S2), Next, an AI electrode film 3 is formed on the entire surface of the electrode pattern formation surface (S3), and a resist 4 is spin-coded to a predetermined thickness on this electrode film 3 (S4). In order to volatilize the solvent in the film of step 4 and strengthen the adhesive force, heat it in an oven at about 70° C. to 90° C. for a certain period of time (S5), and cover the electrode pattern forming surface with a photomask 5 having a predetermined mask pattern. Ultraviolet L! 2
Exposure is performed by irradiating for about seconds (S6). Next, it is immersed in a developer for 60 seconds to perform development (S7), and a developed resist 4 is formed on the electrode film 3 formed on the substrate 1. Roughly, the development process of this resist 4 (swelling by blowing,
In order to improve the adhesive strength and chemical resistance of the softened resist 4, it was heated in an oven for a certain period of time at about 140 to 150 degrees Celsius (S8), and then immersed in a phosphoric acid-based etching solution to dissolve the exposed parts. Form an electrode pattern (S9)
. Finally, after thoroughly washing the etching solution under running water and drying, the resist 4 was removed using a specified stripping solution (5IO) to create a surface acoustic wave element with a predetermined electrode pattern (Sl+ ). Note that after this, the first gold R film 2 formed on the back surface of the substrate 1 may be removed by etching. In the above, the photolithography process in the present invention includes a resist coating process (S4), a pre-bake process (S5
), an exposure process (S6), a development process (S7), and a post-bake process (S8), and a pre-bake process (S
5) and the post-bake step (S8), the substrate 1 is heated.

この実施例においでは、プリベーク工程(S5)8行な
う前に、基板1の両面に金属膜2および電極膜3が形成
されでいるので、プリベーク工程(S5)における加熱
の際に基板1に発生した電荷の偏在が金a膜2および電
極膜3によって解消されるので、静電気の発生か抑えら
れ、その後の露光工程(S6)においで基板1にフォト
マスク5が吸着されることがなくなり、フォトマスク5
の損傷や基板1の破損が防止された。また、その復のポ
ストヘーク工程(S8)においても静電気の発生が抑え
られるので、空気中に浮遊するゴミなどが製造工程中に
基板1に付着することも防止された。したがって、製品
の歩留りを大幅に向上させることが可能となった。
In this example, the metal film 2 and the electrode film 3 are formed on both sides of the substrate 1 before the pre-bake step (S5) 8 is performed, so that the metal film 2 and the electrode film 3 are formed on both sides of the substrate 1 before the pre-bake step (S5). Since the uneven distribution of charges is eliminated by the gold a film 2 and the electrode film 3, the generation of static electricity is suppressed, and the photomask 5 is prevented from being attracted to the substrate 1 in the subsequent exposure step (S6). 5
Damage to the substrate 1 and damage to the substrate 1 were prevented. Furthermore, since the generation of static electricity is suppressed in the subsequent post-hake step (S8), it is also possible to prevent dust floating in the air from adhering to the substrate 1 during the manufacturing process. Therefore, it has become possible to significantly improve the yield of products.

第2図には、本発明による電極パターンの形成方法の他
の実施例か示されている。第2図中(a)は工程に従っ
て基板の断面図であり、第1図中(b)はそのフローチ
ャートである。
FIG. 2 shows another embodiment of the method for forming an electrode pattern according to the present invention. (a) in FIG. 2 is a cross-sectional view of the substrate according to the process, and (b) in FIG. 1 is a flowchart thereof.

この実施例は、本発明をリフトオフ法による電極パター
ン形成方法に適用したものであり、実施例]においで説
明した81〜S8の工程はほぼ同様である。まず、基板
1を研磨、洗浄しくSl)、この基板1の電極パターン
形成面裏面に、基板1の温度そ上昇させない方法により
Cr、 Ti等の高融点金属を用いた第1の金属膜2を
成膜する(S2)、次に、電極パターン形成面にCr、
 Ti等の高融点金属からなる第2の金属膜6を全面形
成しくS3)、この電極膜6上にレジスト4を所定の厚
さでスピンニートする(S4)。その後、ブリヘークし
くS5)、所定のマスクパターンを有するフォトマスク
5を被せ、紫外線りを2秒間位照射し、露光を行なう(
S6)、次に、現像液に60秒間浸漬し、現像を行ない
(S7)、第2の金属膜6上にレジスト4を形成する。
In this example, the present invention is applied to an electrode pattern forming method using a lift-off method, and the steps 81 to S8 described in Example] are almost the same. First, the substrate 1 is polished and cleaned (Sl), and a first metal film 2 made of a high melting point metal such as Cr or Ti is formed on the back surface of the electrode pattern forming surface of the substrate 1 by a method that does not increase the temperature of the substrate 1. Form a film (S2), then Cr,
A second metal film 6 made of a high melting point metal such as Ti is formed on the entire surface (S3), and a resist 4 is spin-neat to a predetermined thickness on this electrode film 6 (S4). After that, in step S5), a photomask 5 having a predetermined mask pattern is placed on it, and ultraviolet rays are irradiated for about 2 seconds to perform exposure (
S6) Next, the resist 4 is immersed in a developer for 60 seconds to perform development (S7), and a resist 4 is formed on the second metal film 6.

ざらに、このレジスト4を必要であれば、ポストへ−り
(S8)する。
Roughly, if necessary, this resist 4 is sent to the post (S8).

ボストヘーク(S8)終了俊、電極パターン形成面上に
AI又はAu等の第3の金属膜7を全面形成しくS9)
、レジスト4vi−除去してリフトオフ法によつ第3の
金属膜7をパターン化する(510)。その後、エツチ
ング液に浸漬する等しでCr、Ti等からなる第2の金
属膜6のみを選択的にエツチングする。これにより、第
3の金属膜7で覆われた部分のみが残つ、第2の金属膜
6および第3の金属膜7かうなる電極パターンが形成さ
れる(SI +)。なお、この実施例ては、基板1の裏
面に形成した第1の金属膜2が第2の金属膜6と同様な
材質からなるので上記エツチング時に一緒に除去されで
いる金属膜2及び6を異なる材質で形成して、金属膜2
が残るようにしでもよい。こうして、所定の電極パター
ンか形成された弾′注表面波素子を作成した。
After completion of Bosthake (S8), a third metal film 7 such as AI or Au is to be entirely formed on the electrode pattern formation surface (S9).
, the resist 4vi is removed and the third metal film 7 is patterned by a lift-off method (510). Thereafter, only the second metal film 6 made of Cr, Ti, etc. is selectively etched by immersing it in an etching solution or the like. As a result, an electrode pattern consisting of the second metal film 6 and the third metal film 7 is formed in which only the portion covered with the third metal film 7 remains (SI + ). In this embodiment, since the first metal film 2 formed on the back surface of the substrate 1 is made of the same material as the second metal film 6, the metal films 2 and 6, which are removed together during the above etching, are removed. The metal film 2 is made of different materials.
may remain. In this way, a bullet injection surface wave device with a predetermined electrode pattern was produced.

この実施例においても、フォトリソ工程(こ入る前に、
基板1の表裏面に第2の金属膜6および第1の金属膜1
が形成されでいるので、ブリヘーク工程(S5)や、ポ
ストヘーク工程(S8)における静電気の発生を防止す
ることができ、前述した実施例と同様な効果を得ること
ができた。
In this example as well, before starting the photolithography process,
A second metal film 6 and a first metal film 1 are formed on the front and back surfaces of the substrate 1.
was not formed, it was possible to prevent the generation of static electricity in the pre-hake step (S5) and the post-hake step (S8), and it was possible to obtain the same effects as in the above-mentioned embodiments.

「発明の効果」 以上説明したように、本発明によれば、フォトリソ工程
の前に、基板の表裏面に金属膜を形成するようにしたの
で、ブリヘークやボストヘークに伴なう温度の昇降によ
り発生する静電気を減少させることができる。このため
、基板が静電気によってフォトマスク(ζ吸着されるこ
とがなくなり、フォトマスクの損傷や基板の破損を防止
できる。また、空気中に浮遊するゴミなどが静電気によ
つ基板に付着することも防止できる。したかつて、歩留
りを大幅に向上させることが可能となる。
"Effects of the Invention" As explained above, according to the present invention, metal films are formed on the front and back surfaces of the substrate before the photolithography process. can reduce static electricity. This prevents the substrate from being attracted to the photomask (ζ) due to static electricity, preventing damage to the photomask and damage to the substrate.Furthermore, dust floating in the air is prevented from adhering to the substrate due to static electricity. By doing so, it is possible to significantly improve yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の電極パターンの形成方法の一実施例を
示す工程図、第2図は本発明の電極パターンの形成方法
の他の実施例を示す工程図、舅3図は従来の電極パター
ンの形成方法の一例を示す工程図である。
Fig. 1 is a process diagram showing one embodiment of the method for forming an electrode pattern according to the present invention, Fig. 2 is a process diagram showing another embodiment of the method for forming an electrode pattern according to the present invention, and Fig. FIG. 3 is a process diagram showing an example of a pattern forming method.

Claims (1)

【特許請求の範囲】[Claims]  焦電性単結晶から成る基板上に電極パターンをフォト
リソグラフィにより形成する電極パターンの製造方法に
おいて、フォリソグラフィー工程の前に前記基板の両面
に金属膜を形成しておくことを特徴とする電極パターン
の形成方法。
An electrode pattern manufacturing method in which an electrode pattern is formed by photolithography on a substrate made of a pyroelectric single crystal, characterized in that a metal film is formed on both sides of the substrate before the photolithography step. How to form.
JP28123586A 1986-11-26 1986-11-26 Method for forming electrode pattern Pending JPS63135007A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28123586A JPS63135007A (en) 1986-11-26 1986-11-26 Method for forming electrode pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28123586A JPS63135007A (en) 1986-11-26 1986-11-26 Method for forming electrode pattern

Publications (1)

Publication Number Publication Date
JPS63135007A true JPS63135007A (en) 1988-06-07

Family

ID=17636244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28123586A Pending JPS63135007A (en) 1986-11-26 1986-11-26 Method for forming electrode pattern

Country Status (1)

Country Link
JP (1) JPS63135007A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006014099A (en) * 2004-06-28 2006-01-12 Kyocera Corp Surface acoustic wave device and manufacturing method thereof, and communication device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006014099A (en) * 2004-06-28 2006-01-12 Kyocera Corp Surface acoustic wave device and manufacturing method thereof, and communication device
JP4610244B2 (en) * 2004-06-28 2011-01-12 京セラ株式会社 Manufacturing method of surface acoustic wave device

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