JPH02139972A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02139972A JPH02139972A JP29383488A JP29383488A JPH02139972A JP H02139972 A JPH02139972 A JP H02139972A JP 29383488 A JP29383488 A JP 29383488A JP 29383488 A JP29383488 A JP 29383488A JP H02139972 A JPH02139972 A JP H02139972A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- photoresist
- printing method
- manufacturing
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims description 15
- 239000012212 insulator Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 16
- 239000011521 glass Substances 0.000 abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、特に液晶と組み合わせて画像表示
装置を構成するための薄膜トランジスタ（以後ティーエ
フティ（Ｔ Ｆ Ｔ）と呼ぶ）および液晶に電圧を印加
する表示電極をマトリクス状に形成したＴＦＴアレイの
製造方法に間するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device, particularly to a thin film transistor (hereinafter referred to as TFT) for constructing an image display device in combination with a liquid crystal and a thin film transistor for applying voltage to a liquid crystal. The present invention relates to a method of manufacturing a TFT array in which display electrodes are formed in a matrix.
従来の技術 第２図にＴＦＴアレイの要部構成断面図を示す。Conventional technology FIG. 2 shows a sectional view of the main part of the TFT array.
ガラス基板１上に例えばクロム等のゲート電極２なる第
１の導電体層が形成され、非晶質シリコン半導体層４が
窒化シリコンゲート絶縁体層３を介して形成され、アル
ミニウムまたはチタン等のソース、ドレイン電極５ａ、
５ｂなる第２の導電体層およびドレイン電極５ｂと接続
されているＩＴＯ等からなる透明表示電極６が形成され
ている。A first conductor layer, which is a gate electrode 2 made of, for example, chromium, is formed on a glass substrate 1, an amorphous silicon semiconductor layer 4 is formed with a silicon nitride gate insulator layer 3 interposed therebetween, and a source material, such as aluminum or titanium, is formed on a glass substrate 1. , drain electrode 5a,
A transparent display electrode 6 made of ITO or the like is formed, which is connected to the second conductor layer 5b and the drain electrode 5b.
次に上述の構造を持つＴＦＴアレイの従来の製作工程に
ついて簡単に説明する。まず、ガラス基板ｌ上全面にに
クロムをスパッタ蒸着し、フォトリソグラフィによりク
ロムの不用部分を除去して所望の形状のゲート電極２を
形成する。ついで全面に窒化シリコンゲ、−ト絶縁体層
３、非晶質シリコン半導体層を化学気相堆積法等により
順次被４着する。その後、第２図に示すように、非晶質
シリコン半導体層をフォトリソグラフィを用いて島状の
半導体層４にする。さらに、酸化インジウム−スズ（Ｉ
ＴＯ）を全面にスパッタ蒸着した後、フォトリソグラフ
ィによりＩＴＯの不用部分を除去して所望の形状の透明
表示電極６を形成する。そして最後に、アルミニウムを
全面にスパッタ蒸着した後、フォトリソグラフィにより
アルミニウムの不用部分を除去して所望の形状のソース
、ドレイン電極５ａ、５ｂを形成してＴＰＴプレイが完
成する。Next, a conventional manufacturing process for a TFT array having the above structure will be briefly explained. First, chromium is sputter-deposited over the entire surface of the glass substrate l, and unnecessary portions of the chromium are removed by photolithography to form the gate electrode 2 in a desired shape. Next, a silicon nitride layer, an insulator layer 3, and an amorphous silicon semiconductor layer are sequentially deposited on the entire surface by chemical vapor deposition or the like. Thereafter, as shown in FIG. 2, the amorphous silicon semiconductor layer is formed into an island-shaped semiconductor layer 4 using photolithography. Additionally, indium-tin oxide (I
After sputter-depositing ITO (TO) over the entire surface, unnecessary portions of ITO are removed by photolithography to form transparent display electrodes 6 having a desired shape. Finally, after aluminum is sputter-deposited over the entire surface, unnecessary portions of aluminum are removed by photolithography to form source and drain electrodes 5a and 5b of desired shapes, thereby completing the TPT play.
発明が解決しようとする課題
前述のＴＦＴアレイの製造方法では所望の形状の電極等
を形成するために、少なくとも４回のフォトリソグラフ
ィを用いている。このフォトリソグラフィは、材料上に
塗布したフォトレジスト（感光性樹脂）をフォトマスク
を通して露光しくこの時すでに前のフォトリソグラフィ
により形成した形状に整合させる必要がある）、次いで
現像することにより所望の形状として残し、レジストが
残らずに露出している各材料の不要部分をエツチングし
て除去する技術である。このようにフォトリソグラフィ
は所望の形状を形成するために、フォトレジスト塗布−
フオドマスク整合−露光一現像一エッチングーレジスト
除去というように多くの工程が必要であるという課題を
有する。さらに大型基板にフォトマスクを使うフォトリ
ソグラフィにより所望の形状を形成するためには、数度
に分割して露光する必要があり、従って工程数が増加し
、分割部分を精密に整合させることが技術的に困難であ
るという課題を有している。Problems to be Solved by the Invention In the method for manufacturing a TFT array described above, photolithography is performed at least four times in order to form electrodes and the like in a desired shape. In this photolithography, a photoresist (photosensitive resin) coated on a material is exposed through a photomask (this time it is necessary to match the shape already formed by the previous photolithography), and then developed to create the desired shape. This is a technique in which the unnecessary parts of each exposed material are etched away without leaving any resist. In this way, photolithography involves applying photoresist to form a desired shape.
The problem is that many steps are required, such as photomask alignment, exposure, development, etching, and resist removal. Furthermore, in order to form a desired shape on a large substrate using photolithography using a photomask, it is necessary to divide the exposure into several parts, which increases the number of steps and requires precise alignment of the divided parts. The problem is that it is technically difficult.
一方、大型基板に上述したようなりロム等の材料をスパ
ッタ法等により蒸着するためには非常に大型の真空装置
が必要であるため、製造コストが高価になるという課題
も有している。On the other hand, since a very large vacuum apparatus is required to deposit a material such as the above-mentioned ROM onto a large substrate by sputtering or the like, there is also the problem that the manufacturing cost becomes high.
本発明はかかる従来の技術の課題に鑑みなされたもので
、ＴＦＴアレイの導電体層を印刷法により形成すること
により、フォトマスクを使用するフォトリソグラフィを
用いることなく半導体装置の製造方法を提供することを
目的としている。The present invention was made in view of the problems of the conventional technology, and provides a method for manufacturing a semiconductor device by forming a conductor layer of a TFT array by a printing method without using photolithography using a photomask. The purpose is to
課題を解決するための手段
本発明は、ゲート、ソース、ドレイン電極の導電体層あ
るいは透明表示電極の少なくともひとつを印刷法により
形成するものである。Means for Solving the Problems In the present invention, at least one of the conductor layers of the gate, source, and drain electrodes or the transparent display electrode is formed by a printing method.
また、基板上に塗布したフォトレジストをゲート電極な
る第１．の導電体層をフォトマスクの代用にして露光、
現像してゲート電極形状に残し、その後フォトレジスト
が残らずに露出している半導体層等の不要部分をエツチ
ングして除去する。In addition, the photoresist coated on the substrate is used as the first gate electrode. Exposure using the conductor layer as a photomask,
The photoresist is developed to remain in the shape of the gate electrode, and then unnecessary portions of the exposed semiconductor layer and the like are removed by etching so that no photoresist remains.
作用
本発明は上述したように、各種電極の形成方法として印
刷法を用いることにより、それぞれの電極の必要部分の
みを所望の形状で被着形成できるため、フォトマスクを
使うフォトリソグラフィが必要なく、また分割して形成
する必要がないため大型基板にも一度の工程で容易に形
成できる。Function As described above, the present invention uses a printing method as a method for forming various electrodes, so that only the necessary portions of each electrode can be formed in a desired shape, so there is no need for photolithography using a photomask. Furthermore, since there is no need to form the film in separate parts, it can be easily formed on a large substrate in a single process.
また、ゲート電極なる第１の導電体層をフォトマスクの
代用にしてフォトレジストを露光して現像することによ
り、フォトマスクを使用することなく必要とする半導体
層等をゲート電極に整合して形成できる。In addition, by exposing and developing the photoresist using the first conductive layer, which is the gate electrode, as a photomask, the necessary semiconductor layers can be formed in alignment with the gate electrode without using a photomask. can.
以上述べたように本発明によればフォトマスクを使うフ
ォトリソグラフィを用いずに各材料を所望の形状で形成
できるため、大型基板を用いてもＴＦＴアレイを容易に
製造できる。As described above, according to the present invention, each material can be formed into a desired shape without using photolithography using a photomask, so a TFT array can be easily manufactured even if a large substrate is used.
実施例
以下、本発明の実施例について図面に基づいて説明する
。Embodiments Hereinafter, embodiments of the present invention will be described based on the drawings.
第１図に本実施例のＴＦＴアレイの工程断面図を示す。FIG. 1 shows a process sectional view of the TFT array of this embodiment.
第１図（ａ）に示すようにガラス基板ｌ上にゲート電極
２となる金属（例えば金、銀、白金、銅、アルミニウム
、クロム、タングステン、チタン等）を印刷法により図
のような形状で被着する０次に第１図（ｂ）に示すよう
に全面に化学気相堆積法により窒化シリコンゲート絶縁
体層３を被着し、さらに半導体層４１（例えば多結晶シ
リコン半導体、非晶質シリコン半導体等）を連続して被
着する。そして以下のような方法にて不必要な部分の半
導体層を除去する。まず、ポジ型フォトレジスト（未感
光部分のフォトレジストが現像後に残る）を全面に塗布
後ガラス基板ｌの裏面より光を照射することにより、ゲ
ート電極２が形成されていない場所のフォトレジストが
露光され（裏面露光）、ついで現像することによりゲー
ト電極２上にフォトレジストが残る。そしてフォトレジ
ストが残存していない部分の半導体層４１をエツチング
し、その後フォトレジストを除去すると第１図（ｃ）に
示すような半導体層４が形成される。このようにして不
必要な部分の半導体層を除去した後、第１図（ｄ）に示
すような形状でＩＴＯからなる透明表示電極６を印刷法
により形成し、最後に第２図に示すうな形状でソース、
ドレイン電極５ａ、５ｂとなる金属（例えば上述した金
属）を印刷法により形成して、本発明によるＴＰＴプレ
イが完成する。As shown in Figure 1(a), a metal (for example, gold, silver, platinum, copper, aluminum, chromium, tungsten, titanium, etc.) that will become the gate electrode 2 is printed on a glass substrate l in the shape shown in the figure. As shown in FIG. 1(b), a silicon nitride gate insulator layer 3 is deposited on the entire surface by chemical vapor deposition, and a semiconductor layer 41 (for example, a polycrystalline silicon semiconductor, an amorphous (silicon semiconductor, etc.) is continuously deposited. Then, unnecessary portions of the semiconductor layer are removed by the following method. First, after coating a positive photoresist (unexposed areas of the photoresist remain after development), light is irradiated from the back side of the glass substrate l, exposing the photoresist in areas where the gate electrode 2 is not formed. The photoresist is left on the gate electrode 2 by exposure (backside exposure) and development. Then, the portions of the semiconductor layer 41 where no photoresist remains are etched, and then the photoresist is removed to form the semiconductor layer 4 as shown in FIG. 1(c). After removing unnecessary portions of the semiconductor layer in this manner, transparent display electrodes 6 made of ITO are formed by printing in the shape shown in FIG. 1(d), and finally, as shown in FIG. Source in shape,
The TPT play according to the present invention is completed by forming the metals (for example, the metals mentioned above) that will become the drain electrodes 5a and 5b by a printing method.
本実施例によれば、ゲート、ソース、ドレインの各電極
および透明表示電極となる導電体材料を、フォトリソグ
ラフィを用いずに必要とする形状で形成できる。従って
、例えば１ｍ四方のような大型基板上にも精密な分割露
光によるフォトリソグラフィを用いることなく容易にＴ
ＦＴアレイを製造できる。According to this embodiment, the conductive material that becomes the gate, source, and drain electrodes and the transparent display electrode can be formed in the required shape without using photolithography. Therefore, even on a large substrate, such as one meter square, T can be easily applied without using photolithography using precise divided exposure.
FT arrays can be manufactured.
次に他の実施例について説明する。Next, other embodiments will be described.
本実施例では第１の実施例と同様第３図（ａ）に示すよ
うにガラス基板２１上にゲート電極２２を形成する０次
に全面に化学気相堆積法により窒化シリコンゲート絶縁
体層、半導体層（例えば多結晶シリコン半導体、非晶質
シリコン半導体等）、第２の窒化シリコン絶縁体層を連
続被着した後に、第１の実施例で不要な半導体層を除去
した方法と同一方法（裏面露光）を用いて、第２の窒化
シリコン絶縁体層を第３図（ｂ）に示すような形状の保
護絶縁体層７にする。つづいて印刷法によりソース、ド
レイン電極２５ａ、２５ｂを形成し、フッ酸と硝酸の混
合液に基板を浸漬して保護絶縁体層およびソース、ドレ
イン電極が形成されていない部分である一部の不要な半
導体層を除去する（第３図（ｃ）に示す）。最後に第３
図（ｄ）に示すように印刷法により透明表示電極２６を
形成して、本実施例のＴＦＴアレイが完成する。In this embodiment, as in the first embodiment, a gate electrode 22 is formed on a glass substrate 21 as shown in FIG. After sequentially depositing a semiconductor layer (for example, a polycrystalline silicon semiconductor, an amorphous silicon semiconductor, etc.) and a second silicon nitride insulating layer, the unnecessary semiconductor layer was removed in the first embodiment ( Using backside exposure), the second silicon nitride insulator layer is formed into a protective insulator layer 7 having a shape as shown in FIG. 3(b). Next, the source and drain electrodes 25a and 25b are formed by a printing method, and the substrate is immersed in a mixed solution of hydrofluoric acid and nitric acid to remove a protective insulator layer and a part of the unnecessary portion where the source and drain electrodes are not formed. (as shown in FIG. 3(c)). Finally the third
As shown in Figure (d), transparent display electrodes 26 are formed by a printing method to complete the TFT array of this example.
本実施例ではソース、ドレイン電極間のチャンネル部と
なる半導体層上に保護絶縁体層が形成されるためＴＰＴ
特性が安定化する。In this example, since a protective insulator layer is formed on the semiconductor layer which becomes the channel part between the source and drain electrodes, the TPT
Characteristics are stabilized.
次に他の実施例について説明する。Next, other embodiments will be described.
本実施例では、上述した第１の実施例の製作工程におい
て第１図（Ｃ）に示す工程まで同様の工程で制作し、そ
の後第４図に示すように、ＩＴＯからなるソース電極３
５とドレイン電極と透明表示電極が一体化した電極３６
を同時に印刷法により形成して、本実施例のＴＦＴアレ
イが完成する。In this example, the manufacturing process is similar to that of the first example described above up to the step shown in FIG. 1(C), and then as shown in FIG.
5, an electrode 36 in which a drain electrode and a transparent display electrode are integrated.
are simultaneously formed by a printing method to complete the TFT array of this example.
本実施例によれば、ソース、ドレイン電極と透明表示電
極を同一工程で形成できるために工程数を削減でき、さ
らに製作コストを低減できる効果を有する。According to this embodiment, since the source and drain electrodes and the transparent display electrode can be formed in the same process, the number of processes can be reduced, and the manufacturing cost can also be reduced.
なお、本発明の３実施例ではゲート、ソース、ドレイン
の各電極および透明表示電極のすべてを印刷法により形
成することについて説明したが、本発明ではこれら電極
の少なくとも一つを印刷法により形成するだけでも従来
に比べ、制作コストの低減、大型基板を用いた製造の容
易性の向上、等の効果を有する。In addition, in the three embodiments of the present invention, it has been explained that all of the gate, source, and drain electrodes and the transparent display electrode are formed by the printing method, but in the present invention, at least one of these electrodes is formed by the printing method. This alone has the effect of reducing production costs and improving ease of manufacturing using large substrates compared to conventional methods.
以上本発明の詳細な説明では、ＴＰＴの構造がガラス基
板上にゲート電極、ゲート絶縁体層、半導体層、ソース
、ドレイン電極の順に形成するいわゆる逆スタガ構造の
製造方法について説明したが、ソース、ドレイン電極、
半導体層、ゲート絶縁体層、ゲート電極の順に形成する
スタガ構造の製造方法についても同様の効果を有するこ
とはいうまでもない。In the above detailed description of the present invention, a method for manufacturing a so-called inverted staggered TPT structure in which a gate electrode, a gate insulator layer, a semiconductor layer, a source, and a drain electrode are formed in this order on a glass substrate has been described. drain electrode,
It goes without saying that a method for manufacturing a staggered structure in which a semiconductor layer, a gate insulator layer, and a gate electrode are formed in this order has similar effects.
発明の効果
以上述べてきたように、本発明はゲート、ソース、ドレ
インの各電極および透明表示電極となる導電体材料の少
なくとも一つをを印刷法により被着形成することにより
、製造工程においてフォトマスクを用いたフォトリソグ
ラフィの工程をを軽減できることから大型基板上に容易
にＴＦＴアレイを製造できる効果を有する。また、フォ
トリソグラフィの工程が削減できるとともに、導電体材
料の真空装置による蒸着工程を必要としないため、ＴＦ
Ｔアレイの製作コストを低減できる効果をも有する。Effects of the Invention As described above, the present invention uses a printing method to deposit at least one of the conductive materials that will become each of the gate, source, and drain electrodes and the transparent display electrode, thereby making it possible to use photosensitive materials in the manufacturing process. Since the photolithography process using a mask can be reduced, it has the effect of easily manufacturing a TFT array on a large substrate. In addition, the photolithography process can be reduced and there is no need for a vapor deposition process using a vacuum device for the conductive material.
It also has the effect of reducing the manufacturing cost of the T array.
第１図（ａ’）〜（ｄ）及び第３図（ａ） 〜（ｄ）−
ト電極、 ３．２３・・・ゲート絶縁体層、４．２４拳
・・半導体層、５ａ、２５ａ、３５・・・ソース、５ｂ
、２５ｂ争・争ドレイン電極、６．２６．３６・・・透
明表示電極、７・・・保護絶縁体層。
代理人の氏名 弁理士 粟野重孝 はか１名ＦＴプレイ
の要部構成断面図である。
１．２１・・・ガラス基板、２．２２争・・ゲ１％、１
図
第 ２図
５ａ 、 ５ｂ、−−ソース・ドしインミオ曇ン
篇
ン２
図
２］・・・ガラス葛引反
第
図
３５− ソース電才憂
３６−透明表示電極Figure 1 (a') to (d) and Figure 3 (a) to (d)-
3.23... Gate insulator layer, 4.24... Semiconductor layer, 5a, 25a, 35... Source, 5b
, 25b Drain electrode, 6.26.36... Transparent display electrode, 7... Protective insulator layer. Agent's name: Patent attorney Shigetaka Awano This is a cross-sectional diagram of the main parts of a one-person FT play. 1.21...Glass substrate, 2.22...Ge 1%, 1
Figure 2 Figure 2 5a, 5b, -- Source display electrode 2 Figure 2]...Glass tension Figure 35 - Source electrode 36 - Transparent display electrode
Claims (6)
形成する工程と、絶縁体層を被着形成する工程と、少な
くとも前記第１の導電体層の一部と重なるように半導体
層を被着形成する工程と、前記半導体層の一部と重なる
ように第２の導電体層を選択的に被着形成する工程とを
有し、前記第１の導電体層、第２の導電体層を形成する
工程の一方あるいは両方が印刷法により形成する工程で
あることを特徴とする半導体装置の製造方法。(1) A step of selectively depositing a first conductive layer on one main surface of the substrate, a step of depositing an insulating layer, and at least a part of the first conductive layer. the step of depositing and forming a semiconductor layer so as to overlap with the semiconductor layer; and the step of selectively depositing and forming a second conductor layer so as to overlap a part of the semiconductor layer; A method of manufacturing a semiconductor device, characterized in that one or both of the steps of forming the second conductive layer are formed by a printing method.
する請求項１記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is made of non-single crystal silicon.
選択的に被着形成する工程を有する請求項１記載の半導
体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of selectively depositing a second insulating layer so as to overlap a part of the semiconductor layer.
半導体層、前記絶縁体層の一方あるいは両方を所望の形
状に加工する工程を有する請求項１記載の半導体装置の
製造方法。4. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of processing one or both of the semiconductor layer and the insulator layer into a desired shape using the first conductor layer as a photomask.
記第２の導電体層と電気的に接続するように選択的に被
着形成する工程を有する請求項１記載の半導体装置の製
造方法。(5) The method for manufacturing a semiconductor device according to claim 1, further comprising the step of selectively depositing a transparent conductor to be a transparent display electrode so as to be electrically connected to the second conductor layer by a printing method. .
いは両方が透明導電体であることを特徴とする請求項１
記載の半導体装置の製造方法。(6) Claim 1 characterized in that one or both of the first conductor layer and the second conductor layer is a transparent conductor.
A method of manufacturing the semiconductor device described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29383488A JPH02139972A (en) | 1988-11-21 | 1988-11-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29383488A JPH02139972A (en) | 1988-11-21 | 1988-11-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02139972A true JPH02139972A (en) | 1990-05-29 |
Family
ID=17799762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29383488A Pending JPH02139972A (en) | 1988-11-21 | 1988-11-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02139972A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002071478A1 (en) * | 2001-03-02 | 2002-09-12 | Koninklijke Philips Electronics N.V. | Thin film transistors and method of manufacture |
| JP2002343970A (en) * | 2001-05-10 | 2002-11-29 | Koninkl Philips Electronics Nv | Method for manufacturing thin film transistor, thin film transistor manufactured by using the method, and liquid crystal display panel |
| JP2003505889A (en) * | 1999-07-21 | 2003-02-12 | イー−インク コーポレイション | Preferred method of fabricating electronic circuit elements for controlling an electronic display |
| JP2004241769A (en) * | 2003-01-17 | 2004-08-26 | Semiconductor Energy Lab Co Ltd | Method of framing resist pattern and method of manufacturing semiconductor device |
| JP2010192935A (en) * | 2003-01-17 | 2010-09-02 | Semiconductor Energy Lab Co Ltd | Method of manufacturing semiconductor device |
| US8053174B2 (en) | 2003-02-05 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for wiring |
-
1988
- 1988-11-21 JP JP29383488A patent/JPH02139972A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003505889A (en) * | 1999-07-21 | 2003-02-12 | イー−インク コーポレイション | Preferred method of fabricating electronic circuit elements for controlling an electronic display |
| JP4948726B2 (en) * | 1999-07-21 | 2012-06-06 | イー インク コーポレイション | Preferred method of making an electronic circuit element for controlling an electronic display |
| WO2002071478A1 (en) * | 2001-03-02 | 2002-09-12 | Koninklijke Philips Electronics N.V. | Thin film transistors and method of manufacture |
| JP2002343970A (en) * | 2001-05-10 | 2002-11-29 | Koninkl Philips Electronics Nv | Method for manufacturing thin film transistor, thin film transistor manufactured by using the method, and liquid crystal display panel |
| JP2004241769A (en) * | 2003-01-17 | 2004-08-26 | Semiconductor Energy Lab Co Ltd | Method of framing resist pattern and method of manufacturing semiconductor device |
| JP2010192935A (en) * | 2003-01-17 | 2010-09-02 | Semiconductor Energy Lab Co Ltd | Method of manufacturing semiconductor device |
| JP2010258473A (en) * | 2003-01-17 | 2010-11-11 | Semiconductor Energy Lab Co Ltd | Method of manufacturing semiconductor device |
| JP4656843B2 (en) * | 2003-01-17 | 2011-03-23 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4667532B2 (en) * | 2003-01-17 | 2011-04-13 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4667529B2 (en) * | 2003-01-17 | 2011-04-13 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| US8053174B2 (en) | 2003-02-05 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for wiring |
| US8460857B2 (en) | 2003-02-05 | 2013-06-11 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method for wiring |
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