JPH04235529A - Manufacture of wiring substrate - Google Patents

Manufacture of wiring substrate

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Publication number
JPH04235529A
JPH04235529A JP216791A JP216791A JPH04235529A JP H04235529 A JPH04235529 A JP H04235529A JP 216791 A JP216791 A JP 216791A JP 216791 A JP216791 A JP 216791A JP H04235529 A JPH04235529 A JP H04235529A
Authority
JP
Japan
Prior art keywords
resist
wiring
electrodes
exfoliation
base material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP216791A
Other languages
Japanese (ja)
Inventor
Yozo Yasukawa
安川 庸三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP216791A priority Critical patent/JPH04235529A/en
Publication of JPH04235529A publication Critical patent/JPH04235529A/en
Pending legal-status Critical Current

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  • Manufacturing Of Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Electric Cables (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE:To facilitate washing after exfoliation of a resist and reducing the dimension of a manufacturing device by facilitating the exfoliation of the resist after etching is carried out by using the positive type resist. CONSTITUTION:An ITO(indium tin oxide) film is formed on a substrate, and a positive type resist is applied. After the resist is heated-hardened, ultraviolet rays are radiated on the resist staying in other than in an electrode formation region, and after development, the ITO film is subjected to etching. Then, ultraviolet rays are radiated on the whole surface of the substrate, and after the resist covering the electrode is softened, the exfoliation of the resist is carried out by a resist exfoliation liquid, which is perfectly removed through washing.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、液晶表示素子の電極の
形成にかかわる配線基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a wiring board for forming electrodes of a liquid crystal display element.

【0002】0002

【従来の技術】図4は液晶表示素子1に用いられる帯状
の電極4,5を形成する従来の製造方法を示す工程図で
あり、図2は液晶表示素子1の断面図であり、従来例お
よび実施例において共通に参照する。工程a1では透光
性基板2,3上に電極4,5材料であるITO(インジ
ウム錫酸化物)膜が形成され、工程a2では前記ITO
膜上にポジ形のレジストが塗布される。工程a3では工
程a2で塗布されたレジストを加熱して硬化するプリベ
ークが行われ、工程a4では電極4,5形成領域部分以
外に露光が行われる。工程a5ではレジストに対して現
像が行われ、露光が行われた部分のレジストが、たとえ
ば1%NaOH溶液によって剥離される。その後、水洗
および乾燥が行われ、後述する工程a7のエッチングに
おいて電極4,5形成領域上のレジストの強度が不足す
る場合には、工程a6でさらに加熱してレジストを硬化
するポストベークが行われる。工程a7でITO膜のエ
ッチングが行われて電極4,5が形成され、工程a8で
は現像液より高濃度の溶液、たとえば現像に1%NaO
H溶液が用いられた場合には、3%NaOH溶液の剥離
液を用いて電極4,5上のレジストが剥離される。その
後、工程a9で、電極4,5が形成された基板2,3の
洗浄が行われる。
2. Description of the Related Art FIG. 4 is a process diagram showing a conventional manufacturing method for forming band-shaped electrodes 4 and 5 used in a liquid crystal display element 1, and FIG. 2 is a cross-sectional view of the liquid crystal display element 1. and are commonly referred to in the Examples. In step a1, an ITO (indium tin oxide) film, which is the material of electrodes 4 and 5, is formed on the transparent substrates 2 and 3, and in step a2, the ITO
A positive resist is applied onto the membrane. In step a3, pre-baking is performed to heat and harden the resist applied in step a2, and in step a4, areas other than the areas where the electrodes 4 and 5 are formed are exposed to light. In step a5, the resist is developed, and the exposed portions of the resist are peeled off using, for example, a 1% NaOH solution. After that, washing with water and drying are performed, and if the strength of the resist on the electrode 4, 5 formation area is insufficient in the etching in step a7 to be described later, a post-baking is performed in step a6 to further heat and harden the resist. . In step a7, the ITO film is etched to form electrodes 4 and 5, and in step a8, a solution with a higher concentration than the developer, for example 1% NaO, is used for development.
When a H solution is used, the resist on the electrodes 4 and 5 is stripped off using a stripping solution of 3% NaOH solution. Thereafter, in step a9, the substrates 2 and 3 on which the electrodes 4 and 5 are formed are cleaned.

【0003】0003

【発明が解決しようとする課題】前述の従来技術では、
電極4,5上のレジストを剥離する際に高濃度の剥離液
が用いられる。剥離液が基板2,3および電極4,5上
に残留すると、液晶表示素子1製造工程の次工程である
配向膜6,7の形成の際、配向膜6,7を均一に形成す
ることができなくなり、表示むらが生じて表示品位が低
下するという問題が生じる。この問題を解決するために
は、工程a9で行われる洗浄工程において、レジスト剥
離液を完全に除去することが必要である。このため、基
板2,3の洗浄にブラシを用いる、超音波を用いるなど
洗浄工程および製造装置が複雑になる。また、繰返し洗
浄を行わなければならないため、装置が大形化するなど
の問題がある。
[Problem to be solved by the invention] In the above-mentioned prior art,
A highly concentrated stripping solution is used when stripping off the resist on the electrodes 4 and 5. If the stripping solution remains on the substrates 2, 3 and the electrodes 4, 5, it may be difficult to form the alignment films 6, 7 uniformly during the formation of the alignment films 6, 7, which is the next step in the manufacturing process of the liquid crystal display element 1. This causes a problem in that display unevenness occurs and display quality deteriorates. In order to solve this problem, it is necessary to completely remove the resist stripping solution in the cleaning step performed in step a9. Therefore, the cleaning process and manufacturing equipment become complicated, such as using brushes or ultrasonic waves to clean the substrates 2 and 3. Furthermore, since repeated cleaning must be performed, there is a problem that the apparatus becomes larger.

【0004】本発明の目的は、配線上の被覆層の剥離を
容易にし、簡略化した製造方法にすることによって、装
置を小形化することができる配線基板の製造方法を提供
することである。
[0004] An object of the present invention is to provide a method for manufacturing a wiring board, which makes it possible to easily peel off the coating layer on the wiring and to simplify the manufacturing method, thereby making it possible to downsize the device.

【0005】[0005]

【課題を解決するための手段】本発明は、基材上に導電
体からなる配線を形成されて成る配線基板の製造方法に
おいて、下記A)ないしE)の工程を含むことを特徴と
する配線基板の製造方法である。
[Means for Solving the Problems] The present invention provides a method for manufacturing a wiring board in which wiring made of a conductor is formed on a base material, which includes the following steps A) to E). This is a method for manufacturing a substrate.

【0006】A)基材上に配線となる導電体層を形成し
、さらにその上に感光性材料から成る被覆層を塗布する
A) A conductive layer serving as wiring is formed on a base material, and a coating layer made of a photosensitive material is further applied thereon.

【0007】B)前記被覆層の配線となる領域以外の部
分を露光する。
B) Exposing a portion of the covering layer other than the area that will become the wiring.

【0008】C)前記被覆層を現像後、導電体層をエッ
チングして基材上に配線を形成する。
C) After developing the coating layer, the conductor layer is etched to form wiring on the base material.

【0009】D)前記基材を全面露光する。D) The entire surface of the base material is exposed to light.

【0010】E)配線上の被覆層を剥離する。E) Peel off the coating layer on the wiring.

【0011】[0011]

【作用】本発明に従えば、基材上に導電体からなる配線
を形成されて成る配線基板の製造方法として、まず基材
上に配線となる導電体層を形成して、その上に感光性材
料から成る被覆層を塗布する。次に前記被覆層の配線と
なる領域以外の部分を露光し、現像後、導電体層をエッ
チングして基材上に配線を形成する。その後、前記基材
を全面露光し、配線上の被覆層を剥離する。
[Operation] According to the present invention, as a method for manufacturing a wiring board in which wiring made of a conductor is formed on a base material, a conductive layer that will become the wiring is first formed on the base material, and then a photosensitive layer is formed on the conductive layer. Apply a covering layer of a synthetic material. Next, a portion of the covering layer other than the region that will become the wiring is exposed, and after development, the conductor layer is etched to form the wiring on the base material. Thereafter, the entire surface of the base material is exposed to light, and the coating layer on the wiring is peeled off.

【0012】0012

【実施例】図1は本発明の一実施例の液晶表示素子1に
用いられる帯状の電極4,5の形成工程を説明する工程
図であり、図2は帯状の電極4,5を用いた液晶表示素
子1の断面図である。一対の基材である透光性基板2,
3上に、図1で示される工程で形成される配線である帯
状の電極4,5が予め定める間隔を空けて形成されてい
る。その上に配向膜6,7が形成され、ラビング処理が
施されている。両基板2,3は電極4,5が直交するよ
うに向かい合わされ、シール材8によって貼合わせられ
た後、液晶9が注入されて液晶表示素子1が完成する。
[Example] FIG. 1 is a process diagram illustrating the process of forming band-shaped electrodes 4 and 5 used in a liquid crystal display element 1 according to an embodiment of the present invention, and FIG. 1 is a cross-sectional view of a liquid crystal display element 1. FIG. Translucent substrate 2, which is a pair of base materials;
Band-shaped electrodes 4 and 5, which are wiring formed in the process shown in FIG. 1, are formed on the electrode 3 at a predetermined interval. Alignment films 6 and 7 are formed thereon and subjected to a rubbing process. Both substrates 2 and 3 are faced to each other so that electrodes 4 and 5 are perpendicular to each other, and after being bonded together with a sealing material 8, liquid crystal 9 is injected to complete the liquid crystal display element 1.

【0013】図3は、本発明の一実施例の電極4,5の
製造工程を示す断面図である。
FIG. 3 is a sectional view showing the manufacturing process of electrodes 4 and 5 according to an embodiment of the present invention.

【0014】図1の工程b1では透光性基板2,3上に
導電体層であるITO(インジウム錫酸化物)膜10を
形成し、工程b2にて前記ITO膜10上に、被覆層で
ある、たとえばノボラック樹脂から成るポジ形のレジス
ト11を図3(1)に示すように塗布する。工程b3で
はレジスト11を加熱して硬化するプリベークが行われ
る。プリベークの条件としては、たとえばバッチ処理の
場合には80℃の温度で30分間処理を行い、連続処理
の場合には120℃の温度で2〜3分間処理を行う。
In step b1 of FIG. 1, an ITO (indium tin oxide) film 10, which is a conductive layer, is formed on the transparent substrates 2 and 3, and in step b2, a coating layer is formed on the ITO film 10. A positive resist 11 made of, for example, novolac resin is applied as shown in FIG. 3(1). In step b3, prebaking is performed to heat and harden the resist 11. As conditions for prebaking, for example, in the case of batch processing, processing is performed at a temperature of 80° C. for 30 minutes, and in the case of continuous processing, processing is performed at a temperature of 120° C. for 2 to 3 minutes.

【0015】工程b4では電極4,5形成領域以外の部
分に透孔12aを有するパターン12を介して紫外光に
よる露光が図3(2)に示すように行われる。この紫外
光は、たとえば波長が365nm、強度が120mJ/
cm2 で照射される。工程b5では現像が行われ、工
程b4で紫外光が照射された部分のレジスト11が現像
液によって剥離される。現像液としては、たとえば1%
NaOH溶液などが用いられる。工程b7においてIT
O膜10のエッチングが行われるけれども、電極4,5
領域上を覆っているレジスト11が、工程b7で用いら
れるエッチング液に対して強度が足りない場合には、工
程b6においてレジスト11を加熱硬化するポストベー
クが行われる。ポストベークの条件は、たとえばプリベ
ークに示される条件と同一である。
In step b4, exposure to ultraviolet light is performed through the pattern 12 having through holes 12a in areas other than the areas where the electrodes 4 and 5 are formed, as shown in FIG. 3(2). For example, this ultraviolet light has a wavelength of 365 nm and an intensity of 120 mJ/
irradiated at cm2. In step b5, development is performed, and in step b4, the portion of the resist 11 irradiated with ultraviolet light is removed by a developer. As a developer, for example, 1%
A NaOH solution or the like is used. In step b7, IT
Although the O film 10 is etched, the electrodes 4 and 5
If the resist 11 covering the area is not strong enough for the etching solution used in step b7, post-baking is performed to harden the resist 11 by heating in step b6. The conditions for post-bake are, for example, the same as those shown for pre-bake.

【0016】工程b7ではITO膜10がたとえば強酸
などによって図3(3)に示すように電極4,5状にエ
ッチングされる。工程b8では、電極4,5が形成され
た基板2,3が図3(4)に示すように紫外光によって
全面露光される。紫外光照射条件は、工程b4で行った
パターン露光と同一条件で行われるけれども、工程b6
でポストベークを行っているときには、レジスト11の
硬化に応じて紫外光の強度を上げるとよい。
In step b7, the ITO film 10 is etched using, for example, strong acid to form the electrodes 4 and 5 as shown in FIG. 3(3). In step b8, the entire surface of the substrates 2 and 3 on which the electrodes 4 and 5 are formed is exposed to ultraviolet light as shown in FIG. 3(4). Although the ultraviolet light irradiation conditions are the same as the pattern exposure performed in step b4, step b6
When post-baking is performed, the intensity of the ultraviolet light may be increased in accordance with the curing of the resist 11.

【0017】工程b9では図3(5)に示すようにレジ
スト11の剥離が行われる。レジスト11剥離条件は、
たとえば工程b5の現像条件と同一で行われる。工程b
10では洗浄が行われ、剥離液が除去される。
In step b9, the resist 11 is removed as shown in FIG. 3(5). The conditions for removing resist 11 are as follows:
For example, the developing conditions are the same as those in step b5. Process b
In step 10, cleaning is performed to remove the stripping liquid.

【0018】以上のように本実施例によれば、電極4,
5上に形成されているレジスト11の除去に高濃度の剥
離液を用いる必要がない。これによって、従来技術で用
いている剥離液を希薄して用いることができるため、剥
離液の使用量を減少することができる。低濃度の剥離液
を用いるため、剥離液除去のための洗浄を容易に行うこ
とができる。たとえば従来技術では4段のシャワーを用
いていたけれども、本実施例では3段のシャワーを用い
ることによって剥離液を除去することができる。したが
って、製造装置を小形化することができる。また、従来
技術で行っていたブラシ洗浄および超音波洗浄などを行
うことなく剥離液の除去を行うことができるため、さら
に製造装置の小形化を行うことができる。ブラシ洗浄や
超音波洗浄を行う場合には、洗浄時間を短縮することが
できるため、製造時間を短縮することができる。また、
本実施例によれば、従来技術に比べてより確実な洗浄を
行うことができるという効果も得られた。
As described above, according to this embodiment, the electrodes 4,
There is no need to use a highly concentrated stripping solution to remove the resist 11 formed on the resist 5. As a result, the stripping solution used in the prior art can be diluted and the amount of stripping solution used can be reduced. Since a low concentration stripping solution is used, cleaning for removing the stripping solution can be easily performed. For example, in the prior art, four stages of showers were used, but in this embodiment, the stripping liquid can be removed by using three stages of showers. Therefore, the manufacturing apparatus can be downsized. Further, since the stripping liquid can be removed without performing brush cleaning, ultrasonic cleaning, etc., which were performed in the prior art, it is possible to further downsize the manufacturing apparatus. When performing brush cleaning or ultrasonic cleaning, the cleaning time can be shortened, so the manufacturing time can be shortened. Also,
According to this embodiment, an effect was also obtained in that cleaning could be performed more reliably than in the prior art.

【0019】したがって、配線上の被覆層の剥離を容易
にし、簡略化された製造方法を用いて製造装置を小形化
することができる。
[0019] Therefore, the coating layer on the wiring can be easily peeled off, and the manufacturing apparatus can be downsized using a simplified manufacturing method.

【0020】本実施例においては、レジスト11に対し
て、紫外光の照射を行うことによってレジスト11の剥
離を容易にしたけれども、紫外光に限定されるものでは
なく、使用するレジスト11に応じて赤外光または可視
光などの照射を行ってもよい。
In this example, the resist 11 was easily peeled off by irradiating the resist 11 with ultraviolet light; however, the method is not limited to ultraviolet light, and may vary depending on the resist 11 used. Irradiation with infrared light or visible light may also be performed.

【0021】また、本実施例では配線として液晶表示素
子1の帯状の電極4,5について説明したが、形状は帯
状に限られるわけではなく、また、液晶表示素子以外の
配線についても同様に用いることができる。また、電極
4,5の材料としてITOをあげたけれども、これに限
られるものではない。
Further, in this embodiment, the strip-shaped electrodes 4 and 5 of the liquid crystal display element 1 have been described as the wiring, but the shape is not limited to the strip-shaped one, and the wires can be similarly used for wiring other than the liquid crystal display element. be able to. Furthermore, although ITO is used as the material for the electrodes 4 and 5, it is not limited to this.

【0022】[0022]

【発明の効果】本発明によれば、導電体層をエッチング
して配線を形成した後、基材を全面露光して、配線上を
覆っている被覆膜の露光を行う。このため、配線上の被
覆膜の剥離が容易になり、配線基板の製造方法が簡略化
され、製造装置を小形化することができる。
According to the present invention, after the conductor layer is etched to form wiring, the entire surface of the base material is exposed to light, and the coating film covering the wiring is exposed. Therefore, the coating film on the wiring can be easily peeled off, the method for manufacturing the wiring board can be simplified, and the manufacturing apparatus can be downsized.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例の液晶表示素子1に用いられ
る帯状の電極4,5の形成時の工程を説明する工程図で
ある。
FIG. 1 is a process diagram illustrating steps for forming band-shaped electrodes 4 and 5 used in a liquid crystal display element 1 according to an embodiment of the present invention.

【図2】帯状の電極4,5を用いた液晶表示素子1の断
面図である。
FIG. 2 is a cross-sectional view of a liquid crystal display element 1 using band-shaped electrodes 4 and 5. FIG.

【図3】本発明の一実施例の電極4,5の製造工程を示
す断面図である。
FIG. 3 is a cross-sectional view showing the manufacturing process of electrodes 4 and 5 according to an embodiment of the present invention.

【図4】液晶表示素子1に用いられる帯状の電極4,5
を形成する従来の製造方法を示す工程図である。
[Fig. 4] Strip-shaped electrodes 4 and 5 used in the liquid crystal display element 1
1 is a process diagram showing a conventional manufacturing method for forming a

【符号の説明】[Explanation of symbols]

2,3  基板 4,5  電極 10  ITO膜 11  レジスト 2, 3 Board 4,5 Electrode 10 ITO film 11 Resist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  基材上に導電体からなる配線を形成さ
れて成る配線基板の製造方法において、下記A)ないし
E)の工程を含むことを特徴とする配線基板の製造方法
。 A)基材上に配線となる導電体層を形成し、さらにその
上に感光性材料から成る被覆層を塗布する。 B)前記被覆層の配線となる領域以外の部分を露光する
。 C)前記被覆層を現像後、導電体層をエッチングして基
材上に配線を形成する。 D)前記基材を全面露光する。 E)配線上の被覆層を剥離する。
1. A method for manufacturing a wiring board comprising wiring made of a conductor formed on a base material, the method comprising the following steps A) to E). A) A conductive layer serving as wiring is formed on a base material, and a coating layer made of a photosensitive material is further applied thereon. B) Exposing a portion of the covering layer other than the area that will become the wiring. C) After developing the coating layer, the conductor layer is etched to form wiring on the base material. D) The entire surface of the base material is exposed. E) Peel off the coating layer on the wiring.
JP216791A 1991-01-11 1991-01-11 Manufacture of wiring substrate Pending JPH04235529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP216791A JPH04235529A (en) 1991-01-11 1991-01-11 Manufacture of wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP216791A JPH04235529A (en) 1991-01-11 1991-01-11 Manufacture of wiring substrate

Publications (1)

Publication Number Publication Date
JPH04235529A true JPH04235529A (en) 1992-08-24

Family

ID=11521809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP216791A Pending JPH04235529A (en) 1991-01-11 1991-01-11 Manufacture of wiring substrate

Country Status (1)

Country Link
JP (1) JPH04235529A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003086638A (en) * 2001-09-13 2003-03-20 Hitachi Cable Ltd Method for manufacturing tape carrier for semiconductor device
JP2018053276A (en) * 2016-09-26 2018-04-05 富士フイルム株式会社 Method for producing perforated metal substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003086638A (en) * 2001-09-13 2003-03-20 Hitachi Cable Ltd Method for manufacturing tape carrier for semiconductor device
JP2018053276A (en) * 2016-09-26 2018-04-05 富士フイルム株式会社 Method for producing perforated metal substrate

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