JPS63133541A - Bondingless ic chip packaging method - Google Patents
Bondingless ic chip packaging methodInfo
- Publication number
- JPS63133541A JPS63133541A JP61281217A JP28121786A JPS63133541A JP S63133541 A JPS63133541 A JP S63133541A JP 61281217 A JP61281217 A JP 61281217A JP 28121786 A JP28121786 A JP 28121786A JP S63133541 A JPS63133541 A JP S63133541A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- package
- contact terminal
- cap
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000012858 packaging process Methods 0.000 abstract 3
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 239000003292 glue Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L2224/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
- H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ICチップの実装技術に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC chip mounting technique.
第3図、第4図は、従来のICチップ実装方法の2つの
例の断面図であり、図において、(1)はICチップ、
(2)はICチップ(1)を収納するパッケージ、(3
)はICチップ(1)を密閉するキャップ、(4)はパ
ッケージ(2)のIC搭載面にメッキされた金属膜、(
5)はICチップ(1)の表面外周に作られている接続
用パッド、(6)はリードワイア、(7)はリードワイ
ア(6)を接続するためのパッケージ(2)にメッキさ
れた金属膜、(8)はICチップ(1)の表面に作られ
ている信号取り出し用のバンプ、(9)はバンプ(8)
を接続するためのパッケージ(2)にメッキされた金属
膜、口1はICチップ(1)固定用の弾性体、(ロ)は
パッケージ(2)の外に信号を導く配線である。3 and 4 are cross-sectional views of two examples of conventional IC chip mounting methods. In the figures, (1) is an IC chip;
(2) is a package that stores the IC chip (1);
) is a cap that seals the IC chip (1), (4) is a metal film plated on the IC mounting surface of the package (2), (
5) is a connection pad made on the outer periphery of the surface of the IC chip (1), (6) is a lead wire, (7) is a metal film plated on the package (2) for connecting the lead wire (6), (8) is a bump for signal extraction made on the surface of IC chip (1), (9) is bump (8)
The opening 1 is an elastic body for fixing the IC chip (1), and (b) is a wiring for guiding signals outside the package (2).
次に実装方法について説明する。まず第3図の例につい
てであるが、ICチップ搭載面にメッキされた金属膜(
4)に、ICチップ(1)を接着し、固定するダイボン
ド工程を行う。次いで、接続パッド(5)と、金属膜(
7)との間をリードワイア(6)で接続するワイアポン
ド行程を行う。そして、キャップ(3)をパッケージ(
2)に接着し、ICチップ(1)を密閉する0
次に第4図の例についてであるが、ICチップ(1)の
表面に、信号取り出し用のバンプ(8)を形成する。次
いで、ICチップ(1)をパッケージ(2)に置き、I
Cチップ(1)の裏面に弾性体α〔を入れ、キャップ(
3)を、パッケージ(2)に接着し、ICチップ(1)
を固定、密閉する。Next, the implementation method will be explained. First, regarding the example in Figure 3, the metal film plated on the IC chip mounting surface (
4) A die bonding process is performed to bond and fix the IC chip (1). Next, a connection pad (5) and a metal film (
7) and perform a wire pounding process to connect with the lead wire (6). Then, package the cap (3) (
2) to seal the IC chip (1) Next, referring to the example shown in FIG. 4, bumps (8) for signal extraction are formed on the surface of the IC chip (1). Next, place the IC chip (1) in the package (2), and place the IC chip (1) in the package (2).
Put the elastic body α on the back side of the C chip (1), and put the cap (
3) to the package (2), and the IC chip (1)
Fix and seal.
従来のICチップ実装方法は、以上のように構成されて
いるので、第3図の例の場合、ダイボンド、ワイアボン
ド2つの工程が必要であり、さらに、ダイボンドの位置
決め精度がワイアボンドの良否に影響するなどの問題点
があった。また第4図の例の場合、ICチップ表面に、
信号取り出し用の特別なバンプを作る必要があり、さら
に、バンプの高さを一定にしておかないと、ICチップ
裏面からの圧力で、工0チップが割れてしまうなどの問
題点があった。Since the conventional IC chip mounting method is configured as described above, in the case of the example shown in Fig. 3, two processes are required: die bonding and wire bonding, and furthermore, the positioning accuracy of die bonding affects the quality of wire bonding. There were problems such as: In addition, in the case of the example shown in Figure 4, on the IC chip surface,
It was necessary to create a special bump for signal extraction, and if the height of the bump was not kept constant, there were problems such as the chip being cracked by pressure from the back of the IC chip.
この発明は、上記のような問題点を解消するためになさ
れたもので、ICチップ実装工程を短縮できるとともに
、ICチップに特別な加工を必要としない実装方法を得
ることを目的とする。The present invention was made to solve the above-mentioned problems, and aims to provide a mounting method that can shorten the IC chip mounting process and does not require special processing of the IC chip.
この発明に係るICチップ実装方法は、パッケージのI
Cチップ搭載面から接触端子を突出させ、この接触端子
にICチップ表面外周に設けられた接続パッドを接触さ
せるとともに、接触端子とパッドは、接触せずに、IC
チップ裏面と、キャップの間に挿入した弾性体又は、プ
ローブ自体の弾性により、ICチップを固定するように
したものである。The IC chip mounting method according to the present invention includes
A contact terminal is made to protrude from the C chip mounting surface, and a connection pad provided on the outer periphery of the IC chip surface is brought into contact with this contact terminal.
The IC chip is fixed by an elastic body inserted between the back surface of the chip and the cap, or by the elasticity of the probe itself.
この発明における実装方法を用いることにより、ICチ
ップの実装工程は、パッケージのICチップ搭載面にI
Cチップを置き、キャップするだけとなり、従来の実装
工程に比べ大幅な、工程短縮を計ることができる。By using the mounting method of the present invention, the IC chip mounting process can be performed by placing an I/O on the IC chip mounting surface of the package.
By simply placing the C chip and capping it, the process can be significantly shortened compared to the conventional mounting process.
以下、この発明の一実施例を図について説明する。第1
図において、(2)はパッケージ(2)にうめこまれた
接触端子で6シ、パッケージ(2)の中で、配線αηと
接続されている0さらに接触端子(6)は、ICチップ
(1)の接続パッド(5)と接触している。ICチップ
(11は、弾性体a1と、キャップ(3)によシ、接触
端子(6)に圧着、固定されている。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (2) is a contact terminal embedded in the package (2), and the contact terminal (6) is connected to the wiring αη in the package (2). is in contact with the connection pad (5) of. The IC chip (11) is crimped and fixed to the contact terminal (6) through the elastic body a1 and the cap (3).
次に実装工程について説明する。まず、パッケージ(2
)内1c、ICチップ(1)を置き、弾性体(IQをそ
の上に置きキャップ(3)を、パッケージ(2)に接着
する。以上の工程で実装が完了する。またこの方法で実
装する時に要求される精度は、パッケージ(2)にうめ
こまれた接触端子(2)に対する、ICチップ(1)の
位置決め精度だけである。パッケージ(2)内にうめこ
まれた接触端子(6)の位置精度は、パッケージ製造時
における精度でアシ、実装時における精度とは完全に分
離が可能で、実装工程における分留まシは、向上する。Next, the mounting process will be explained. First, package (2
), place the IC chip (1), place the elastic body (IQ) on top of it, and glue the cap (3) to the package (2). Mounting is completed with the above steps. Also, use this method for mounting. Sometimes the only accuracy required is the positioning accuracy of the IC chip (1) with respect to the contact terminals (2) embedded in the package (2).The positioning accuracy of the contact terminals (6) embedded in the package (2) Accuracy is the accuracy at the time of package manufacturing, and can be completely separated from the accuracy at the time of mounting, and the accuracy in the mounting process is improved.
なお、上記実施例では、ICチップを固定するために弾
性体ellをICチップ(1)と、キャップ(3)の間
に挿入したものを示したが、接触端子自体を弾性体とし
て使用してもよい。第2図に、接触端子(2)を、5字
形に曲げ、バネとし、弾性体とした例を示す。In addition, in the above embodiment, an elastic body ELL was inserted between the IC chip (1) and the cap (3) to fix the IC chip, but it is also possible to use the contact terminal itself as the elastic body. Good too. FIG. 2 shows an example in which the contact terminal (2) is bent into a 5-shape to form a spring and is made into an elastic body.
また、接触端子とICチップの接続パッドを接着してい
ないことから、中ヤツプを脱着式にすれば、ICチップ
の交換も可能となる。Furthermore, since the contact terminals and the connection pads of the IC chip are not bonded, the IC chip can be replaced by making the inner cap removable.
以上のように、この発明によれば、IC,チップ実装方
法を、グイボンドレス、ワイアボンドレスにしたので、
装置が安価にでき、また、実装工程が短縮できる効果が
ある。As described above, according to the present invention, since the IC and chip mounting methods are Guibondress and Wirebonddress,
This has the effect of making the device inexpensive and shortening the mounting process.
第1図はこの発明の一実施例によるICチップ実装方法
を示す断面何面図、第2図はこの発明の他の実施例((
よる工0チップ実装方法を示す断面側面図、第3図、第
4図は従来のICチップ実装方法を示す断面側面図であ
る。
図において、(1)はICチップ、(2)はパッケージ
、(3)はキャップ、(4)は金属膜、(5)は接続パ
ッド、(6)はリードワイア、(7)は金属膜、(8)
はバンプ、(9)は金属膜、Qlは弾性体、(6)は配
線、(2)は接触端子でめる。
なお図中、同一符号は同一、又は相当部分を示す0FIG. 1 is a cross-sectional view showing an IC chip mounting method according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view showing another embodiment of the present invention ((
FIGS. 3 and 4 are cross-sectional side views showing a conventional IC chip mounting method. In the figure, (1) is an IC chip, (2) is a package, (3) is a cap, (4) is a metal film, (5) is a connection pad, (6) is a lead wire, (7) is a metal film, ( 8)
is a bump, (9) is a metal film, Ql is an elastic body, (6) is a wiring, and (2) is a contact terminal. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
接触端子を突出させ、この接触端子にICチップの接続
用パッドを接触させ接触端子に接続された線によつてパ
ッケージの外部へ入出力信号を導き、ICチップとパッ
ケージの間に挿入した弾性体によりICチップを接触端
子に押え付け又は、接触端子自体の弾性によりICチッ
プをパッケージに押え付けて固定することを特徴とする
ボンディングレスICチップ実装方法。A contact terminal is protruded from the chip mounting surface of a package housing an IC chip, a connecting pad of the IC chip is brought into contact with the contact terminal, and an input/output signal is guided to the outside of the package through a wire connected to the contact terminal. A bondingless IC chip mounting method characterized in that the IC chip is pressed against a contact terminal by an elastic body inserted between the IC chip and the package, or the IC chip is pressed and fixed to the package by the elasticity of the contact terminal itself.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61281217A JPS63133541A (en) | 1986-11-25 | 1986-11-25 | Bondingless ic chip packaging method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61281217A JPS63133541A (en) | 1986-11-25 | 1986-11-25 | Bondingless ic chip packaging method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63133541A true JPS63133541A (en) | 1988-06-06 |
Family
ID=17635995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61281217A Pending JPS63133541A (en) | 1986-11-25 | 1986-11-25 | Bondingless ic chip packaging method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63133541A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002088017A1 (en) * | 2001-04-26 | 2002-11-07 | Advantest Corporation | Connection member, microswitch, method for manufacturing connection member, and method for manufacturing microwitch |
JP2021097100A (en) * | 2019-12-16 | 2021-06-24 | 株式会社東芝 | Electronic device |
-
1986
- 1986-11-25 JP JP61281217A patent/JPS63133541A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002088017A1 (en) * | 2001-04-26 | 2002-11-07 | Advantest Corporation | Connection member, microswitch, method for manufacturing connection member, and method for manufacturing microwitch |
US6903637B2 (en) | 2001-04-26 | 2005-06-07 | Advantest Corporation | Connecting member, a micro-switch, a method for manufacturing a connecting member, and a method for manufacturing a micro-switch |
JP2021097100A (en) * | 2019-12-16 | 2021-06-24 | 株式会社東芝 | Electronic device |
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