JPS63132483A - Junction-gate field-effect transistor and manufacture of same - Google Patents

Abstract

PURPOSE:To keep fluctuation of the threshold voltage small even if the gate length is made short by forming the junction depth of the gate region in the end parts of the channel region larger than the depth in the central part of the channel region. CONSTITUTION:For the existence of a parasitic channel region 13, an effective n-type channel region 4 is usually formed more deeply in the end parts as compared with the central part of the channel region 4. And, according to its shape, the junction depth with a gate region 5 in the end parts of the channel region 4 is formed more deeply as compared with that in the central part. Therefore, the actual channel thickness increases little, and the depletion layer can be widened by an ordinary threshold voltage, enabling the current to be pinched off.

Description

[Detailed Description of the Invention] [Summary] In order to suppress the dependence of a certain force value voltage on the gate length, the depth of contact with the gate region at the end of the channel region is changed from that at the center of the channel region. It is something that is formed more deeply.

[Industrial application field]

The present invention relates to a semiconductor device, particularly the structure of a junction gate field effect transistor (JFETI) and its manufacturing method.

[Conventional technology]

Conventional JPET will be explained in Figure 4 with reference to an example of its manufacturing method. FIG. 4 is a cross-sectional view showing a conventional method for manufacturing an n-channel JFET in order of steps.

In this example, first, as shown in FIG. 4 (2), for example, a diffusion mask 1
0, and by implanting Si ions through the diffusion window 10a, an n shadow region 4a is formed. After that, a higher concentration of Si
Source region tJ of nfJl by implanting ions
I12 and drain groove 3 are formed.

Next is AI (not shown)! A N (aluminum nitride) film is formed over the entire surface and annealed.

Next, as shown in Figure 4 (0), after forming the StO film 9 on the entire surface, a window is made in the area that will become the gate region 5 in the future.
Next, after a WSix (tungsten silicide) film 11 doped with, for example, Mg (magnenium) is formed on the entire surface, heat treatment is performed to diffuse Mg in the WSix film 11 and form a gate M5.

Next, after patterning the WSix film 11 in the form of an island, contact windows are formed on the source region 2 and drain region 113 (1) Siol'd 9, and then on the surface, for example, Forming an electrode material made of AI,
By performing this patterning, the gate 1, the pole 6, the source electrode 7, and the drain electrode 8 are formed.

[Problem that the invention seeks to solve]

JFET's driving force, transfer conductance, gn], and is usually a.

Here, Wg: gate width, a: channel thickness η, Lg: gate, e〆: constant Vcs: gate-source voltage Vth: L threshold voltage. In other words, gm is proportional to the gate width Wg,
The channel thickness a is inversely proportional to the gate length Lg.

In order to improve the driving ability of the JFET, it is necessary to increase gm, but increasing the gate width Wg is disadvantageous because it increases the device area. This is also disadvantageous since the reverse breakdown voltage decreases.

As a result of the above, in order to rationally improve gmk, it is most desirable to shorten the gate length Lg. However, in actual JFETs, as shown in Figure 5 (2), 2 and the drain @t2113, the carriers move into the type 1 GaAs substrate 1, so that a raw channel @t213 is formed in the type 1 GaAs substrate 1 at both ends of the channel region. As shown in Figure IBI, when the gate region 5 is shortened to create a short channel, the parasitic channel region 13 is formed at a position corresponding to the effective channel region, and the effective channel thickness is accordingly reduced. As a result, the so-called short gate effect appears, in which the threshold t'k flf voltage shifts to the negative side.

Figure 81I6 shows typical data regarding the short gate effect. As shown in the figure, if the gate length is set and formed around Lg'frl (μm) in order to increase the speed of the device, the threshold voltage vth will vary greatly due to minute variations in the processing. It had some problems.

[Means for solving problems]

In view of the above-mentioned problems, the present invention provides a vt due to short gate effect.
In order to suppress the shift of h, the effective n-type channel region 4 due to the presence of the W raw channel @#12 is normally shifted to the center of the channel region 4 as shown in the figure. According to the present invention, the depth of the junction with the gate region 5 at the end of the channel region 4 is formed deeper than that at the center according to the shape. Therefore, the actual channel thickness hardly increases, and the normal threshold voltage sufficiently reduces the depletion IIi#
can be expanded and the current can be pinched off.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to Figure 2. This embodiment is an n-channel type JPET, and FIG. 2 shows it in step 11! FIG.

In this example, first, Si ions were implanted using a quasi-2 diagram (al) type conduction with an acceleration energy of 120 (key) and a tones amount of 2X 10'' (cm). An n-type region 4a is formed by the following steps.

After a while, as shown in FIG. 2B, a new sales promotion mask 12 made of, for example, resist is formed in the part that will become the channel region 4 in the future, and then Si ions are further heated, for example, at an acceleration energy of 1.
75 (kev), dose lid is 2X ] 013 (cm
) by implanting source region 2, drain/
Forming Region 3 In this case, a parasitic channel region 13 is formed by carriers moving into the GaAs substrate from the source region 2 and drain cutout 3 .

Next, the diffusion mask IQ, the trowel from which '12'fr was removed, and the entire surface covered with klN (aluminum nitride) S, not shown.
is formed, and then annealed for 15 minutes at, for example, 750'0, using it as a cover.

Next, after removing the A4N film, gloss 2 (as shown in 0, for example, CV
5i01 embryo 9 is formed by D+>.

Next, as shown in Figure 2 (n), there are gates @ti that will be formed in the future.
S10. on the area that is the center of jJt15. After forming the diffusion window 9a in the leg 9, for example, incoming S (nitrogen) ions are
A gate diffusion suppressing region 14 is formed by implanting at 0'4 (Crn-''). Next, using an etching mask (not shown), plasma etching is performed, for example, to form a gate diffusion region 14. After widening the diffusion window 9a by about 1000 (A), a WSix (tungsten-silicide) film doped with λ4g (magnesium) is formed on the entire surface by sputtering I, for example, to a thickness of about 20001). .

Next, as shown in Figure 2 (■), heat treatment is performed at 900° C. for 6 seconds using, for example, a rapid heating method using an infrared lamp, so that Mg diffuses into the k channel region 4 in the WSix film 11 and forms the gate region 5. Form.

In this case, since the region where the suppression region J3 is formed has a smaller Mg diffusion coefficient than other regions, the junction depth at the center of the formed gate region is smaller than that at the ends. formed shallower than the

(In this example, the center part...0.3 (μmL end part...0
6 (μm)).

Next, as shown in Figure 2 (D), a %WS ix film 11 is patterned on the entire surface using, for example, Ti (titanium) and Au.
The gate electrode 6 is formed by vapor-depositing an electrode material made of gold (C gold) and performing Butter/Jung processing. Form a contact window in 9 with butter/
By performing Jung, source electrode 7, drain/1
1 to form the pole 8.

Threshold voltage Vth- of the JFET formed as a result of the above
The gate length Lg characteristics are shown in Figure 3. As shown in the figure, the gate length Lg of the JFET of this example is set to around 1 (μm),
Even in the case where the gate length Lg is formed, fluctuations in the threshold voltage vth due to variations in the gate length Lg can be kept low, and a highly reliable J FET can be obtained.

〔Effect of the invention〕

In the JFET of the present invention, fluctuations in the force value voltage vth can be kept low even when the gate length Lg is shortened, so that a small, high-speed, and highly reliable JPET integrated circuit element can be obtained.

The detailed explanation diagram of the present invention, the third diagram, is an example of JFETI.
)Vth-Lg characteristic t Figure 4 shows the conventional JF
FIG. 5 is a diagram explaining the problems of the conventional JPET, and FIG. 6 is a diagram showing the Vth-Lg% properties of the conventional JFET. In the figure, 1 is based on GaAs, 2 is the source region, 3 is the drain region, 4 is the channel region, and 4a
is an n-type region, 5 is a gate region, 6 is a gate electrode, 7 is a source electrode, 8 is a drain/polar electrode, 9ijStag p, 9
a+ 10a is a diffusion window, 10.12 is a diffusion mask,
11 WSix membrane, 131-t'#F raw channel region,
14 is a suppression area.

Engraving of the drawing (no changes to the content) I bar? Zusaro JFET's Shōgo, Mashi 1 Kogyo 8 Kenito-bLy (, Mez-cho i ni shi>) Snore Hi A! 13 JFl Mi T /) Vth-
L≦〆 4) Name to ζ 3 Gap plate floor J/: ET θ process bihan 4 Pi (, 4) Warabi JFET opening 1 [6, 'g 5 Σ Gate length g <, um > Lumi pot JFETf） Relationship with the case of the person who made the third amendment Patent applicant address: 1015 Niodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture
522) Name Fujitsu Limited

Claims (1)

[Claims] 1. A semi-insulating compound semiconductor substrate is provided with a high concentration source region and a drain region of one conductivity type, the source region and
A channel region of one conductivity type is provided between the drain regions;
In a junction gate field effect transistor in which a gate region of an opposite conductivity type is provided in the channel region, the depth at the end of the gate region is deeper than the depth at the center of the gate region. A junction gate field effect transistor characterized by: 2. A process of introducing impurities of one conductivity type into a semi-insulating compound semiconductor substrate to form a channel region, and introducing high concentration impurities of one conductivity type into both ends of the channel region to form a source region and a drain region. A step of forming a suppression region by introducing an element constituting the substrate into the center of a gate region to be formed in the future through a mask formed on the surface of the substrate; Manufacturing a junction gate field effect transistor, comprising the step of widening an opening and introducing an impurity of a conductivity type opposite to that of the channel region through the opening to form a gate region. Method.