JPS63127380A - Bit map depicting device - Google Patents

Abstract

PURPOSE:To perform the transfer of data between planes at high speed, by providing two memory address generators provided with data buses used for the transfer of a memory data and which designate an area in a source or a destination plane to one of two address buses. CONSTITUTION:Plural bit map memory planes 30-i are connected to a memory bus 50. The multiplexer(MUX)32 of the plane 30-i selects the address buses 52a and 52b, and the MUX33 selects control buses 53a and 53b. A computing element ALU35 inputs an input data from a data bus 51 and a readout data from a memory block 31, and outputs them to the bus 51 via a register 36. The address generator 62 generates the address of the area designated as the source plane out of the planes 30-i, and the address generator 63 generates the address of the area designated as the destination plane out of the planes 30-i. The generators 62 and 63 are connected to the bus 52a or 52b selectively by the indication of a control processor, and thereby, the data can be transferred at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a bitmap drawing device having a plurality of bitmap memory planes.

(Prior Art) In a bitmap drawing device using a bitmap memory, such as a bitmap display device, conventionally, as shown in FIG.
1-n memory buses 12 are connected to one data bus 13,
It consisted of one address bus 14 and one control bus 15. In a bitmap drawing device with such a configuration, even if it has a plurality of memory brains 11-1 to 11-n, it is common that only one memory brain can operate within one memory cycle. there were. Further, even if a plurality of memory brains were allowed to operate, all of these memory brains could only perform the same memory operation (memory write operation) within one memory cycle. That is, for example, memory brain 1
During memory read operation, memory brain 11-1
2 could not perform a memory write (read-modify-write) operation. Therefore, assuming that memory brain 11-1 is a character font registration brain and memory brain 11-2 is a display brain, copying character fonts from memory brain 11-1 to memory brain 11-2 (between brains) In the case of copying), one copy (one word) involves a memory read cycle in which a memory read operation is performed using memory brain 11-1 as a source plane, and memory brain 11-2 as shown in FIG. This was a problem because it required two memory cycles for a memory write operation to be performed with the memory plane as the destination plane.

(Problems to be Solved by the Invention) As mentioned above, in conventional bitmap drawing devices, the source plane and destination plane cannot operate in the same memory cycle, so inter-brane data transfer is required for copying between memory brains, etc. There was a problem that the speed could not be increased.

This invention was made in view of the above circumstances, and its purpose is to enable the source plane and destination plane to operate in the same memory cycle, thereby achieving high speed data transfer between brains, which is necessary for copying between memory brains, etc. The object of the present invention is to provide a bitmap drawing device that can be used to draw bitmaps.

[Structure of the invention] (Means and effects for solving the problem) In this invention,
There are two address buses and two control buses for the memory bus.
Books (2 types) will be prepared. A plurality of bitmap memory planes connected to this memory bus include a first multiplexer for switching between two address buses, a second multiplexer for switching between two control buses, and a first multiplexer for switching between two address buses, a second multiplexer for switching between two control buses, and A flip-flop that controls two multiplexers, a memory block that is addressed according to the outputs of the first and second multiplexers, and a pipeline register that temporarily holds read data from this memory block and outputs it to the data bus. , respectively. Further, in the present invention, there is provided a main control means for selecting and specifying a source and destination plane from the plurality of bitmap memory planes, and a memory data control means for controlling data transfer between the memory planes selected and specified by the main control means. The transfer control circuit includes a first address generator that generates a memory address specifying an area in the source plane on one of the two address buses, and a destination plane on one of the two address buses. and a memory data transfer control circuit having a second address generator that generates a memory address specifying the inner area. According to the above configuration, one of the two address buses and two control buses is used to perform a memory read operation of the source plane, while the other is used to perform a memory write (read modify write) operation of the destination plane. can be done.

(Embodiment) FIG. 1 shows a block configuration of a bitmap drawing device according to an embodiment of the present invention. In the figure, 21 is a control processor that controls the entire device, and 22 is a control processor 2.
1 is a system bus, and 23 is a host interface which is a communication interface with a host computer (not shown). 30-1゜30-1...30-n are bitmap memory planes (hereinafter simply referred to as memory planes) used for storing display images, kanji, symbols, etc.; 41 is a display monitor; 42 is a display control circuit that performs display control for displaying the contents of the memory planes 30-1 to 30-n on the display monitor 41.

50 is a memory bus for the memory planes 30-1 to 30-n, and 60 is a memory bus for the control processor 21 to connect to the memory plane 3o-1.
This is a memory data transfer control circuit that performs control for accessing the memory planes 30-1 to 30-n, data transfer control between the memory planes 30-1 to 30-0, and the like. The memory bus 5o includes one data bus 51 (one system) used for transferring memory data, two address buses 52a and 52b used for transferring memory addresses, and a read request signal and a write (read) bus 51. two control buses 53a used for transferring various memory control signals such as (modify write) request signals;
53b.

FIG. 2 shows the memory plane 30-i (i −1
.

2...n), and 31 is a memory block having a RAM configuration, for example. 32 is a multiplexer (which selects one of the address buses 52a and 52b as the address bus for the memory block 31);
(hereinafter referred to as MLJX), 33 is a MUX (multiplexer) that selects which of the control buses 53a or 53b is the control bus for the memory block 31, and 34 is a flip 7 that outputs a selection control signal for MUXs 32 and 33.
0 tube (hereinafter referred to as F/F). This F/
F 34 is operated (set/reset) by control processor 21 via system bus 22 of FIG. In addition, the outputs of MUX 32 and 33 are the respective address input ports (ADD) of memory block 31.
RESS>, is connected to the grave signal input port (CONTROL). 35 is an arithmetic unit (hereinafter referred to as ALU) which takes input data from the data bus 51 as one input and read data from the memory block 31 as the other input, and 36 temporarily latches the read data from the memory block 31. This is the pipeline register (R). A
The output of L U 35 is connected to the data input/output port (DATA) of memory block 31 , and the output of register 36 is connected to data bus 51 .

FIG. 3 shows a block configuration of the memory data transfer control circuit 60 shown in FIG.
This is a transfer control circuit that controls data transfer of ~3O-nIIl. 62 is a memory plane 30-1 to 30-
An address generator 63 generates an address of an arbitrary rectangular area of a memory plane designated as a source plane among the memory planes 30-1 to 30-n, and an address generator 63 of a memory plane designated as a destination plane among the memory planes 30-1 to 30-n. This is an address generator that generates addresses for arbitrary rectangular areas. Address generators 62 and 63 operate on address bus 52a according to instructions from control processor 21.
, 53b. However, in FIG. 3, the address generator 62 is connected to the address bus 52.
A shows a state in which the address generators 63 are connected to the address bus 52b.

Next, the operation of one embodiment of the present invention will be explained below.
The contents of memory area A consisting of 0-1 are transferred to memory plane 3.
Taking inter-brane copying to another memory area B of 0-2 as an example, explanation will be given with reference to the operation diagram of FIG. 4 and the timing chart of FIG. 5.

First, the control processor 21 instructs the address generator 62 of the memory data transfer control circuit 60 to generate a source address (memory read address) targeting memory area A, and instructs the address generator 63 to generate a source address (memory read address) for the memory area A. Each set-up operation is performed via the system bus 22 to generate a destination address (memory write address) targeting area B. In addition, in the memory plane 30-1, the control bus processor 21 uses an address bus 52a and a control bus 53a as the address bus and control bus for the memory block 31, respectively, and the MUX 32, 33.
F/ in the same plane 30-1 as selected by
F 34 is operated (for example, set operation), and in the memory plane 3o-2, the address bus 52b and control bus 5 are used as the address bus and control bus of the memory block 31.
3b is selected by the MLJXs 32 and 33, the F/F 34 in the same brain 30-2 is operated (eg, reset operation).

Next, the control processor 21 allows only the memory brain 30-1, which is the source plane, to output data (data read output) to the data bus 51 among the memory brains 30-1, 30-2, . . . 30-o, All other memory brains are set to a data output prohibited state. The control processor 21 also includes a memory brain 30-1.3.
0-2...30-n, only the memory block 30-2, which is the destination plane, is the memory block 3.
1 is permitted, and all other memory brains are set to a state where access is prohibited. Furthermore, the control processor 21 controls the performance n-f needs (AN
D, OR, EXOR, left input through, etc.). Note that registers for specifying read output prohibition/enable, write prohibition/permission, and operation mode are omitted in FIG.
-n and is set by the control processor 21.

When the control processor 21 completes the above setting operation, the control processor 21 instructs the transfer control circuit 61 of the memory data transfer control circuit 60 to transfer data from the memory brain 30-1 to the memory brain 30-2.
A command instructing inter-brane copying is transferred via the system bus 22 to activate data transfer for inter-brane copying. Thereby, the transfer control circuit 61 controls each section based on the above command so that the data transfer shown in the timing chart of FIG. 5 is performed. That is, the transfer control circuit 61 sends a read request signal onto the control bus 53a (memory read request signal line of the control bus 53a).
A write request signal is output on (memory write request signal II) of b. Further, the address generator 62 is
The address generator 63 updates and outputs a source address (memory read address) targeting memory area A onto the address bus 52a every memory cycle, and outputs a destination address targeting memory area B onto the address bus 52b. The nation address (memory write address) is updated and output every memory cycle.

The source address updated and output from the address generator 62 every memory cycle is guided to the memory brain 30-1 via the address bus 52a, and is sent to the MU within the same brain.
X32 and supplied to the address input port of memory block 31. Also memory brain 30-1
A read request signal output from the transfer control circuit 61 onto the control bus 53a is guided to the control signal input port of the memory block 31 in the memory block 31 via the IVTUX 33. As a result, in the memory brain 30-1, a memory read operation targeting the memory block 31 is performed every memory cycle.

On the other hand, the destination address updated and output from the address generator 63 every memory cycle is guided to the memory brain 30-2 via the address bus 52b.
It is selected by the MUX 32 in the same brain and supplied to the address input port of the memory block 31. Further, a control signal input port of the memory block 31 in the memory brain 30-2 is connected to a control bus 53t from the transfer control circuit 61.
) is guided through the MUX 33. As a result, in the memory brain 30-2, a read-modify-write operation targeting the memory block 31 is performed every memory cycle.

Now, due to the memory read operation in the memory brain 30-1, the data read from the memory block 31 in the memory cycle T1 shown in the timing chart of FIG.
6 and output onto the data bus 51 during the next memory cycle T2.

The data on this data bus 51 (memory brain 30-
During the memory cycle T2, the read data from the memory block 31 of 1) is read from the A L of the memory brain 30-2.
Supplied to the left input of U35. In this memory brain 30-2, the read-modify-write operation is performed as described above. Details of this read-modify-write operation are shown below.

In the memory brain 30-2, for example, in the first half of the memory cycle T2, a memory read operation targeting the memory block 31 is performed, and the read data is latched by a latch circuit (not shown) and input to the right side of the ALU 35. Supplied. A L in memory brain 30-2
U 35 receives read data in memory cycle T1 from memory block 31 of memory brain 30-1 supplied to its left input and memory block 31 of memory brain 30-2 supplied to its right input. 31) Memory cycle T2 from (first half of)
The control processor 21 receives the read data and performs an operation specified in advance by the control processor 21. If it is just a copy between planes, the memory brain 30
The ALU 35 in -2 is set to the left input through mode, and outputs the left input contents, that is, the read data from the memory brain 30-1 as is. Memory brain 30-
The output data from the ALIJ 35 in the same brain 30-2 is guided to (the data input/output port of) the memory block 31 of the same brain 30-2.In this memory brain 30-2, in the second half of the same memory cycle T2, the memory block A memory write operation is performed targeting the memory block 31. As a result, the output data from the ALU 35 in the memory brain 30-2 is transferred to the memory block 31 of the same brain 30-2.
1 is included in.

As mentioned above, in cycle T1, memory brain 30-
In the next cycle T2, the data read from memory brain 30-2 is processed as is or is calculated with the data read from memory brain 30-2.
Written to 0-2. As is clear, this cycle T
2, the memory block 3 in the memory brain 30-1 is selected based on the next address from the address generator 62.
1 is read accessed, and the data supplied to the memory brain 30-2 is read in the next cycle T3. That is, according to this embodiment, a memory read operation targeting the memory brain 30-1, which is the source plane, and a memory read operation targeting the memory brain 30-1, which is the destination plane.
Memory write (read modify write) operations targeting 0-2 are executed simultaneously in a pipeline manner. Therefore, in reality, 1 word of memory data is transferred by 1 time.
It only requires one memory cycle. That is, copying between memory planes can be executed in one memory cycle/one word.

[Effects of the Invention] As detailed above, according to the present invention, the source plane and the destination plane can operate in the same memory cycle, so inter-brain data transfer required for copying between memory planes, etc. Speed-up can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bitmap drawing device according to an embodiment of the present invention, FIG. 2 is a block diagram of the memory brain of FIG. 1, and FIG. 3 is a block diagram of the memory data transfer control circuit of FIG. 1. 4 is an explanation of the operation of copying between memory planes, FIG. 5 is a timing chart of temporary copying between memory planes, FIG. 6 is a block diagram showing a conventional example, and FIG. 7 is a diagram showing a conventional example of copying between memory planes. It is a timing chart explaining copying. 21... Control processor, 22... System bus,
30-1 to 30-0...Memory brain (pit map memory brain), 31...Memory block, 32
．． 33...Multiplexer (MLIX), 34...
Flip-flop (F/F), 35... Arithmetic unit (AL
U>, 3B... Pipeline register (R), 50.
...Memory bus, 51...Data bus, 52a, 52
b...Address bus, 53a. 53b... Control bus, 60... Memory data transfer control circuit, 62, 63... Address generator. Applicant's representative Patent attorney Takehiko Suzue 50' Memory bus Figure 3 Figure 4 ° Figure 5

Claims (1)

[Claims] A memory having a data bus for transferring memory data, two address buses for transferring memory addresses, and two control buses for transferring various memory control signals. a first multiplexer for switching between the two address buses; a second multiplexer for switching between the two control buses; a flip-flop for controlling the first and second multiplexers; A memory block that is addressed according to the output of the multiplexer, and an arithmetic unit that takes the read data from this memory block as one input and the data on the data bus as the other input, and whose output is the address of the memory block. a plurality of bitmap memory planes each having an arithmetic unit connected to a data input/output terminal and a pipeline register that temporarily holds read data from the memory block and outputs it to the data bus; A main control means for selecting and specifying the source and destination planes from the memory planes, and a memory data transfer control circuit for controlling data transfer between the memory planes selected and specified by the main control means, the two address buses a first address generator that generates a memory address that specifies the area within the source plane on one of the two address buses; and a first address generator that generates a memory address that specifies the area within the destination plane on either one of the two address buses. A bitmap drawing device comprising: a memory data transfer control circuit having a second address generator.