JPH04123127A - Scan-out control system - Google Patents

Abstract

PURPOSE:To shorten the time required for scan-out and to efficiently execute the operation by writing specific data in a register by passing a main body device as for the part in which scan-out data is unnecessary. CONSTITUTION:To a scan data control part 10, scan address data of an unneces sary latch is given in advance from a service processor 2, and when an unneces sary scan address is given from the service processor 2, the scan data control part 10 bypasses a main body device 1, and writes specific data in a second register 3b. Accordingly, as for unnecessary latch data, the specific data can be written quickly in a second register 3b without waiting until data given from the main body device 1 is read out by giving a scan address to the main body device 1. In such a way, the time required for scan-out is shortened and the operation can be executed efficiently.

Description

[Detailed Description of the Invention] [Summary] To perform efficient operation by shortening the time required for scanout, regarding a scanout control system that can read latch data in a main unit to the outside at any timing. In a scan-out control system, the system console interface section reads out arbitrary latch data in the main unit in a bit-serial manner at arbitrary timing in response to instructions from the service processor. , the system console interface unit includes a first register that receives scan address data from the service processor, a second register that holds data read from the main unit, and a second register that provides scan addresses to the main unit and removes unnecessary scans. Regarding address data, a scan data control section is provided to write specific data into the second register without waiting for output from the main device.

[Industrial Application Field] The present invention relates to a scanout control system that can read latch data in a main body device to the outside at any timing.

As computer systems have become faster in recent years, scan-out is increasingly being used to read out and control the internal state of the main unit. For this reason, there has been a demand for faster scan-out. On the other hand, unnecessary latches are being deleted in order to increase speed, and service processors (SVPs) are sometimes required to edit scanned-out results.

[Conventional technology] FIG. 4 is a block diagram of a conventional system.

In the figure, l is the main device to be inspected. The main body device 1 includes various devices such as a computer system. 2 is a service processor (SVP) that requests scanout data from the main unit 1 and reads the scanout data; 3 is a system console interface unit (SVP) installed between the main unit 1 and the service processor 2; SCI). The system console interface unit 3 includes a first register 3a (hereinafter referred to as register 1) that receives scan address data from the service processor 2, and a second register 3b (hereinafter referred to as register 1) that holds scan-out data read from the main unit 1. (hereinafter referred to as register 2).

11 to g4 are signal lines connecting each component.

In the system configured in this way, first, the main body bag W
1 is first set to scanout mode. This mode setting may be made from a keyboard attached to the main body device 1, or may be made by an instruction from the service processor 2. The service processor 2 notifies the register 1 of the scan address via the signal line 11.

The notified scan address is held in register 1. The scan address held in register 1 is given as a scan address to main unit 1 via signal line I2.

When a scan address is given to the main device 1, the data ("1" or "0") latched in the area corresponding to the scan address is outputted from the signal line g3. Here, the output latch data is 1 bit for each scan address. The output data is held in register 2 within system console interface section 3. Here, the number of bits in register 2 is n
If it is a bit, the register 2 will hold n pieces of scan-out data.

The scan-out data output from the main device 1 is stuffed into the register 2 in order from its lower bits. In this way, scan addresses are sequentially changed and given to the main body device 1 from the service processor 2, and the latch data of each scan address is output and held in the register 2.

FIG. 5 is a diagram showing the structure of register 2. register 2
is an n-bit shift register, in which data sequentially inputted by a shift clock is shifted to the left and stored. And nbi.

When all the data in the bit is filled, one bit is read out one by one at every shift clock and is applied to the service processor 2 via the signal line g4. The service processor 2 sequentially reads the input scanout data and performs a predetermined analysis.

[Problems to be Solved by the Invention] In the conventional system as shown in FIG. 4, n scan addresses are required to obtain n-bit scan-out data. By the way, in some cases, all n pieces of data may not be necessary. Even in such a case, you can edit the contents of the specified address in the service processor 2, set an appropriate address as the address of the undefined bit, scan the main unit 1, and then use the scan-out data that is output as a result. As shown in FIG. 6, unnecessary data areas are masked with "0", and only necessary data is read.

FIG. 7 is a flowchart showing the operation of the conventional system. First, set the constant 1 that sets the number of bits in register 2 to 0.
Initialize to (Sl). Next, the specified number of bits (n in this case) is compared (S2). If the specified number of bits is 1, scan the main device 1 (S3),
Set the read contents in register 2 (SDR) (S
4). Next, update the contents of i in step S5), Step 2.
Returning to step S2, l is compared with the specified number of bits n (S
2).

If the specified number of bits reaches i in step S2, it means that all scan addresses have been scanned, so the service processor 2 registers register 2 (SDR).
The contents of register 2 are read out (S6), and the contents of register 2 are masked with the necessary bits.

In other words, only unnecessary bits are masked to "O".

Or edit (S7).

In this way, in the conventional system, the contents of unnecessary latches are also scanned out, which results in wasted time. Another problem was that it required processing to mask unnecessary data from scanned-out data.

The present invention has been made in view of such problems, and an object of the present invention is to provide a scanout control system that can shorten the time required for scanout and perform efficient operation. The purpose is

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 4 are designated by the same reference numerals. The figure shows a scan-out control system in which a system console interface section 4 reads out arbitrary latch data in a main unit 1 in a bit-serial manner at an arbitrary timing in response to an instruction from a service processor 2.

In the figure, the system console interface unit 4 includes a first register 3a that receives scan address data from the service processor 2, a second register 3b that holds data read from the main unit 1, and a second register 3b that holds data read from the main unit 1. At the same time, unnecessary scan address data is transferred to the second register 3b without waiting for output from the main device 1.
A scan data control unit 10 is provided for writing data into the scan data.

The other configurations are the same as in FIG. 4.

[The scan address data of the unnecessary latch is given to the scan data control unit 10 in advance from the service processor 2, and when the unnecessary scan address is given from the service processor 2, the scan data control unit 10 Bypassing this, specific data (for example, "0") is written into the second register 3b. As described above, according to the present invention, unnecessary latch data is immediately stored in the second latched data without waiting until the main device 1 is given a scan address and the data output from the main device 1 is read.
Since specific data can be written into the register 3b, the time required for processing can be shortened and the processing speed can be increased. Furthermore, according to the present invention, there is no need for processing to mask scan-out data.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. In the figure, 1.0 a receives the scan address read from the register 1, divides it into an unnecessary address part and a necessary address part, and in the case of an address that requires scanning, gives the scan address data to the main device 1, and also sends the scan address data to the main unit 1, and In the case of an address, the address control circuit 10b outputs an identification signal to that effect, and the address control circuit 10b is used to write the scan data read from the main device l into the register 2 upon receiving the scan address unnecessary signal from the address control circuit 10a. ,
The main device 1 is bypassed and specific data (in this case, 0
This is a clock control circuit that adjusts the write timing when writing ``).These address control circuits 10a, clock control circuits 10b, and scan data control section 1
It constitutes 0.

]] is a gate circuit that receives a control signal from the clock control circuit 10b and controls switching of the scan data read from the main unit 1 and the specific data "θ' to the register 2.The other configuration is as follows. This is the same as Fig. 1.The operation of the system configured as described above will be explained as follows.

First, the main device 1 is set to scan-out mode. This remote setting may be made from a keyboard attached to the main body device 1, or may be made by instructions from the service processor 2. The service processor 2 notifies the register 1 of the scan address via the signal line g1. The notified scan address is held in register 1. The scan address held in register 1 is given to address control circuit 10a. The address control circuit 10a receives input scan address data from the register 1, divides it into an unnecessary address part and a necessary address part, and in the case of an address that requires scanning, gives the scan address data to the main unit 1, and also sends the scan address data to the main unit 1, and In the case of a scan address, an identification signal to that effect is output.

If the address requires scanning, scan address data is given to the main device 1 via the signal line g2. When a scan address is given to the main unit 1, the data (“1”) latched in the area corresponding to the scan address is
” or “0”) is output from the signal line g3.Here, the output latch data is 1 bit for each scan address.The output data is output from the system console interface section 3. Gate circuit 11
to go into. Since the gate circuit 11 is now configured to transmit data from the main device l side to the register 2, the output scan data from the main device 1 is held in the register 2.

On the other hand, if the address control circuit 10a determines that the address is an unnecessary address, the address control circuit 10a notifies the clock control circuit 10b of this fact. Clock control circuit 10b
When receiving the unnecessary address signal, it sets the gate circuit 11 to the specific data "0" side. As a result, the data from the main unit 1 is ignored, and the specific data “O” is sent to the gate circuit 1.
1 and given to register 2. Furthermore, when writing specific data "O" to the register 2, the clock control circuit 10b increases the speed of the shift clock.

In other words, the time it takes to apply scan address data from the address control circuit 10a to the main device 1, read out the data latched in the latch in the main device 1, and provide it to the register 2 via the signal line g3, and the specific data There is a difference in the time it takes to read "0" from the gate circuit 11 and apply it to the register 2. Therefore, the clock control circuit 10b adjusts the timing of the shift clock applied to the register 2 in consideration of these time differences. It is.

When n bits of data are stored in the register 2 in this way, the service processor 2 sequentially reads out the contents of the register 2 and performs a predetermined analysis process.

FIG. 3 is a flowchart showing the operation of the system of the present invention. First, a constant l that sets the number of bits in register 2 is initialized to O (Sl). Next, a comparison is made between i and the specified number of bits (n in this case) (S2). If the specified number of bits is 1, scan the main device 1 (S3)
, set the read contents in register 2 (SDR) (
S4).

Next, the contents of i are updated (S5), the process returns to step S2, and 1 is compared with the specified number of bits n (S2).

If the specified number of bits reaches l> in step S2, it means that all scan addresses have been scanned, so the service processor 2 registers register 2 (SDR).
The content of is read out (S6). As can be seen from a comparison with the operation of the conventional system shown in FIG. 7, the operation of masking the contents of the SDR and necessary bits is no longer necessary.

[Effects of the Invention] As described in detail above, according to the present invention, scan-out data can be achieved by writing specific data into register 2 by busing the main unit for portions where scan-out data is not required. It is possible to shorten the time required and perform efficient operations.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram of the configuration of an embodiment of the present invention. FIG. 3 is a flowchart of the operation of the system of the present invention. FIG. 4 is a block diagram of the configuration of the conventional system. , FIG. 5 is a diagram showing the structure of the register, FIG. 6 is a diagram showing the scan-out format, and FIG. 7 is a flow chart showing the operation of the conventional system. In FIG. 1, 1 is a main unit, 2 is a service processor, and 3a is a register 1. 3b is register 2. 10 is a scan data control unit, 4 is a system console interface unit, p1 to p4
is a signal line. Figure 1 shows the operation of the system of the present invention. Figure 1 shows the register 2 (71MA construction. Figure 1 shows the scan-out data format.

Claims (2)

[Claims] (1) Scan-out control that allows the system console interface unit (4) to read arbitrary latch data in the main unit (1) bit-serially at an arbitrary timing in response to instructions from the service processor (2). In the system, the system console interface unit (4) includes a first register (3a) that receives scan address data from the service processor (2), and a second register that holds data read from the main unit (1). It gives a scan address to the register (3b) and the main device (1), and also sends specific data to the second register (3b) without waiting for the output from the main device (1) for unnecessary scan address data. 1. A scan-out control system comprising: a write scan data control section (10). (2) The timing adjustment mechanism that adjusts the timing of writing output data from the main device (1) to the second register (3b) and the timing of writing specific data to the second register (3b) is scanned. The scan-out control system according to claim 1, characterized in that it is provided within the data control section (10).