JPS63126035A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of wires by connecting a microprocessor to peripheral circuits through only one control line. CONSTITUTION:When an interruption request cause is generated in a peripheral circuit I/O in case of applying an interruption request from the peripheral circuit I/O to the microprocessor CPU, the circuit I/O charges up a control signal line IRQ/the inverse of ACK from a low level to a high level synchronously with a 2-phase system clock signal 2 out of signals phi1, phi2 and transmits the an interruption request signal IRQ to the CPU. The CPU receives a change in a signal level as the timing of the clock signal phi1 and decides whether the interruption is to be received or not. At the time of determining the reception of the interruption, said control line IRQ/the inverse of ACK is turned from the high level to the low level synchronously with the clock phi1 and an acknowledge signal is transmitted to the peripheral circuit I/O.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and provides a technology that is effective for use in an interrupt control circuit in a one-chip microcomputer system consisting of a microprocessor and its peripheral circuits, for example. It is related to.

[Conventional technology]

Interrupt control from peripheral circuits to the microprocessor is performed using two signals. That is, the peripheral circuit sends an interrupt request signal to the microprocessor. When a microprocessor accepts an interrupt,
When the 0 peripheral circuit that sends the interrupt acknowledge signal to the peripheral circuit receives the interrupt acknowledge signal,
A vector is output via the data bus, and the microprocessor shifts to interrupt processing accordingly. As a microprocessor with such an interrupt control function,
For example, Hitachi Ltd. rHD6418, published in March 1985.
0 (0MO38-bit microprocessor) User's manual J page 24 is available.

[Problem that the invention seeks to solve]

As described above, conventional interrupt control of microprocessors and peripheral circuits requires two control signals: an interrupt request signal and an interrupt acknowledge signal.

Therefore, at least two interrupt control lines are required for one peripheral circuit.

Therefore, when the microprocessor and peripheral circuits are configured into one semiconductor integrated circuit device, the number of signal lines increases. These signal lines are wired in one-to-one correspondence between the microprocessor and each peripheral circuit. Therefore, the wires are often routed over a relatively long distance over the semiconductor chip, which is a major cause of deteriorating the degree of integration.

An object of the present invention is to provide a semiconductor integrated circuit device that is highly integrated.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the peripheral circuit supplies an interrupt request signal to the microprocessor by changing the signal line from one level to the other level, and the microprocessor supplies the interrupt request signal to the microprocessor by changing the other level to one level on the same signal line. It supplies an acknowledge signal to peripheral circuits.

[For production]

According to the above-mentioned means, the interrupt control signal between the microprocessor and the peripheral circuit can be configured by one control line.

〔Example〕

FIG. F shows a block diagram of a one-chip microcomputer system to which the present invention is applied. Each circuit block in the figure is formed on one semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The one-chip microcomputer of this embodiment includes a microprocessor CPU and peripheral circuits 1100 to 1100/1100.
Consists of On. These microprocessors C
The PU and each of the peripheral circuits 100 to I/On are interconnected by a control bus (not shown) including an address bus AB, a data bus DB, and a signal line for interrupt control shown in the drawing.

The above peripheral circuits l100 to I/On are not particularly limited, but modularized circuits with various functions such as timer circuits, A/D conversion circuits, etc. The necessary items can be installed in various combinations.

The configuration of the microprocessor CPU itself is well known from the rHD64180 (0MO 38-bit microprocessor) user's manual, and a detailed explanation of its internal configuration will be omitted.

In this embodiment, in order to reduce the number of signal lines for interrupt control, the control signal lines provided between the microprocessor CPU and each peripheral circuit I100 to I/On are the control signal lines IRQ/I/On. It is composed of one signal line such as ACKO or IRQ/ACKn.

As mentioned above, in the interrupt control operation, the peripheral circuit I
10 to the microprocessor CPU, a certain peripheral circuit I10 sends an interrupt request signal IRQ to the microprocessor CPU, and when the microprocessor CPU accepts it, it transfers an interrupt acknowledge signal ACK. It will be done. Therefore, both the signals IRQ and ACK are never transmitted at the same time, but are always transmitted with a predetermined time difference. Focusing on this, this embodiment uses one control signal line as described above to control both the IRQ and AC signals.
K is transmitted, so to speak, in a time-division manner. however,
This is somewhat different from time-division in the usual sense, and as will be explained next with reference to the timing diagram shown in FIG. A distinction is made.

FIG. 2 shows a timing diagram for explaining an example of a signal transfer operation for the above interrupt control.

Since the control signal line IRQ/ACK is at a low level, there is no interrupt request, and the peripheral circuit I10
When an interrupt request is made to the microprocessor CPU from the peripheral circuit 110, when the cause of the interrupt request occurs in the peripheral circuit 110, the peripheral circuit I10 outputs the control signal IIRQ in synchronization with the clock signal φ2 of the two-phase system clock signals φ1 and φ2. /ACK is charged up from low level to high level and transmitted to the microprocessor CPU as an interrupt request signal IRQ.
CPU Honey (7) Control signal vAIRQ/AC
A change in the signal level of K is taken in at the timing of the clock signal φ1, and it is determined whether or not to accept the interrupt. During this time, the above system? The 111 signal line IRQ/ACK is maintained charged up to a high level. When the microprocessor CPU accepts an interrupt request,
The control signal line IRQ/A is synchronized with the clock signal φ1.
The peripheral circuit I10 transfers the interrupt acknowledge signal ACK to the peripheral circuit I10 by discharging CK from high level to low level. When the peripheral circuit I10 confirms that the interrupt acknowledge signal ACK has been transferred, it discharges the interrupt vector via the data bus DB. is transferred to the microprocessor CPU. At this time, since the interrupt processing has not yet been completed and an interrupt request has been issued, the control signal line IRQ/ACK is charged up to a high level again in synchronization with the clock signal φ2.

The microprocessor CPU processes the corresponding interrupt according to the vector transferred via the data bus DB. When this interrupt processing is completed, the microprocessor CPU connects the control signal line IRQ/AC to the
K is discharged to a low level to create a state where there is no interrupt request.

In this embodiment, as described above, the interrupt request signal IRQ
becomes active when the level of the control signal line changes from low level to high level, and interrupt acknowledge signal ACK becomes active when the control signal line changes from high level to low level. In this way, two signals are transmitted and received in a time-division manner using one signal line due to the combination of the time difference and its level change.

In this embodiment, since the interrupt request and its acknowledge signal are sent and received using one control signal line as described above, the number of control signal lines can be reduced to 1/2.

The effects obtained from the above examples are as follows. That is, (11) the peripheral circuit supplies an interrupt request signal to the microprocessor by changing the signal line from one level to the other, and the microprocessor changes the other level on the same signal line to one level. By supplying the interrupt acknowledge signal to the peripheral circuit, the interrupt control signal between the microprocessor and the peripheral circuit can be configured using one control line, thereby achieving the effect of achieving high integration.

(2) By transmitting the interrupt request signal using a charge amplifier and a discharge operation on a common control signal line, it is possible to realize the signal generation and determination circuit with an extremely simple configuration.

(3) By controlling the charge-up/discharge operation using two-phase clock signals, it is possible to easily determine the timing of the level determination.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, a specific example of a circuit that generates an interrupt request signal by changing from one level to another using a common control signal line, and generates an interrupt acknowledge signal by changing from the other level to one level. The configuration can take various embodiments.

The present invention can be widely used not only in one-chip microcomputers but also in various semiconductor integrated circuit devices having microcomputer functions.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a one-chip microcomputer system, the peripheral circuit supplies an interrupt request signal to the microprocessor by changing the signal line from one level to the other, and the microprocessor changes the other level on the same signal line. By supplying the interrupt acknowledge signal to the peripheral circuit by changing it to one level, the interrupt control signal between the microprocessor and the peripheral circuit can be configured by a one-zero control line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining an example of its operation. CPU...Microprocessor, l10ONI/On
...Peripheral circuit, DB...Data bus, AB...Address bus, IRQ/ACKO to IRQ/ACKn...Control signal line

Claims (1)

[Claims] 1. Includes a microprocessor and a peripheral circuit, and supplies an interrupt request signal from the peripheral circuit to the microprocessor by changing a signal line from one level to the other; A semiconductor integrated circuit device characterized in that an interrupt acknowledge signal is supplied to a peripheral circuit by changing the other level of the same signal line to one level. 2. The above signal line generates an interrupt request signal by charging up from one level to the other level in the peripheral circuit in synchronization with one of the clock signals of two or more phases. The semiconductor integrated circuit device according to claim 1, wherein the interrupt acknowledge signal is formed by discharging the other level to one level in a microprocessor in synchronization with a clock signal. .