JPS62160560A - Bus control system - Google Patents

Abstract

PURPOSE:To reduce the difference of response time by providing a setting means which makes the set time of the bus busy state longer than a prescribed time when the bus use rate is lower than a certain value. CONSTITUTION:A program of OS calculates the time of setting to the idle waiting state and the time of release by interrupt to calculate the busy rate of a computer, namely, the bus use rate per unit time (one minute or the like). A set value based on the use rate is set/reset to a setting means 11 (delay mode latch), which extends the time of the output of the bus busy state outputted by a bus controller in accordance with the calculated value or if this value is smaller than a prescribed value, by a diagnosis instruction. A bus controller 10 sets the time of the bus busy state by the value set to the means 11. Thus, the bus capacity is degraded when the processing load of the computer is light, and the difference of response time to terminals accompanied with the variance of the processing load of the computer is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control system for a bus used for data transfer inside a computer such as a data processing device.

[Conventional technology]

FIG. 3 shows an example of a data processing device using a conventional bus control method. In the figure, (1) is a bus for data transfer,
(2) and (3) are units 0 and 1, such as CPUs and input/output interfaces, to which data is input/output via the bus (1), and (4) is a memory unit composed of RAM. . (5) is the request signal of unit O (2) requesting the use of bus (1), (6
) is an enable signal for unit 0 (2) that allows use of bus (1), (7) is a request signal for unit 1 (3), (8) is an enable signal for Uni-node 1 (3), (9 ) is an enable signal for the memory unit (4). (10) is each of the above units (2) according to each of the above signals.

This is a bus control device that controls the use of bus (1) in (3) and (4).

FIG. 4 is a time chart showing the operation of the conventional lotus control system shown in FIG. 3, and the operation of the conventional system will be described below with reference to FIG.

First, when unit O (2) needs to read data from memory unit O (4), unit O (2) reads data from memory unit O (4) at clock n.
(2) sets the request signal (5). The bus control device (10) accepts this at the same clock n and sets the enable signal (6) at clock n+l. This causes unit 0 (2) to output the memory address onto bus (1) and transfer it to memory unit (10). Also, unit 0 (2) resets the request signal (5) at the next clock n+2. Then, at clock n+3, the bus control device (10) sets an enable signal (9) to the memory unit (4). As a result, data read from memory unit (4) is output onto bus (1) and transferred to unit O (2). This completes the memory reading of unit 0 (2). Note that during this period from clock n+1 to clock n+3, the bus control device (
A bus busy state is set inside bus (10) to prevent other units from using bus (1). By the way, at clock n+3, unit l-1(3) sends the request signal (
7), but this request cannot be accepted because the bus is busy at this clock. However, since the bus busy state is reset at clock n+4, the request from unit 1 (3) is accepted at this clock, and the enable signal (8) is set for unit l (3) at clock n+5. As a result, unit 1 (3) outputs the memory address onto hash (1) and transfers it to memory unit (4). Also, unit 1 (3) sends a request signal (7) at the next clock n+5.
) to reset. Then, at clock n+7, the enable signal (9) is set for the memory unit (4), and the data successively output from the memory unit (4) is output onto the bus 1 and sent to the unit 1 (3). Similarly, the bus busy state is set from n+5 to n+7 during this period.

As explained above about the conventional technology, controlling the use of the bus based on the bus busy state is done in order to prevent another unit from using the bus at the same time when one unit is transferring data on the bus. It is essential for

[Problem that the invention seeks to solve]

By the way, as the performance of modern computers has improved, multiple users are often able to use the computer in a time-sharing manner from their terminals in the form of a TSS (time sharing system). Since one computer is used by many people in a time-sharing manner, the heavier the processing load on the computer, that is, the more people use it, the slower the response time to the terminal becomes. On the other hand, when the processing load is light, that is, when there are few people using computers, the response time becomes extremely fast. For example, the response time may be slow during the day when many people are using the device for work, but it will be extremely fast at night when few people are using it after work. This is because the bus usage rate, ie, the busy rate, changes as the frequency of bus requests from each unit shown in FIG. 3 changes depending on the number of terminals in use.

However, for computer users, such a large difference in response time is not very convenient. In other words, the slowness of the daytime is an unavoidable problem due to computer performance, but the extreme speed at night is a problem that cannot be solved by computer performance.

This invention was made to solve the above-mentioned problems, and when the processing load on the computer is light, the performance of the computer can be moderately reduced, thereby reducing the difference in response time. The purpose is to provide a bus control method.

[Means for Solving the Problems] The bus control method according to the present invention includes a bus control device that sets a bus busy state for a predetermined period when the bus is used, and a setting means that sets the set period of the bus busy state to be longer than the predetermined period. The setting means is configured to operate when the bus usage rate per unit time is below a certain value.

[Effect]

In this invention, for example, when the bus usage rate falls below a certain value during times when the computer load is very light, such as late at night or on holidays, the setting means is set so that the bus busy state is set for a longer time than usual. As a result, the performance of the computer decreases, and the response time to the terminal user can become slower than it should be.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment, and the same or equivalent parts as in the conventional example shown in FIG. 3 are denoted by the same reference numerals, and the explanation thereof will be omitted. In the figure, numeral 11 is a delay mode latch corresponding to the setting means provided in the bus control device (10) according to the present application, and in this embodiment, the machine language program can set/reset the input/output by the diagnosis command. It has become. The O3 (operating system) program calculates the busy rate of the computer, that is, the busy rate of the bus, by measuring the time when the Idle WAT is entered and the time when it is released by an interrupt. When a state is detected in which the average busy rate over a unit time 9, for example, one minute is less than a constant value 1, for example 5%, the O8 program sets this delay mode latch (11) by a diagnosis command. On the other hand, if the average busy rate for one minute becomes 5% or more while this latch is set, O8 similarly resets this delay mode latch (11) by a diagnosis command. When this delay mode latch (11) is reset, the bus (1) is the same as in the conventional device of FIG.

That is, it operates as shown in the time chart shown in FIG.

FIG. 2 shows the delay mode latch (
11) is set, and the operation of this embodiment will be described below with reference to this diagram.

Unit O (2) sends a request signal (5) at clock n.
is set, the enable signal (6) is set at clock n+l and the memory address is output on the bus (1), and the enable signal (9) is set at clock n+3 and the memory read data is output on the bus (1). The output is the same as in the case of FIG. The difference is that in the case of FIG. 4, the bus busy state is set from clock n+1 to clock n+3, whereas here it is set from clock n+l to clock n+7, that is, four clocks more. Therefore, even if unit 1 (3) raises the request signal (7) at clock fi+3, it will not be accepted until clock n+8. This request is accepted at clock n+8, the enable signal (8) is set at clock n+9, and the memory address is output from unit 1 (3) onto bus l. Then, at clock n+11, memory read data is outputted from the memory unit 7 (4) onto the bus (1) and sent to the unit 1 (3). In this case as well, the bus busy state is set from clock n+9 to clock n+15, which is 4 clocks longer than usual. When the delay mode latch (11) is not set (Fig. 4), unit 1 (3) is clocked n+
3, cut the request signal (7) by 7" and set the clock f.
Memory read data is accepted at clock i+7, but when the delay mode latch (11) is set (Figure 2), unit 1 (3) similarly sets the request signal (7) at clock H+3. will also receive data at clock n+11. That is, the delay mode latch (
If 11) is set, each unit will spend extra time transferring data on bus (1), which will reduce the performance of the computer. This also slows down the response time of each terminal.

Note that in the above embodiment, the machine language program is
The operating system (operating system) detects the Idle state of the computer and sets/resets the delay mode latch, but instead, a microprogram such as a service processor similarly detects the Idle state of the computer and sets/resets the delay mode latch. A latch may also be set/reset.

In addition, a delay mode latch is provided with, for example, 4 bits, and when these values are "o o o o", it is normal operation and "000".
When it is 1", the bus busy state is extended by 1 clock from normal, and when it is "OO10", it is also extended by 2 clocks, etc.
..., "1111'" may be similarly extended by 15 clocks.

[Effects of the Invention] As described above, according to the bus control method according to the present invention,
A bus control device that sets the bus busy state for a predetermined period when the bus is used is provided with a setting means for setting the bus busy state to be longer than the predetermined period, and when the bus usage rate per unit time is below a certain value, the above setting is performed. By making the process more effective, it is possible to lower the bus performance and, by extension, the computer performance when the computer's processing load is light, thereby reducing the difference in response time for terminals caused by changes in the computer's processing load. You can get the effect that you can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of a bus in an embodiment of the present invention.
FIG. 3 is a block diagram showing a conventional bus control method, and FIG. 4 is a time chart showing the operation of the conventional bus control method. (1)...Bus, (2,)...Unino)0. (3)...Unit L (4)...
...Memory unit, (5), (7)...
-Request signal, (6). (8), (9)... Enable signal, (1
0)... Bus control device, (11)...
Delay mode controller 7chi (setting means). Note that the same reference numerals are used for the middle part of the figure or corresponding parts.

Claims (1)

[Claims] A common data transfer bus connects multiple units that input and output data, and when one of the units requests to use the bus when the bus is not in use, the unit is given permission to use the bus and becomes bus busy. In a computer equipped with a bus control device that sets the bus busy state for a predetermined period of time and controls the bus so that it does not accept any bus use requests from other units during that time, the bus control device has the bus busy state set period as described above. 1. A bus control method, characterized in that a setting means is provided for setting a period of time or more, and the setting means can be operated when the bus usage rate per unit time is below a certain value.