JPS634218B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling input/output interrupts of an electronic computer.

The simplest method for controlling input/output device interrupts is
This is a method of generating an interrupt for the input/output device with the highest priority among the input/output devices that caused the interrupt, according to predetermined priorities of the input/output devices. However, with this method, when interrupt factors for high-priority input/output devices occur continuously, lower-priority input/output devices are left in an interrupt pending state for a long time, resulting in a so-called sinking phenomenon. .

There are two ways of thinking to avoid this phenomenon: One is the first-in, first-out method.
That is, the addresses of input/output devices with pending interrupts are stored in a table sequentially, and interrupts are generated in order from the address entered in the table first. The other method is to check the interrupt pending status of all input/output devices according to the priority order, but when an interrupt occurs for a certain input/output device, that input/output device is excluded and the next and subsequent input/output devices are This is a method of checking the interrupt pending state of an input/output device.

Although these two ideas are not difficult in principle, there is a problem in that concrete control is complicated and requires a considerable amount of hardware.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an input/output interrupt control method that can avoid the above-mentioned sinking phenomenon using a simple control mechanism.

Thus, the input/output interrupt control method according to the present invention uses first and second registers. The first register is used as an interrupt pending state flag, and when an interrupt factor occurs in an input/output device, the bit corresponding to that input/output device is set to "1" (or "0"). The second register acts as a so-called interrupt register, and the contents of the first register are transferred during initialization and when all bits become "0" (or "1"). This second
The interrupts of the input/output devices (interrupt pending devices) corresponding to the "1" (or "0") bit of the register are sequentially generated in accordance with the priority order. At the same time, the bits in the first and second registers corresponding to the input/output device that generated the interrupt are reset.

An embodiment of the input/output interrupt control method according to the present invention having the above-mentioned features will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

1 is a group of input/output devices (eight in the figure), and each input/output device is assigned an address of #0, #1, #2, . . . , #7. When a termination or request interrupt factor occurs in one of these input/output devices, the address of that input/output device is transferred to the decoder 2 via the bus, etc.
is transmitted to. Decoder 2 is a circuit that converts bits of the input/output device address that caused the interrupt.
The corresponding bit in the first register 3 is set to "1". It is assumed that the higher bits of the register 3 (on the left side in the figure) are associated with input/output devices of higher priority. In this way, register 3
will display the I/O devices with pending interrupts.

All bits of the second register 4 are first cleared to "0", and then the contents of the first register 3 are transferred (of course, the contents of the first register 3 are saved). Thereafter, the above transfer is performed when all bits of register 4 become "0".

5 is a priority encoder, and when register 4 has a "1" bit, the interrupt address corresponding to the most significant bit (in this example, the higher the priority of register 4 is, the higher the priority) is set as the interrupt address. - Register in register 6 and generate an interrupt. When the priority encoder 5 registers an interrupt address corresponding to a certain "1" bit in the register 4, that bit and the corresponding bit in the first register 3 are reset. Note that, after a certain bit in the register 3 has been reset, if an interrupt factor occurs again in the input/output device corresponding to that bit, the bit will of course be set again.

As described above, when all bits of register 4 become "0", the contents of register 3 are transferred to register 4.
The interrupts are generated sequentially as described above.

FIG. 2 is a schematic flowchart showing the interrupt control routine described above. This routine runs at idle or interrupt checkpoints, similar to conventional electronic computers. Note that the step of first clearing the register 4 is not shown in the figure.

Next, an example of transition of the states of registers 3 and 4 will be explained with reference to FIG.

Suppose now that the contents of register 3 are transferred to register 4, and the contents of both registers become as shown in (1). In the priority encoder 5, the higher the bit (on the left side) of the register 4, the higher the priority is set, so in this example, the most significant bit (corresponding to input/output device #0) is "1". , registers interrupt address #0 in the interrupt address register 6, and generates an interrupt. At this time, bit #0 of registers 3 and 4 is reset, and registers 3 and 4 enter the state shown in (2). However, (2) is expressed on the assumption that #0 becomes interrupt pending again after accepting the interrupt of #0. In other words, bit #0 of register 3 was reset once, but then set again.

In state (2), the most significant bit among the "1" bits in register 4 is bit #2, so
The #2 interrupt is accepted, the #2 bits of registers 3 and 4 are reset, and the contents of both registers change as shown in (3).

In state (3), interrupt #3 is accepted and bit #3 of registers 3 and 4 is reset.
Now, all bits in register 4 become "0", so the contents of register 3 are transferred to register 4,
The contents of both registers are shown in (4).

In state (4), the most significant bit of register 4 is "1", so interrupt #0 is accepted,
The contents of registers 3 and 4 change to the state shown in (5).

In state (5), interrupt #6 is accepted and all bits of register 4 become "0". Therefore, the contents of register 3 are transferred to register 4,
(6) is reached.

In the same way, the state changes to (7), (8), etc.
Interrupts are accepted as #2, #3, and so on.

Here, even if #0 becomes interrupt pending again after #0 interrupts in state (1), until all bits of register 4 become "0" and are retransferred from register 3 ((4 As described above, the #0 interrupt pending state continues until the state changes to ). As described above, according to the present invention, it is possible to prevent the sinking phenomenon of interrupts from low-rank input/output devices as described above.

Note that in the present invention, there are 1 register for interrupt control.
However, due to recent advances in integrated circuit technology, the cost increase due to the increase in registers is negligible. Furthermore, control including transfers between registers and reset operations can be easily realized at the microprogram level. For this reason, the present invention is advantageous in terms of cost compared to the conventional method.

As described above, according to the present invention, there is an effect that interrupt control that can prevent the sinking phenomenon can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a schematic flowchart of the interrupt control routine;
The figure is a transition diagram of register contents for explaining the operation of the embodiment. 1... Input/output device group, 2... Decoder, 3, 4
...Interrupt control register, 5...Priority encoder, 6...Interrupt address register.

Claims (1)

[Claims] 1 First and second with corresponding input/output devices and bits
Each time an interrupt factor occurs in an input/output device, the bit in the first register corresponding to that input/output device is set to “1” (or “0”), and the contents of the first register are The second transferred
The interrupts of the input/output devices corresponding to the "1" (or "0") bits of the registers are generated sequentially according to the priority order, and at the same time, the interrupts of the input/output devices corresponding to the input/output devices that have generated the interrupt are 1 and the bits of the second register are reset, and when all bits of the second register become "0" (or "1"), the first
An input/output control device characterized in that the contents of the register are transferred again to the second register, and an interrupt is generated in the same manner as described above depending on the contents of the second register.