JPS63119578A - Semiconductor device - Google Patents

Abstract

PURPOSE:To control a threshold voltage value (Vth) to be an adequate value all the time and to make it possible to manufacture the title device by a simple method, by providing a conductor layer and an insulating layer in contact with the conductor layer with respect to an N-channel type thin film transistor group and a P-channel type thin film transistor group, and contacting the insulating layer with the channel part of each thin film transistor (TFT). CONSTITUTION:In a semiconductor device, a complementary type circuit comprising an N-channel type thin film transistor and a P-channel type thin film transistor and the like are provided. A conductor layer and an insulating layer contacting the conductor layer are provided with respect to the N-channel type thin film transistor group and the P-channel type thin film transistor group. The insulating layer is in contact with the channel part of each thin film transistor. For example, source and drain parts 107, 109, 110 and 112 of the TFTs are formed only in the vicinities of the surfaces of the thin films. Thus Vth can be always controlled at an adequate value, and a semiconductor device, which includes the complementary integrated circuit that can be fabricated by a simple method, is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Use in Oncology The present invention relates to the structure of a semiconductor device having a complementary circuit using a thin film transistor (hereinafter referred to as TPT).

[Conventional technology]

The structure of a conventional complementary TF'T integrated circuit is as shown in FIG. 107 and 109. 11O and 112 are the source and drain parts of TF'T, 108 and 111, respectively.
113 and 114 are the gates of the TPT, respectively. 115 and 116 are Tl!, respectively. 'T gate electrode, 107 to 1
T F Tt- grooved at 09, 113 and 115
If it is an N-channel type, the TUFT composed of 11O to 112, 114, and 116 will be a P-channel type.

117, 119, 120, 123 are interlayer insulating films, 125
Reference numerals 128 to 128 are wiring materials, and 130 is a protective film.

[Problem that the invention seeks to solve]

In the TF'T as shown in FIG. 2, the threshold voltage (hereinafter referred to as vth) fluctuates due to abnormalities during the N and P channel co-manufacturing process (for example, the channel portions 108 and 111
change in the impurity concentration in the gate electrodes 115 and 116), especially in H! After performing a plasma process or a sputtering process, vth shifts significantly. Figure 3 (
aJ is the gate voltage (Vas)-drain current (11) of the TUFT, which is a degradation type with vth shifting in the negative direction, and (b) is an enhancement type with vth shifting in the positive direction. The VO2 of TFT became
- 8% sex, and the same figure (c) shows normal vth [(V(
VO when ha = 8 is the minimum from near OV)
2-8 is custom made.

When vth is 1/7th (Figure 3 ('') * (6)
), Vall = 8 in mouth V (hereinafter referred to as work of
f ) increases.

This may interfere with circuit operation.

In order to solve the above problems, the channel parts 108 and 1
Provide electrodes above and below 11! Although a 11-structure 'rFT has been devised, it has problems such as requiring two extra patterning steps and complicated wiring, and has not been put into practical use.

SUMMARY OF THE INVENTION The present invention is intended to solve the problems described below, and its purpose is to provide a complementary T11'T integrated circuit that can always control vth' properly and directly and that can be manufactured by a simple method. It is about realization.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a conductive layer and an insulating layer in contact with the conductive layer for each of the N-channel RIII transistor group and the P-channel thin film transistor group, and the insulating layer is connected to the channel portion of the thin film transistor. A special number is that it is tangent to .

[Implementation row]

An embodiment of the present invention is shown in FIG. 1, where (a) is a sectional view,
Figure (6) is a plan view. In the same figure (α), 10
1 is an insulating substrate, 102 and 103 are conductive layers, and 104 to 106 are insulating layers. 107,109.110,11
2 is the source and drain part of TPT.

108 and ill are TPT channel parts, 113 and 1
What about 14? ? TO gate insulation, engineering 15 and 116 are TN
This is a TO gate electrode. 107.108.109,11
If the TIFT composed of 3,115 is an N-channel type, the TIFT composed of 110, 111, 112, 114, and 116 is a P-channel type. 117 to 123
Is the interlayer insulation olfactory.

124 to 129 are wiring materials such as muj, 130 to 13
2 is the retention membrane. In Figure (6), the same symbols as in Figure (a) represent the same things. In Figure (6), 133 and 134 are 107 to 109 and 1, respectively.
A thin film composed of 10 to 112, 135 and 14
0 is the wiring material and conductive layer 102 and 103″f, respectively:
Contact holes 136 to 139 for connection are contact holes for connecting the wiring material and the saw X/drain portion of the TPT. In the structure shown in the figure, the wiring materials 24 and 129 are connected to the conductive layers 102 and 103, respectively.
The threshold voltage vth of a single-wire TPT serving as a terminal for controlling the potential of is expressed by the following equation.

Vth = VT - Cs, Vsrb / Cow +
a (1) VT...vth when the potentials of the conductive layers 102 and 103 are equal to the source potential of TPT C8...-Capacitance of the insulating layer 105 (area is equal to the channel part 10
8 and 111) v8 舊...Potential difference between the conductive layers 102 and 103 and the source of the TFT C6W...Capacity α of the gate insulating films 113 and 114 e...Other factors N-channel type and P-channel temperature can be applied by simply inverting the signs of the second and third terms on the right side of equation α).

(1) As shown in Figure 2 (2), if VT is set so that the potential applied to the four electric layers 102 and 103 is set to an appropriate value VSlL, Vth becomes an appropriate value, and the custom-made TPT is shown in Figure 3 (c). ) can be done as follows.

In addition, if a single structure is used, experience and the ion implantation process for forming the source/drain parts 107, 109, 110, 112, and the sputtering process for forming the retainer i4@130 to 132t, etc. Damage (dielectric breakdown of gate insulating films 113, 114, etc.) can be reduced,
High yield.

However, if the materials and film thicknesses are set so that the insulating layers 104 to 106 and the one-layer interlayer films 117 to 123 can be etched in the same process, the patterning process shown in FIG. The structure shown in can be realized.

Furthermore, if the conductive layers 102 and 103 are polycrystalline silicon doped with impurities, and the insulating layers 104 to 106t are silicon oxide layers obtained by thermally oxidizing the polycrystalline silicon,
The film quality of the insulating layers 104 to 106 is also good, and the reliability of the TIFT is improved.

The figure shows gate electrodes 115, 116 and gate insulating film 11.
3 and 114 are on the upper part of the channel part 108 and 111. Similarly, when the genit electrode and the gate insulating film are on the lower part of the channel part, the insulating layer and the conductive film are in contact with the channel part. All you have to do is create layers.

FIG. 4 shows an embodiment of the present invention, in which TPT source and drain portions 107, 109, 110, and 112 are formed only near the surface of the thin film. This can be manufactured if the conditions for the process of forming the source/drain regions are perfected. In the embodiment shown in FIG. 1, conductive layers 102 and 1
Depending on the potential applied to 03, a channel may be formed near the interface between 108, 111 and 105, and the leakage current of the TFT may increase, but this problem can be resolved by creating a structure as shown in Figure 4. It was done.

FIG. 5 shows an application of the present invention, in which the present invention is applied to a three-dimensional integrated circuit. In the same figure.

The same symbols as in Figure 1 represent the same things as in Figure 1, 5
01 and 502 are conductive layers, 503 and 504 are insulating layers,
505 and 506 are TFT source and human train parts, 5
07 is the channel part of TIPT, 508 is the gate insulation film of TIPT, 509 is the gate electrode of TPT, 510 to 5
14 is an interlayer insulating film, 515 to 518 are wiring materials, 51
9 to 521 are protective films. In the implementation sequence as shown in the same figure.

vt of TFT made up of 11I elements from 505 to 509
h can be controlled by the potential applied to the conductive layer 501;
Since it also plays the role of shielding the lower TPT from interference caused by T and 107, 108, 109, 113, and 115, analog minute signals can also be handled.

[Effect of the invention] As described above, by using the present invention, t), always vt
A semiconductor device including a complementary TIFT integrated circuit that can be controlled directly and appropriately and that can be manufactured by a simple method is realized1.
The present invention is particularly effective when applied to a process that includes H2 products, processes, etc. in which vth easily changes, and is also highly effective when applied to three-dimensional integrated circuits.

[Brief explanation of the drawing]

FIG. 1(α) is a sectional view of a semiconductor device in an implementation row of the present invention, and FIG. 1(6) is a plan view. The second factor is a cross-sectional view of a conventional semiconductor device. Figure 3 ((L) (6) (6) is a diagram for explaining the vG8-8 characteristics of TFT, &a) is depletion type, (b) is ennouncment type, (C) is vth A diagram showing a case of proper direct handling. FIG. 4 is a cross-sectional view of a row in which source and drain regions of TFTs are formed near the surface of a thin film in an embodiment of the present invention. FIG. 5 is a cross-sectional view of a three-dimensional integrated circuit in an application row of the present invention. 101...Insulating substrate 102.103---Conductive layers 104 to 106...Insulating layers 107, 109, 110, 112---TPT source/drain portion 108.111...TFT channel portion 113. 11
4-...TFT gate insulating film 115.116Q...T
Gate electrodes 117 to 123 of F"!'...interlayer t
#, @124 to 129...Φ Wiring material 130 to 132-...Protective film or more Applicant: Seiko Egun Co., Ltd.-2,

Claims (2)

[Claims] (1) In a semiconductor device having a complementary circuit including an N-channel thin film transistor and a P-channel thin film transistor on an insulating substrate, a conductive layer and insulation in contact with the conductive layer are provided for each of the N-channel thin film transistor group and the P-channel thin film transistor group. 1. A semiconductor device comprising a layer, the insulating layer being in contact with a channel portion of a thin film transistor. (2) The semiconductor device according to claim 1, wherein the conductive layer is formed of polycrystalline silicon doped with impurities.