JPS6343375A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a thin-film transistor capable of controlling threshold voltage at a proper value at all times by forming a conductive layer and an insulating layer being in contact with the conductive layer and bringing the insulating layer into contact with a channel section for the thin-film transistor. CONSTITUTION:A conductive layer 102 and insulating layers 103, 104 are shaped onto an insulating substrate 101. Source, drain and channel sections 105, 106, 107 for a thin-film transistor TFT are formed onto the layer 104, thus shaping the thin-film transistor TFT. The conductive layer 102 and the insulating layer 103 are formed adjacently at that time, and the insulating layer 103 is brought into contact with the channel section of the TFT. The potential of the conductive layer 102 is controlled by a wiring material 116. Accordingly, the fluctuation of threshold voltage is prevented, thus causing no trouble on circuit operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device formed by integrating thin film transistors (hereinafter referred to as TPT), etc., and a method for manufacturing the same.

[Conventional technology]

The structure of a conventional TIPT integrated circuit is shown in FIG. 2, where the electrode that controls the charge induced in the channel region is the gate 1!
It was only extreme. In the figure, 101 is an insulating substrate;
5 and 106 are the source and drain parts of TF'T, 1o
7 is the channel part of TF'T, 108 is the gate insulating film, 1
09 is gate 1! poles, 11Q to 112 are interlayer insulating films,
114 and 115 are wiring materials such as He2. In the figure, the protective film is omitted ◇ [Problem to be solved by the invention] In the TFT shown in Fig. 2, the threshold voltage (hereinafter referred to as vth) fluctuates due to abnormalities during the manufacturing process. . (
For example, the impurity concentration of the channel part 107, the gate electrode 10
(e.g., changes in impurity concentration in 9), especially after performing an H, plasma process, or sputtering process, v th shifts significantly. Figure 3 (α) shows the TPT gate voltage (VGII) when vth shifts in the negative direction and becomes depletion type.
- Drain current (I D8) characteristics, the same figure (b) is vth
T shifted in the positive direction and became an enhancement type.
'FT(7)VG[]- is the fl characteristic, and the figure (c) is the 8 characteristic from vG day- when vth is a normal value (S is minimum near Vag = OV). When v th shifts (Fig. 3 (α) + (b)), V a
g=Q In order to solve the above problems in which B (hereinafter referred to as Ioff) increases at y, which hinders circuit operation, a TIFT with a structure in which electrodes are provided above and below the channel portion 107 was devised. However, it has problems such as requiring two extra buttering steps and complicated wiring, so it has not been put into practical use.

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems, and its purpose is to realize a TPT integrated circuit that can always control vth to an appropriate value and that can be manufactured by a simple method.

[Means for solving problems]

In order to solve the above problems, the present invention is characterized in that a conductive layer and an insulating layer are provided in contact with the conductive layer, and the insulating layer is in contact with a channel portion of a thin film transistor (TPT).

〔Example〕

An embodiment of the invention is shown in FIG. In the same figure, 101
is an insulating substrate, 102 is a conductive layer, and 103 and 104 are insulating layers. 105 and 106 are the source and drain parts of the TFT, 107 is the channel part of the TFT, and 708 is the TPT.
The gate insulating film 109 is the gate electrode of the TF'T, and the above elements 105 to 109 form the TPT. 110 to 113 are interlayer insulating films between the wiring material and the TIFT, 114 to 116 are wiring materials including A, and 117 and 11B are protective films. In the structure shown in FIG. 1, the wiring material 116 serves as a terminal for controlling the potential of the conductive layer 102. The threshold voltage vtb of the TPT of this structure is as follows: 0 Vth=VT-Q 5rI10 ox+α (
1) VT...vth when the potential of the conductive layer 102 is equal to the source potential of TIFT 0 days...Capacity of the insulating layer 105 (area is the area of the channel portion 1070) VIFσ...Conductivity Potential difference Co between layer 102 and source
x... Gate insulating film capacitance α after 10 days...
...Other factors As shown in equation (1), if the potential applied to the conductive layer 102 is set to be an appropriate value y sU no matter what value vT is, then v th will be an appropriate value, and the characteristics can be adjusted to Figure 3 (c)
It can be done as follows. Furthermore, this structure does not require any patterning of the conductive layer 102, resulting in a simple process, and is less likely to cause defects due to steps. Also,
With this structure, from experience, the source and drain parts 10
T in the ion implantation process to form 5 and 1o6, the sputtering process to form protective films 117 and 118, etc.
Damage to the F'T (dielectric breakdown of the gate insulating film 108, etc.) can be reduced, resulting in a high yield.

In addition, if the material and film thickness are set so that the insulating layers 103 and 104 and the interlayer insulating films 110 to 115 can be etched in the same process, the patterning process (contact hole forming process) will be increased (for example, using a silicon oxide film). The structure shown in FIG. 1 can be realized without causing any problems.

In addition, the conductive layer 102 is multilayered by 11! If crystalline silicon is doped with impurities and the insulating layers 103 and 104 are silicon oxide layers obtained by thermally oxidizing the polycrystalline silicon, the insulating layer 1
The film quality of 06 and 104 is also good, improving the reliability of TIFT.■ The figure shows an example where the gate electrode 109 and the gate insulating film 108 are on the upper part of the channel part 107, but the gate electrode and the gate insulating film are on the channel part 107. Similarly, in the case where the TPT source and drain parts 105 and 106 are formed using a thin film, an insulating layer and a conductive layer may be provided in contact with the upper part of the channel part. This is an example in which the source/drain regions are formed only near the surface.0 This is possible if the process conditions for forming the source/drain regions are perfected.0
In the embodiment shown in FIG. 1, depending on the potential applied to the conductive layer 102, a channel may be formed near the interface between 107 and 103, and the leakage current of the TPT may increase, but the structure shown in FIG. As a result, this problem has been solved. FIG. 5 shows an example of application of the present invention, in which the present invention is applied to a three-dimensional integrated circuit. In this figure, the same symbols as in FIG. 1 represent the same things as in FIG. 1. 501 and 502 are conductive layers, 503 and 504 are insulating layers, 505 and 506 are TPT source and drain parts, and 507 is TPT.
IFT channel part, 508 is TPT gate insulating film,
509 is the gate N pole of TIIFT, 510 to 514 are interlayer insulating films, 515 to 518 are wiring materials, and 519 to 521 are protective films.In the embodiment shown in the figure,
TIFT vth consisting of elements 505 to 509
Not only can the conductive layer 501 be controlled by the potential applied to the conductive layer 501, but also the conductive layer 501 can be
Since it also plays the role of suppressing the interference of the lower TPT caused by T and 105 to 109, analog minute signals can also be handled.
TIF that can be controlled to an appropriate value and manufactured using a simple method
A semiconductor device including a Tfi integrated circuit is realized. ◎The present invention is particularly effective when applied to a process including H, plasma process, etc. where vth changes easily, and is also applicable to a three-dimensional integrated circuit. is also very effective.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device in an embodiment of the present invention. FIG. 2 is a sectional view of a conventional semiconductor device. Figure 3(a) s (6) and (6) are ve of TIFT.
A diagram for explaining shelf life from s-. (α) is depression type. (6) is enhancement type, (C) is vt
FIG. 4 shows a case where h is an appropriate value. FIG. 4 is a cross-sectional view of an example in which the source and drain regions of a TIFT are formed near the surface of a thin film in an embodiment of the present invention. FIG. 5 is a cross-sectional view of a three-dimensional integrated circuit in an application example of the present invention. 101...Insulating substrate 102...Conductive layers 103 and 104...Insulating layers 105 and 106...TFT north and drain portions 107... ...TIFT channel section 108...
...TFT gate insulating film 109...TIF
Gate electrodes 110 to 113 of T...Interlayer insulating films 114 to 116...Wiring materials 117 and 1
18...Protective film or more Applicant Seiko Epson Corporation/ρ7 Ding FT-Sf channel shield P VT 1 Figure 2 Figure 3 (0) Jun 4 Figure 49 ~ River 1 Minefu L after Figure 5

Claims (4)

[Claims] (1) A semiconductor device comprising thin film transistors etc. integrated on an insulating substrate, characterized in that a conductive layer and an insulating layer in contact with the conductive layer are provided, and the insulating layer is in contact with a channel portion of the thin film transistor. Device. (2) The semiconductor device according to claim 1, wherein the conductive layer is formed of polycrystalline silicon doped with impurities. (3) In a method for manufacturing a semiconductor device that integrates a conductive layer on an insulating substrate, an insulating layer in contact with the conductive layer, and a thin film transistor with a channel portion in contact with the insulating layer, a contact hole is formed between the thin film transistor and wiring material. A method for manufacturing a semiconductor device, characterized in that a step of forming a contact hole between a conductive layer and a wiring material is the same step. (4) The method for manufacturing a semiconductor device according to claim 3, characterized in that after forming a thin film of polycrystalline silicon, the polycrystalline silicon is thermally oxidized to form an insulating layer.