JPH08293598A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To form a plurality of types of threshold voltages by one photolithography by planely dividing to provide a plurality of channel impurity regions on a channel region between a source region and a drain region, and providing an insulated gate field effect transistor on the channel region via a gate insulating film. CONSTITUTION: An NMOSFET is formed on the surface of a P-type silicon substrate 1 not formed with an N-type well 2. An N-type source region 4A and an N-type drain region 4B isolated at the channel region are provided in the NMOSFET. A plurality of divided channel impurity regions 7 are provided in a dotlike plane manner on the channel region of the surface of the substrate 1 between the regions 4A and 4B. Further, a gate electrode 4C is provided on the surface of the channel region via a gate oxide film 6. Thus, a plurality of types of threshold voltages can be formed on the same substrate 1 by one time photolithography.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a channel region of a MOS transistor forming a semiconductor integrated circuit device, and more particularly to the impurity concentration of the channel region. The present invention relates to an integrated circuit semiconductor device composed of MOS transistors having a plurality of threshold voltages on the same substrate and a manufacturing method thereof.

The present invention relates to an integrated circuit semiconductor device having different conductivity type MOS transistors on the same substrate and a method for manufacturing the same. The present invention relates to an integrated circuit semiconductor device having high breakdown voltage and low voltage MOS transistors to which different gate voltages are applied on the same substrate, and a manufacturing method thereof.

The present invention relates to a semiconductor device including an analog circuit and a digital circuit on the same substrate and a method for manufacturing the same. The present invention relates to a semiconductor device formed on a thin film semiconductor provided via an insulating film on a substrate and a manufacturing method thereof.

[0004]

2. Description of the Related Art FIG. 19 is a schematic plan view showing a MOS transistor in a conventional semiconductor integrated circuit device. In FIG. 19, the sources, drains, and gates of the three types of transistors are schematically shown, and the metal wiring of aluminum and the like are omitted for simplicity.

The transistors 1, 2 and 3 have different threshold voltages (Vth). 20
It is a typical sectional view showing a MOS transistor in a conventional semiconductor integrated circuit device.

In the transistor 1, the channel region 20
The impurity concentration of 04 is, for example, a value determined by the impurity concentration of the semiconductor substrate 2006, and the threshold voltage is Vth1. The threshold voltage Vth2 of the transistor 2 is set to Vth1
If a different value from that of the channel region 1 of the transistor 1 is used, impurities are introduced by ion implantation after patterning a resist or the like using a mask or the like for selecting a region for introducing the impurity. The channel region 2 is formed.

At this time, the pattern 1905 of the ion implantation mask 1 is made slightly larger than the channel region and covers the entire surface in consideration of mask misalignment as shown in FIG. 19B. By doing so, Vth2 of the transistor 2 and Vth1 of the transistor 1 can be formed differently, and similarly, as in the case of Vth3 of the transistor 3, a transistor having a required threshold voltage by introducing a necessary type and a necessary impurity. To form.

Although not shown, in an IC having a high voltage MOSFET having a thick gate oxide film and a low voltage MOSFET having a thin gate oxide film provided on the surface of the same substrate,
In order to make each threshold voltage almost the same value, the concentration of the uniform impurity region in the channel region of each MOSFET is controlled by the photolithography technique.

Similarly, PMOSFET and NMOSFET
Also in the CMOS IC made of, the channel doping process is performed separately to obtain almost the same threshold voltage.

[0010]

However, since the MOS transistors in the conventional semiconductor integrated circuit device each have a channel region having a uniform impurity concentration as described above, a semiconductor formed on a single semiconductor substrate. In order to form a plurality of kinds of threshold voltage transistors in an integrated circuit device, a step of introducing a necessary number of kinds of impurities or impurity concentrations has been necessary.

Therefore, forming a plurality of types of transistors having threshold voltages in a semiconductor integrated circuit device formed on a single semiconductor substrate causes a cost increase and is a constraint on circuit design. It was Further, in a case where a transistor having a different threshold voltage before channel doping is provided on the same substrate, a plurality of photolithography steps are required for the IC to adjust the threshold voltage to the range of the power supply voltage. Therefore, it takes a long manufacturing period and a high manufacturing cost to control the threshold voltage of different gate insulating films, different substrate concentrations, or different conductivity type MOSFETs.

[0012]

In order to solve the above problems, the present invention takes the following means. (1) A second conductivity type source / drain region provided separately from the first conductivity type semiconductor region on the substrate surface, a channel region which is a semiconductor region between the source region and the drain region, and a channel region. An insulated gate field-effect transistor (M) including a plurality of channel impurity regions which are divided in a plane for controlling a threshold value and a gate electrode which is provided on the channel region with a gate insulating film interposed therebetween.
The semiconductor device has an ISFET).

(2) The semiconductor device of (1) is characterized in that the channel impurity region is provided shallower than the junction depth of the source / drain regions. (3) The semiconductor device of (1) is characterized in that five or more channel impurity regions are provided.

(4) The semiconductor device of (1) is characterized in that a second MISFET having a second gate insulating film having a thickness different from that of the gate insulating film is provided on the surface of the substrate. (5) A second MISFE is provided on the second semiconductor region provided on the substrate surface and having a different impurity concentration from the semiconductor region.
The semiconductor device of (1) is characterized in that T is provided.

(6) The semiconductor device of (1) is provided in which the second MISFET is provided on the second semiconductor region of the second conductivity type which is provided on the surface of the substrate and has a conductivity type different from that of the semiconductor region. (7) The semiconductor device according to (1), in which an analog circuit including a MISFET and a digital circuit including a second MISFET including a second channel region having an area smaller than that of the channel region by one digit or more are provided on the substrate surface. And

(8) The semiconductor substrate and the insulating film provided on the semiconductor substrate constitute the substrate, and the thickness of the semiconductor region is formed to be thinner than 10 μm (1).
Semiconductor device. (9) The semiconductor device according to (8) has the same thickness as that of the channel region in the semiconductor region.

(10) The semiconductor device according to (8), in which the thickness of the semiconductor region is the same as the depth of the channel impurity region. (11) A step of forming a field insulating film on the surface of the first conductivity type semiconductor region on the surface of the substrate, and a step of forming a gate insulating film on the surfaces of the first transistor region and the second transistor region of the semiconductor region. A step of forming a resist pattern for forming a channel impurity region on the surface of the first transistor region, and ion implantation of impurities into the surface of the first transistor region using the resist pattern as a mask to form a channel impurity region. A step of patterning a gate electrode such as a gate insulating film, a step of forming a second conductivity type source / drain region on the surface of the first transistor region so as to be divided by the gate electrode, and A step of forming an intermediate insulating film in the step of forming a contact hole in the intermediate insulating film,
And a step of patterning a metal wiring so as to overlap the contact hole, and a plurality of channel impurity forming regions are formed by planarly dividing between the source region and the drain region. And the manufacturing method.

(12) Forming a first gate insulating film in the first transistor region, and forming a second gate insulating film having a smaller film thickness than the first gate insulating film in the second transistor region The method of manufacturing a semiconductor device according to (11) includes the steps of: (13) A step of forming a second conductivity type well region on the surface of the semiconductor region including the source / drain regions of the first transistor region, and impurities of the first conductivity type as the source / drain regions of the first transistor region. And a step of doping a second conductivity type impurity as the source / drain regions of the second transistor region.

[0019]

[Operation] Insulated gate field effect transistor (MOSF
The threshold voltage VTH (abbreviated as ET) can be expressed by the following equation. V _TH = φ _MS + (Q _B / C _OX ) + 2φ _f (1) φ _MS is the work function difference between the substrate and the gate electrode. Q _B
Is the depletion charge amount per unit area generated in the channel region. C _ox is the capacitance per unit area of the gate insulating film.

Φ _f is the Fermi level of the substrate. When a plurality of regions having locally different threshold voltages V _T1 and V _T2 are provided in the channel region, the entire threshold voltage V _TH is given by the following equation. V _TH = AV _T1 + BV _T2 (2) A constant of 0 ≦ A and B ≦ 1, which depends on the pattern shape of each region. Therefore, by controlling the constants A and B by the photolithography technique, it is possible to form a plurality of types of threshold voltages on the same substrate by one-time photolithography. However, V _T1 ≤ V _TH ≤ V
Set between _T2 and each local threshold voltage. The local threshold voltage is a threshold voltage that does not depend on the channel size (transistor having a very large size) when the channel region is formed with a uniform impurity concentration, and is a value mathematically derived from the equation (1). .

Further, in MOS transistors having different gate insulating film capacitances (gate insulating film thickness, type of gate insulating film), substrate concentration or φ _MS , different impurity regions are locally formed in the channel region by one photolithography. The target threshold voltage can be obtained by patterning. That is, when different impurity regions are patterned, the threshold voltage is approximated by the following equation.

V _TH = φ _MS + α · (Q _B1 / C _OX ) + β · (Q _B2 / C _OX ) +2 _{φ f} (3) 0 ≦ α + β ≦ 1. Q _B1 and Q _B2 are depletion charge amounts per unit area in the channel depth direction along the depth direction of the substrate from the surfaces of the channel regions of different impurity regions. [phi] _MS and [phi] _f are effective values and can be practically experimentally obtained because there are a plurality of types of impurity concentrations in the channel region. (3)
From the formula, for example, in each transistor having different gate insulating films, by patterning the impurities in the channel region, it is possible to control the threshold voltage to be almost the same by one photolithography. Further, even in N-type and P-type MOSFETs provided on the same substrate, the threshold voltage can be controlled to be substantially the same on the enhance side by the same means.

That is, an integrated circuit having the following features can be formed by one-time photolithography. (1) Multiple types (at least 3 types or more on the same substrate,
It is possible to easily form a MOS transistor having five or more kinds of threshold voltages depending on the application.

(2) It is possible to control the threshold voltages of MOS transistors having different gate insulating film thicknesses or different types of gate insulating films so that the threshold voltage values are substantially the same in the level direction. (3) The threshold voltages of MOS transistors having different substrate densities can be controlled to values in the substantially same level direction.

(4) It is possible to control the threshold voltages of MOS transistors having different gate electrode concentrations or materials so that they are in the same level direction. (5) Different conductivity types (eg NMOSFET and PMOS)
It is possible to control the absolute value of the threshold voltage of the transistor (FET) to almost the same value in the level direction.

(6) High voltage MOSF with thick gate insulating film
It is possible to control the threshold voltage of each of the low voltage MOSFETs of ET and the thin gate insulating film to the same level direction value. (7) A plurality of different threshold voltages of the transistor of the digital circuit unit whose output voltage is almost the power supply voltage or the ground level and the transistor of the analog circuit unit whose output voltage is the intermediate voltage between the power supply voltage and the ground level are different. You can control the value.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a MOS according to a first embodiment of the present invention.
It is a schematic plan view showing a transistor.

If the MOS transistor of the first embodiment is an N-type MOS transistor formed on a P-type semiconductor substrate, the impurity concentration of the channel region 104 having the first impurity concentration depends on the P-type semiconductor substrate, The impurity concentration of the channel region 105 having the impurity concentration of 2 is determined by introducing the impurity into the region selected by the resist patterned by the impurity introducing mask pattern 106 by ion implantation or the like. Since the pattern 106 is drawn in a plurality of strip shapes in a direction parallel to the channel length of the transistor, the impurities introduced to form the channel region having the second impurity concentration are also parallel to the channel length of the transistor. Introduced in strips of direction.

As a result, the first impurity-concentration channel region 104 and the second impurity-concentration channel region 105 are formed in a plurality of strips in a direction parallel to the channel length. Furthermore, the width 107 of the impurity introducing mask pattern
The area ratio of the channel region having the second impurity concentration with respect to the entire surface of the channel region is determined to be a desired value by the combination of and the interval 108 of the impurity introducing mask pattern. Also,
Even if the area ratio is the same, the width 107 of the impurity introducing mask pattern and the size of the space 108 may be different.

The region of the second impurity concentration is generally formed in the channel doping process. The impurity distribution is changed by the subsequent heat treatment. However, the depth thereof is at least shallower than the junction depth of the source region 102 and the drain region 103. By making the depth of the region having the second impurity concentration shallower, the threshold control accuracy can be increased.

FIG. 2 is a sectional view of an integrated circuit type semiconductor device according to the present invention. An N well having a depth of about 1 to 5 μm is formed on the surface of the P type silicon substrate 1. A PMOSFET is formed in the N well. NMO is formed on the surface of the P-type silicon substrate 1 on which the N well 2 is not formed.
The SFET is formed. The NMOSFET is separated from the N-type source region 4A and the channel region by the N-type drain region 4A.
B is provided. Source region 4A and drain region 4
In the channel region, which is the surface of the substrate 1 between B and
The channel impurity regions 7 similar to those in the above embodiment are provided in a dot shape by being divided into a plurality of planes. A gate electrode 4C is provided on the surface of the channel region via a gate oxide film 6. Similarly, the PMOSFET is also formed with the opposite conductivity type.

Further, the ratio of the channel impurity region of the PMOSFET to the total channel region is formed in a pattern different from that of the NMOSFET in order to obtain a desired aim value. For example, each threshold voltage when the channel impurity region 7 is not provided is 0.2 V (NMOSFET) and −
In the case of 1.5V (PMOSFET), in order to control each threshold voltage to 0.6V and -0.6V, boron is used as an impurity element under the ion implantation condition of 40 keV 4 × 10 11 cm ^-2 , and the entire surface of the channel region of the PMOSFET. To NM
In the OSFET, a channel region having an area ratio of 1/5 was selectively implanted. That is, the threshold voltage of MOSFETs having different conductivity types can be controlled to a desired value by forming the resist pattern once and performing ion implantation using the resist pattern as a mask. As shown in FIG. 2, ion implantation may be performed in the channel regions of the respective FETs at different area ratios, but generally, only one of them has an area ratio of 0 or 1.
To The other one FET controls the threshold value by an intermediate value between the area ratios of 0 and 1.

The second embodiment of FIG. 2 is a sectional view of the embodiment of the present invention in which the semiconductor regions serving as the substrates of the respective transistors have different conductivity types. Even in the case of semiconductor regions of the same conductivity type, the threshold voltage can be controlled similarly even when the semiconductor regions have different impurity concentrations. For example, although not shown, P
When P wells of the same conductivity type are provided on the substrate and NMOSFETs are formed in the P substrate and P well, respectively, the threshold voltage of the NMOSFET in the P substrate is 0.1V, whereas the threshold voltage of the NMOSFET in the dark P well is 0V. It was 0.3V. In this case, boron ions were entirely implanted into the channel region of the NMOSFET in the P substrate and controlled to 0.6V.
A similar threshold voltage of 0.6 is obtained by ion-implanting the channel region to the NMOSFET in the dense P-well at an area ratio of about 50%.
I was able to obtain V.

The channel impurity region 7 is formed shallower than the source / drain regions, and is generally formed by channel doping, and therefore has an impurity distribution shallower than 1000A. In order to electrically and efficiently use the impurities in the channel impurity region 7 for controlling the threshold voltage, it is desirable to form the impurity to be shallower than the depth of the depletion layer in the channel region formed when the channel regions of the respective MOSFETs are inverted. . Further, in order to improve the controllability of the threshold value, at least five channel impurity regions are provided in the channel region, preferably 1.
It is necessary to provide 0 or more.

Also, the size of the transistor for controlling the threshold voltage by providing a plurality of channel impurity regions in the channel region is at least four times as large as the size of a transistor for which full surface ion implantation is controlled by a conventional method or not for whole surface ion implantation. Requires 10 times or more the area of the channel region. Therefore, as the semiconductor device of the present invention,
A channel region is formed in a uniform impurity region by using the minimum design rule for MOSFETs that constitute a digital circuit that processes only digital signals whose input / output levels are "H" and "L". The MOSFET that constitutes the analog circuit that processes the analog signal whose input / output level is different from the power supply voltage,
It is preferable that the threshold voltage be controlled by forming the transistor by about 10 times or more of the transistor according to the minimum rule and providing a plurality of channel impurity regions in the channel region. In general,
The IC is composed of an analog circuit and a digital circuit. However, the area of the analog circuit is generally small. Therefore, even if the area of the analog circuit is slightly increased, the manufacturing process can be simplified as compared with the conventional method, and the cost can be reduced. In particular, requires a large number of threshold voltages, or
This is very effective when there are many thresholds before channel doping and it is necessary to adjust them.

FIG. 3 is a sectional view of a semiconductor device according to the third embodiment of the present invention. Low voltage MOS transistors (LVMOS) having different gate insulating film thicknesses are formed on the P-type silicon substrate 1.
FET) and high voltage MOS transistor (HVMOSFE
T) is provided. LVMOSFET has power supply voltage 3
In order to operate at V, a thin gate oxide film 22C is formed of a silicon oxide film of about 100A. HVMOSF
The ET has a thick gate oxide film 23C formed of a silicon oxide film of about 1000 A so that it can operate at a voltage (eg, 30 V) higher than the power supply voltage. Also, LVMOS
Since the FET uses an oxide film of 100 A as a gate insulating film, the threshold voltage is controlled to 0.4 V by providing the channel impurity region 22E over the entire surface of the channel region.

On the other hand, since the HVMOSFET has a thick gate insulating film of 1000 A, the threshold voltage changes greatly to 3 V or more when the entire surface is ON-implanted. Therefore, as shown in FIG. 3, only the HVMOSFET is divided into the channel impurity regions 23E at a rate of 10% with respect to the channel area to form 0.8V ± 0.1.
It was possible to control to V. FIG. 3 shows an example of controlling the threshold voltage of MOSFETs having different film thicknesses as the gate insulating film. Although not shown, the same control can be performed by using gate insulating films made of materials having different dielectric constants. For example,
A silicon oxide film may be used as the gate insulating film of the LVMOSFET, and a three-layer composite film of a silicon oxide film, a silicon nitride film, and a silicon oxide film may be used as the gate insulating film of the HVMOSFET.

Even in such a case, the threshold voltage of each transistor can be controlled to a desired value by performing ion implantation once by patterning the channel impurity region as shown in FIG. 4A to 4D are cross-sectional views in order of the processes, for illustrating the method for manufacturing the semiconductor device in FIG.

First, as shown in FIG. 4A, a field oxide film 3 for electrically isolating each transistor.
Are formed on the surface of the substrate 1. Generally, a silicon nitride film is patterned on a P-type silicon substrate through an oxide film by a normal photolithography technique.

Next, by selectively oxidizing the silicon nitride film as a mask film, the field oxide film as shown in FIG. 4A can be patterned. The thick field oxide film 3 is not formed in the region where the silicon nitride film is formed. After the selective oxidation, when the silicon nitride film and the thin oxide film under the silicon nitride film are removed, the silicon surface is exposed only in the transistor region, as shown in FIG.

Next, as shown in FIG. 4B, a gate oxide film 31 of 1000 A is formed at a high temperature of about 1000.degree.
The field oxide film 3 is a thick oxide film of 5000 A or more. 100 in the transistor area that becomes VLMOSFET
In order to form the gate oxide film of A, a resist film 32 is formed in the HVMOSFET region as shown in FIG.
The gate oxide film 31 is removed using the resist film 32 as a mask. Next, similarly, the silicon substrate 1 is oxidized at a high temperature of about 1000 ° C. for a short oxidation time. HVMOSFET
Since the gate oxide film of 1000 A was present in the region (1), the oxide film 33 of 100 A was formed as the gate oxide film only in the region of the LVMOSFET.

Next, as shown in FIG. 4D, a resist film 34 for forming channel impurities is formed. In FIG. 4D, a resist is entirely formed on the LVMOSFET region. On the other hand, in the HVMOSFET region,
A resist window that is divided in a plane so that a plurality of channel impurity regions 36 are formed in the channel region is formed in the plurality of channel regions. Boron ions are ion-implanted using the resist film 34 as a mask.

Next, a gate electrode 35 is formed on each gate insulating film. Although not shown, after the gate electrode 35 is formed, N-type impurity element arsenic ions are implanted by using the gate electrode and the field oxide film as a mask to form each MOS.
The source / drain regions of the FET are formed. Next, Al
An intermediate insulating film for electrically separating the wiring and the gate electrode is formed on the entire surface. Next, contact holes for making contact between each region and the gate electrode and the Al wiring are formed in the intermediate insulating film. Next, the Al wiring is patterned so as to cover the contact hole to manufacture a semiconductor device. The ion implantation process for forming the channel impurity region is performed between the formation of the field oxide film 3 shown in FIG. 4A and the formation of the thick gate oxide film shown in FIG. 4B, or FIG. Of thick gate oxide film and Fig. 4
It may be between the thin gate oxide film forming step (c). If the resist film 34 is formed on the thin oxide film 33, the yield of the insulating film 33 may decrease. Therefore, generally, the ion implantation step is performed between the thick gate oxide film forming step and the thin oxide film forming step.

FIG. 5 shows the SOI (S) of the fourth embodiment of the present invention.
FIG. 9 is a cross-sectional view in order of the steps, for explaining the semiconductor manufacturing using the substrate (abbreviation of ilicon On Insulator). The present invention can increase the effect when the channel region is formed of a silicon thin film as shown in FIG. The silicon thin film can be applied to any of single crystal, polycrystal, and amorphous. By forming the channel region with a thin film, the channel impurity region for controlling the threshold voltage can be effectively controlled. In particular, by forming the thickness of the channel region thinner than the depletion layer at the time of inversion, it is possible to control more effectively. This is because the threshold voltage is mainly affected by the channel impurity region. In the case of a thick substrate that is not an SOI substrate, a large amount of charges in the depletion layer when being inverted are formed under the inversion layer. S
In the OI substrate, the depletion charge amount is small because the channel region is thinner than the depletion layer. The depletion charge amount is a function of the substrate concentration, but since there is no substrate, the threshold voltage is almost controlled by the impurity concentration distribution in the channel region.

The manufacturing method will be described with reference to FIG. 1000 is formed on the surface of the silicon substrate 1 through the oxide film 41 of 1 μm.
A single crystal silicon film 42 of A is provided. A resist pattern 43 for forming a channel impurity region is formed by a normal photolithography technique. MOS
A plurality of windows of resist film are provided in the channel region of the FET. Boron ions are ion-implanted into the single crystal silicon film 42 using the resist film 43 as a mask.

Next, if necessary, as shown in FIG. 5B, the impurity distribution is uniformly averaged by thermally diffusing boron at a high temperature of about 1000.degree. Next, a resist film 46 is formed on the transistor region by a normal photolithography process.
Are patterned to form isolation regions. In FIG. 4C, the silicon films 44 and 45 having different impurity concentration distributions are removed by etching using the resist film 46 as a mask. Separate formation may be performed by selective oxidation.

Next, as shown in FIG. 4D, LVMOSFE
A thin gate insulating film 47 is formed on T and a thick gate oxide film 48 is formed on the HVMOSFET. Next, as shown in FIG. 4E, a gate electrode 49 is formed on each gate insulating film.

Next, as shown in FIG. 4D, the gate electrode 49 is formed.
LNMO by ion-implanting N-type impurities using as a mask
Form SFET and HVNMOSFET. In at least one of the channel regions, a plurality of ion-implanted channel region impurity regions formed by ion implantation in FIG.

In the SOI substrate, the tinel impurity region is not divided but has a uniform distribution on average due to the relationship between the thermal diffusion condition of FIG. 4B and the resist film spacing of FIG. 4A. It can also be formed as a concentration. When it is desired to control the distribution to be uniform, the distance between the resist films may be formed sufficiently smaller than the diffusion length of impurities.

Further, in FIG. 5, an embodiment in the case of an SOI substrate having a very thin semiconductor region of 1000 A has been described. When the thermal diffusion is sufficient, the channel impurity region reaches the bottom of the silicon thin film. In this case, the threshold voltage is mostly controlled mainly by the channel impurity region. That is, when the thickness of the semiconductor region is almost the same as the depth of the channel impurity region, the influence of the depletion layer is small, and thus the controllability of the threshold voltage can be made higher. Further, the effect can be obtained without thinning the silicon thin film as the semiconductor region to the depth of the channel impurity region. At least, if the silicon thin film can be made thinner than the depth of the depletion layer which is the channel region, the influence of the depletion layer will be small and the threshold control sensitivity can be increased. Generally, in an SOI substrate different from the conventional thick semiconductor substrate, 10
A silicon thin film having a thickness of μm or less is used. Also, although not shown, MOs having silicon thin films having different thicknesses are used.
The threshold voltage of the SFET can be easily controlled by the same method. Further, CMOSSOIIC can be formed by the same method.

[0051]

As described above, the present invention has an effect that the following semiconductor device can be easily manufactured by one impurity doping step such as channel doping performed simultaneously. (1) MOSFETs having a great number of kinds of threshold voltages can be formed on the same substrate.

(2) It is possible to form a high voltage MOSFET and a low voltage MOSFET having a threshold voltage of approximately the same level. (3) N-type MOSF having almost the same threshold voltage
ET and P-type MOSFETs can be formed.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a MOS transistor semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a CMOS IC according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a high voltage MOS built-in IC according to a third embodiment of the present invention.

FIG. 4 is an IC with a high withstand voltage MOS according to a third embodiment of the present invention.
FIG. 6 is a cross-sectional view in order of the manufacturing steps.

FIG. 5 is a cross-sectional view in order of the manufacturing steps of the SOI semiconductor device according to the fourth embodiment of the present invention.

6A, 6B and 6C are schematic plan views of a conventional MOS transistor.

FIG. 7 is a schematic cross-sectional view of a conventional MOS transistor.

[Explanation of symbols]

 101 gate electrode 102 source region 103 drain region 104 first impurity concentration channel region 105 second impurity concentration channel region 106 impurity introduction resist mask pattern

Claims (13)

[Claims] 1. A channel region, which is a semiconductor region between the source region and the drain region, and a second conductivity type source / drain region provided in a semiconductor region of the first conductivity type on the surface of the substrate so as to be separated from each other. And an insulated gate electric field comprising a plurality of channel impurity regions for planarly controlling the threshold value, which are provided in the channel region in a plane, and a gate electrode provided on the channel region via a gate insulating film. A semiconductor device comprising an effect transistor (MISFET). 2. The channel impurity region is connected to the source.
The semiconductor device according to claim 1, wherein the semiconductor device is provided shallower than a junction depth of the drain region. 3. The semiconductor device according to claim 1, wherein five or more channel impurity regions are provided. 4. The semiconductor device according to claim 1, wherein a second MISFET having a second gate insulating film having a film thickness different from that of the gate insulating film is provided on the surface of the substrate. 5. A second MISFET is provided in the second semiconductor region provided on the surface of the substrate and having an impurity concentration different from that of the semiconductor region.
13. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 1, further comprising a second MISFET provided on the surface of the substrate and in a second semiconductor region of a second conductivity type having a conductivity type different from that of the semiconductor region. 7. An analog circuit composed of the MISFET and a second circuit having an area smaller than that of the channel region by one digit or more.
2. The semiconductor device according to claim 1, further comprising a digital circuit including a second MISFET having the channel region of 1. and provided on the surface of the substrate. 8. The semiconductor device according to claim 1, wherein the substrate is composed of a semiconductor substrate and an insulating film provided on the semiconductor substrate, and the thickness of the semiconductor region is thinner than 10 μm. . 9. The semiconductor device according to claim 8, wherein the semiconductor region has a thickness equivalent to that of the channel region. 10. The semiconductor device according to claim 8, wherein the thickness of the semiconductor region is the same as the depth of the channel impurity region. 11. A step of forming a field insulating film on a surface of a semiconductor region of a first conductivity type on a surface of a substrate, and a gate insulating film on surfaces of a first transistor region and a second transistor region of the semiconductor region. And a step of forming a resist pattern for forming a channel impurity region on the surface of the first transistor region, and ion-implanting impurities into the surface of the first transistor region using the resist pattern as a mask. Forming the channel impurity region, patterning a gate electrode on the gate insulating film, and forming a second conductive type source / drain on the surface of the first transistor region so as to be partitioned by the gate electrode. Forming a region,
The method includes the steps of forming an intermediate insulating film on the gate electrode, forming a contact hole in the intermediate insulating film, and patterning a metal wiring so as to overlap the contact hole, and the channel A method of manufacturing a semiconductor device, wherein a plurality of impurity formation regions are formed by being planarly divided between the source region and the drain region. 12. A step of forming a first gate insulating film in the first transistor region, and a second gate insulating film having a smaller film thickness than the first gate insulating film in the second transistor region. 12. The method for manufacturing a semiconductor device according to claim 11, further comprising the step of forming. 13. A second surface is formed on the surface of the semiconductor region including the source / drain regions of the first transistor region.
Forming a conductivity type well region; doping a first conductivity type impurity as the source / drain region of the first transistor region; and secondly forming a source / drain region of the second transistor region. The method for manufacturing a semiconductor device according to claim 11, further comprising the step of doping with a conductivity type impurity.