JP2006324442A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a thin film transistor of a different thickness of a gate insulating film, wherein the off leak current of the thin film transistor is restrained without adjusting a gate voltage when in an off state, separately. <P>SOLUTION: The semiconductor device (100) comprises a plurality of thin film transistors (110, 120, 130, 140). A thickness of gate insulating films (116, 126) of the thin film transistors (110, 120) differs from a thickness of gate insulating films (136, 146) of the other thin film transistors (130, 140). Each of the plurality of thin film transistors (110, 120, 130, 140) has the substantially same drain current rising gate voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a plurality of thin film transistors having different gate insulating film thicknesses and a method for manufacturing the same.

  A liquid crystal display device using a thin film transistor (hereinafter referred to as “TFT”) has advantages such as light weight, thinness, and low power consumption, and thus is used for a display of a television, a computer, a portable terminal, and the like. ing. The liquid crystal display device includes an active matrix substrate formed using a glass substrate, and a display portion having a plurality of pixels and a peripheral circuit portion for driving the display portion are integrally formed on the glass substrate. The cost is reduced.

  The display portion and the peripheral circuit portion are provided with a plurality of TFTs as switching elements, but the characteristics required for the TFTs are different. Specifically, it is required that some TFTs in the peripheral circuit portion of the plurality of TFTs can operate at high speed with low power consumption, and TFTs in the display portion and other TFTs in the peripheral circuit portion are required to operate. Therefore, a high breakdown voltage is required to withstand a high voltage. In order to meet such a demand, a semiconductor device including a TFT having a relatively thin gate insulating film and a TFT having a relatively thick gate insulating film is known (for example, Patent Document 1). A TFT having a thin gate insulating film can operate at a relatively high speed, and a TFT having a thick gate insulating film can withstand a relatively high voltage. In this specification, a TFT that can operate at a higher speed due to the relatively thin gate insulating film is referred to as a high-speed driving TFT. A TFT that can withstand a higher voltage due to a relatively thick gate insulating film is referred to as a high withstand voltage TFT. Called.

Another semiconductor device that reduces off-leakage current in the standby state in order to keep power consumption low is also known (for example, Embodiment 3 of Patent Document 2). In this semiconductor device, the threshold voltage of the TFT is adjusted by doping impurities into the channel of the TFT, so-called channel doping. Further, in this semiconductor device, channel doping is performed so that the impurity concentration in the TFT channel is the same, and the absolute value of the threshold voltage in the TFT having a thick gate insulating film is increased. The current is reduced.
JP 2003-332581 A JP 2004-147175 A

  However, in the semiconductor device disclosed in Patent Document 1, the off-leakage current of the high breakdown voltage TFT is large, and the power consumption during standby is large. Hereinafter, with reference to FIG. 19, it will be described that the off-leakage current of the high breakdown voltage TFT is large.

  FIG. 19 is a graph showing a schematic relationship between the gate voltage (Vg) and the drain current (Id) in a general high-speed drive TFT and a high breakdown voltage TFT, and the vertical axis of the graph is the logarithm of the drain current. Here, the gate insulating film of the high-speed driving TFT is thinner than the gate insulating film of the high voltage TFT. Both the high-speed driving TFT and the high breakdown voltage TFT are N-channel TFTs.

  In both the high-speed driving TFT and the high breakdown voltage TFT, the gate voltage increases and the drain current once increases and then exponentially increases. When the gate voltage when the drain current is the smallest is referred to as the drain current rising gate voltage, as shown in FIG. 19, the drain current rising gate voltage of the high breakdown voltage TFT is smaller than the drain current rising gate voltage of the high-speed driving TFT. This is presumably because the thickness of the gate insulating film of the high-speed driving TFT is different from the thickness of the gate insulating film of the high breakdown voltage TFT.

  In the semiconductor device disclosed in Patent Document 1, channel doping is not performed, and the drain current rising gate voltage of the high-speed driving TFT and the drain current rising gate voltage of the high breakdown voltage TFT are both negative. Also, since the drain current rising gate voltage of the high breakdown voltage TFT is smaller than the drain current rising gate voltage of the high-speed driving TFT, the drain current of the high breakdown voltage TFT when the gate voltage is 0 V (that is, the off leakage current of the high breakdown voltage TFT). Becomes larger. In the semiconductor device disclosed in Patent Document 1, since channel doping is not performed, the threshold voltage of the TFT cannot be easily adjusted.

  In the semiconductor device disclosed in Patent Document 2, channel doping is performed so that the impurity concentrations in the channels of a plurality of TFTs are the same, and the absolute value of the threshold voltage of a TFT having a thick gate insulating film is gate-insulated. The off-leak current of a TFT having a thick gate insulating film is reduced by making it larger than the absolute value of the threshold voltage of a TFT having a thin film. However, only by performing channel doping in this way, the drain current rising gate voltage of the high breakdown voltage TFT is different from the drain current rising gate voltage of the high speed driving TFT, so that the off-leakage current of both the high breakdown voltage TFT and the high speed driving TFT is suppressed. Therefore, it is necessary to individually adjust the gate voltage applied to the high voltage TFT and the high-speed driving TFT. In addition, in the semiconductor device disclosed in Patent Document 2, the on-current, particularly the on-current of a TFT having a thick gate insulating film, is reduced, so that the semiconductor device cannot be driven at high speed, and a high voltage is It is necessary to apply to

  An object of the present invention is to provide a semiconductor device in which the thicknesses of gate insulating films of a plurality of TFTs are different and the drain current rising gate voltages of the plurality of TFTs are substantially the same, and a method for manufacturing the same.

  The semiconductor device of the present invention includes a plurality of thin film transistors, and each of the plurality of thin film transistors controls a source, a drain, a channel provided between the source and the drain, and conductivity of the channel. A gate insulating film provided between the channel and the gate electrode, wherein the plurality of thin film transistors includes a first plurality of thin film transistors, The thickness of the gate insulating film of at least one thin film transistor is different from the thickness of the gate insulating film of the other thin film transistors of the first plurality of thin film transistors, and each of the first plurality of thin film transistors is substantially the same. It has a drain current rising gate voltage.

  In one embodiment, the channel of each of the first plurality of thin film transistors is doped with impurities so that the impurity concentration is substantially the same.

  In one embodiment, the first plurality of thin film transistors is one of an N-channel thin film transistor and a P-channel thin film transistor.

  In one embodiment, the plurality of thin film transistors further includes a second plurality of thin film transistors, and the first plurality of thin film transistors is one of an N-channel thin film transistor and a P-channel thin film transistor, The plurality of thin film transistors is the other of an N-channel thin film transistor and a P-channel thin film transistor, and each of the second plurality of thin film transistors has substantially the same drain current rising gate voltage, and the drains of the first plurality of thin film transistors The current rising gate voltage is different from the drain current rising gate voltage of the second plurality of thin film transistors.

  In one embodiment, the thickness of the gate insulating film of at least one thin film transistor of the second plurality of thin film transistors is equal to the thickness of the gate insulating film of another thin film transistor of the second plurality of thin film transistors. In contrast, the channel of each of the second plurality of thin film transistors is doped with an impurity so that the impurity concentration is substantially the same, and the impurity concentration in each channel of the P-channel type thin film transistor is: The impurity concentration in each channel of the N-channel type thin film transistor is lower.

  In one embodiment, each of the plurality of thin film transistors has substantially the same drain current rising gate voltage.

  In one embodiment, the channel of each of the plurality of thin film transistors is doped with impurities so that the impurity concentration is substantially the same.

  In one embodiment, the plurality of thin film transistors further includes a second plurality of thin film transistors, and the first plurality of thin film transistors is one of an N-channel thin film transistor and a P-channel thin film transistor, The plurality of thin film transistors is the other of the N channel type thin film transistor and the P channel type thin film transistor, and the respective channels of the same channel type thin film transistor are doped with impurities so that the impurity concentration is substantially the same.

  In one embodiment, the impurity concentration in each channel of the first plurality of thin film transistors is different from the impurity concentration in each channel of the second plurality of thin film transistors.

  In one embodiment, the drain current rising gate voltage of each of the plurality of thin film transistors is about 0.0V.

  In one embodiment, the work function of the gate electrode of each of the plurality of thin film transistors is different depending on the thickness of the gate insulating film of each of the plurality of thin film transistors.

  In one embodiment, the channel length of each of the first plurality of thin film transistors varies depending on the thickness of the gate insulating film of each of the first plurality of thin film transistors.

  In one embodiment, the source-drain voltage of each of the first plurality of thin film transistors is different depending on the thickness of the gate insulating film of each of the first plurality of thin film transistors.

  A display device of the present invention includes the above-described semiconductor device.

  An integrated circuit of the present invention includes the semiconductor device described above.

  The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device for manufacturing a semiconductor device including a plurality of thin film transistors having a first plurality of thin film transistors, and forming a source and a drain of each of the plurality of thin film transistors. And forming a channel provided between the source and the drain of each of the plurality of thin film transistors so that each of the channels of the plurality of thin film transistors has substantially the same impurity concentration. Doping each channel of the plurality of thin film transistors with an impurity; and forming a gate insulating film for each of the plurality of thin film transistors, wherein at least one of the first plurality of thin film transistors Thin film transistor gate insulating film In the step of forming the gate insulating film so that the thickness is different from the thickness of the gate insulating film of another thin film transistor in the first plurality of thin film transistors, and in each of the plurality of thin film transistors, the gate Forming a gate electrode facing the channel through an insulating film; and making the drain current rising gate voltages of the first plurality of thin film transistors substantially the same.

  In one embodiment, the step of making the drain current rising gate voltages substantially the same includes the step of making the first plurality of thin film transistors when the channel of each of the first plurality of thin film transistors is doped with an impurity having substantially the same impurity concentration. A step of determining the impurity concentration such that the respective drain current rising gate voltages are substantially the same, and the step of doping the channel with the impurity has the impurity concentration so as to be the determined impurity concentration. A step of doping.

  In one embodiment, the step of making the drain current rising gate voltage substantially the same includes the step of setting the drain current rising gate voltage of each of the plurality of thin film transistors to about 0.0V.

  In one embodiment, the step of making the drain current rising gate voltage substantially the same is the step of forming the gate electrode, wherein a work function of each of the plurality of thin film transistors is the work function of each of the plurality of thin film transistors. The step of making it differ according to the thickness of a gate insulating film is included.

  In one embodiment, in the step of making the drain current rising gate voltages substantially the same, in the step of forming the channel, the length of the channel of each of the first plurality of thin film transistors is the first plurality of thin film transistors. The step of making it differ according to the thickness of each said gate insulating film is included.

  In one embodiment, the step of making the drain current rising gate voltages substantially the same includes the step of setting the source-drain voltage of the first plurality of thin film transistors to the thickness of the gate insulating film of each of the first plurality of thin film transistors. The process of changing according to is included.

  According to the present invention, in a semiconductor device having thin film transistors having different gate insulating film thicknesses, it is possible to suppress the off-leak current of the thin film transistors without individually adjusting the gate voltage when being turned off.

(Embodiment 1)
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 of this embodiment. The semiconductor device 100 includes a substrate 151, a base coat 152 provided on the substrate 151, and a plurality of TFTs provided on the base coat 152. The semiconductor device 100 has four types of TFTs. FIG. 1 shows the four types of TFTs, that is, an N-channel type high-speed driving TFT 110, a P-channel type high-speed driving TFT 120, and an N-channel type high-voltage TFT 130. And a P-channel type high breakdown voltage TFT 140.

The N-channel high-speed driving TFT 110 includes a source 111, a source electrode 112 electrically connected to the source 111, a drain 113, a drain electrode 114 electrically connected to the drain 113, and a source 111 and drain 113. A channel 115 provided between the channel 115, a gate electrode 117 for controlling the conductivity of the channel 115, and a gate insulating film 116 provided between the channel 115 and the gate electrode 117. The source 111, the drain 113, and the channel 115 are provided in a semiconductor film made of Si (silicon). The source 111 and the drain 113 are doped with P (phosphorus) which is an N-type impurity, and B (boron) which is a P-type impurity is implanted into the channel 115 (dose) 1.0 × 10 ¹³ cm ^−. Doped with ^two . The thickness of the gate insulating film 116 is 50 nm. As a material for the gate electrode 117, tantalum, which is a metal, is used. The length of the channel 115 is 8 μm. Note that in this specification, the length of a channel may be referred to as a channel length.

  In the N-channel high-speed driving TFT 110, when a gate voltage higher than a predetermined voltage (threshold voltage) is applied to the gate electrode 117, the N-channel high-speed driving TFT 110 transitions from a non-conductive state to a conductive state. When a gate voltage lower than the voltage (threshold voltage) is applied to the gate electrode 117, the N-channel high-speed drive TFT 110 transitions from a conductive state to a non-conductive state. Thus, the conductivity of the channel 115 is controlled in accordance with the voltage applied to the gate electrode 117.

The P-channel type high-speed driving TFT 120 is provided in the same manner as the N-channel type high-speed driving TFT 110 except that impurities doped in the source and drain are different. The source 121 and the drain 123 of the P-channel type high-speed driving TFT 120 are doped with a P-type impurity with an implantation amount of 1.0 × 10 ¹⁵ cm ⁻² . Further, the channel 125 is doped with B (boron), which is a P-type impurity, in the same manner as the channel 115 with an implantation amount of 1.0 × 10 ¹³ cm ⁻² . Therefore, the impurity concentration in the channel 125 is almost the same as the impurity concentration in the channel 115. The thickness of the gate insulating film 126 is also 50 nm like the gate insulating film 116.

  In the P-channel type high-speed driving TFT 120, when a gate voltage that is equal to or lower than a predetermined voltage (threshold voltage) and whose absolute value is larger than the absolute value of the threshold voltage is applied to the gate electrode 127, When the gate voltage higher than a predetermined voltage (threshold voltage) is applied to the gate electrode 127, the P-channel high-speed drive TFT 120 changes from the conductive state to the conductive state. Transition to non-conduction state. As described above, the conductivity of the channel 125 is controlled in accordance with the voltage applied to the gate electrode 127.

The N-channel type high breakdown voltage TFT 130 is provided in the same manner as the N-channel type high-speed driving TFT 110 except that the thickness of the gate insulating film is different. The thickness of the gate insulating film 116 of the N-channel high-speed driving TFT 110 is 50 nm, whereas the thickness of the gate insulating film 136 of the N-channel high-voltage TFT 130 is 100 nm. Also in the N-channel type high breakdown voltage TFT 130, the source 131 and the drain 133 are doped with P (phosphorus) as an N-type impurity, and the channel 135 is injected with an implantation amount of B (boron) as a P-type impurity. Doped with 0 × 10 ¹³ cm ⁻² . Here, the N-channel high breakdown voltage TFT 130 preferably has an LDD structure or a gate overlap LDD structure in order to improve hot carrier deterioration characteristics.

The P-channel type high breakdown voltage TFT 140 is provided in the same manner as the P-channel type high-speed driving TFT 120 except that the gate insulating film has a different thickness. The thickness of the gate insulating film 126 of the P-channel type high-speed driving TFT 120 is 50 nm, whereas the thickness of the gate insulating film 146 of the P-channel type high-voltage TFT 140 is 100 nm. Also in the P-channel type high-voltage TFT 140, the source 141 and the drain 143 are doped with B (boron), which is a P-type impurity, at an injection amount of 1.0 × 10 ¹⁵ cm ⁻² , and the channel 145 has a P-type impurity. Impurity B (boron) is doped with an implantation amount of 1.0 × 10 ¹³ cm ⁻² .

  As described above, in the semiconductor device 100 of this embodiment, the thickness of the gate insulating film 116 of the N-channel type high-speed driving TFT 110 is thinner than the thickness of the gate insulating film 136 of the N-channel type high breakdown voltage TFT 130. The thickness of the gate insulating film 126 of the channel type high-speed driving TFT 120 is thinner than the thickness of the gate insulating film 146 of the P-channel type high voltage TFT 140. As a result, the N-channel high-speed driving TFT 110 and the P-channel high-speed driving TFT 120 can operate at high speed, and the N-channel high-voltage TFT 130 and the P-channel high-voltage TFT 140 are high withstand voltage.

In the semiconductor device 100 of this embodiment, the channel 115, the channel 125, the channel 135, and the channel 145 are doped with the impurity B (boron) having substantially the same implantation amount (here, 1.0 × 10 ¹³ cm ⁻² ). The impurity concentrations in the channel 115, the channel 125, the channel 135, and the channel 145 are almost the same, and the N-channel high-speed driving TFT 110, the P-channel high-speed driving TFT 120, the N-channel high-voltage TFT 130, and the P-channel high-voltage TFT. The respective drain current rising gate voltages of the TFTs 140 are substantially the same. Note that in this specification, the N-channel high-speed driving TFT 110, the P-channel high-speed driving TFT 120, the N-channel high-voltage TFT 130, and the P-channel high-voltage TFT 140 may be collectively referred to simply as TFTs 110 to 140. Each of the TFTs 110 to 140 has a so-called MIS (Metal Insulator Semiconductor) structure.

  In the semiconductor device 100 of the present embodiment, since the drain current rising gate voltages of the TFTs 110 to 140 are substantially the same, the gate voltages applied to the TFTs 110 to 140 are not adjusted individually when being turned off. By applying the same gate voltage, off-leakage current of each of the TFTs 110 to 140 can be suppressed.

  The drain current rising gate voltage is preferably 0V. For example, when the gate voltage in the standby state is 0V, if the drain current rising gate voltage is 0V, the power consumption of the TFT in the standby state can be ideally zero. However, the drain current rising gate voltage may not be 0V. For example, when a TFT is used as a pass transistor or the like, the TFT can be turned off with a gate voltage other than 0V. Note that if the gate voltage in the off state is too large, the drain leakage current induced by the gate voltage increases, so it is preferable to turn off the TFT with a gate voltage as close as possible to the drain current rising gate voltage. . From this point, in this embodiment, since the gate current rising gate voltages of the TFTs 110 to 140 are substantially the same in the TFTs 110 to 140 having different gate insulating film thicknesses, the gate voltages for turning off are individually adjusted. The same power supply voltage can be used as the gate voltage of the TFTs 110 to 140 without doing so.

  Hereinafter, the implantation amount (impurity concentration) in the channel 115, the channel 125, the channel 135, and the channel 145 in the semiconductor device 100 of this embodiment will be described with reference to FIGS.

  First, with reference to FIG. 2, the current rising gate voltage of the TFTs 110 to 140 that are not channel-doped in the semiconductor device 100 of this embodiment will be described.

  FIG. 2A is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel type high-speed driving TFT 110 and the P-channel type high-speed driving TFT 120. In FIG. 2A, a line denoted by reference numeral 110A indicates a result of applying a source-drain voltage of + 8V to the N-channel type high-speed driving TFT 110, and a line denoted by reference numeral 110B is an N-channel type. The result of applying a source-drain voltage of +0.1 V to the high-speed driving TFT 110 is shown. A line denoted by reference numeral 120A indicates a result of applying a source-drain voltage of −8V to the P-channel type high-speed driving TFT 120, and a line denoted by reference numeral 120B is applied to the P-channel type high-speed driving TFT 120. The result of applying a source-drain voltage of −0.1 V is shown.

  As represented by the line denoted by reference numeral 110A in FIG. 2A, in the N-channel high-speed drive TFT 110, when the source-drain voltage is +8 V, the gate voltage increases and the drain current decreases once. , Increase exponentially. If the gate voltage when the drain current is the smallest is called the drain current rising gate voltage, the drain current rising gate voltage is about −1.1V. In this specification, the drain current rising gate voltage may be expressed as VgRise. Further, as represented by the line denoted by reference numeral 110B in FIG. 2A, when the source-drain voltage is + 0.1V, the drain current cannot be measured when the gate voltage is less than about −1.1V. The drain current increases exponentially when the gate voltage is greater than about −1.1V. Therefore, the drain current rising gate voltage of the N-channel type high-speed driving TFT 110 is about −1.1V.

2A, in the P-channel type high-speed drive TFT 120, when the source-drain voltage is -8V, the gate voltage decreases and the drain current temporarily increases. After decreasing, it increases exponentially. In this case, the drain current rising gate voltage is about −1.1V. Also, as shown by the line with reference numeral 120B in FIG. 2A, when the source-drain voltage is -0.1V, the drain current cannot be measured when the gate voltage is greater than -1.1V. When the gate voltage becomes smaller than −1.1V, the drain current increases exponentially. Therefore, the drain current rising gate voltage of the P-channel type high-speed driving TFT 120 is about −1.1 V, which is the same as that of the N-channel type high-speed driving TFT 110. In the N-channel high-speed driving TFT 110 and the P-channel high-speed driving TFT 120, the gate voltage corresponding to the drain current of 1.0 × 10 ⁻⁶ A (1 μA) is the threshold voltage, and the drain current rising gate voltage is The gate voltage in the so-called subthreshold region.

  FIG. 2B is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high voltage TFT 130 and the P-channel high voltage TFT 140. In FIG. 2B, the line denoted by reference numeral 130A indicates the result of applying a source-drain voltage of +8 V to the N-channel type high breakdown voltage TFT 130, and the line denoted by reference numeral 130B is the N-channel type. The result of applying a source-drain voltage of +0.1 V to the high voltage TFT 130 is shown. A line denoted by reference numeral 140A indicates a result of applying a source-drain voltage of −8V to the P-channel type high breakdown voltage TFT 140, and a line denoted by reference numeral 140B is a line applied to the P-channel type high breakdown voltage TFT 140. The result of applying a source-drain voltage of −0.1 V is shown.

  As represented by the line denoted by reference numeral 130A in FIG. 2B, in the N-channel high breakdown voltage TFT 130, when the source-drain voltage is + 8V, the gate voltage increases and the drain current decreases once. , Increase exponentially. In this case, the drain current rising gate voltage is about −1.7V. Further, as represented by the line denoted by reference numeral 130B in FIG. 2B, when the source-drain voltage is + 0.1V, the drain current is not measurable when the gate voltage is less than about −1.7V. The drain current increases exponentially when the gate voltage is greater than about -1.7V. Therefore, the drain current rising gate voltage of the N-channel type high breakdown voltage TFT 130 is about −1.7V.

  2B, in the P-channel type high breakdown voltage TFT 140, when the source-drain voltage is −8V, the gate voltage is decreased and the drain current is once increased. After decreasing, it increases exponentially. In this case, the drain current rising gate voltage is about −1.7V. In addition, as represented by the line denoted by reference numeral 140B in FIG. 2B, when the source-drain voltage is -0.1V, the drain current cannot be measured when the gate voltage is greater than -1.7V. When the gate voltage becomes smaller than −1.7 V, the drain current increases exponentially. Therefore, the drain current rising gate voltage of the P-channel type high breakdown voltage TFT 140 is about −1.7 V, which is the same as that of the N-channel type high breakdown voltage TFT 130.

  Here, FIG. 2A is compared with FIG. When channel doping is not performed, the drain current rising gate voltage of the N-channel high-speed drive TFT 110 and the P-channel high-speed drive TFT 120 is about −1.1 V, whereas the N-channel high-voltage TFT 130 and the P-channel type The drain voltage rising gate voltage of the high voltage TFT 140 is about −1.7V. Thus, when the thicknesses of the gate insulating films are different, the drain current rising gate voltage is different as follows. In a general TFT, a fixed charge exists at the interface between the gate insulating film and silicon, and the influence of this fixed charge on the drain current rising gate voltage increases as the gate insulating film becomes thicker. When positive fixed charges exist, the drain current rising gate voltage shifts to negative as the gate insulating film is thicker. Therefore, the drain current rising gate voltages of the N-channel type high breakdown voltage TFT 130 and the P-channel type high breakdown voltage 140 are different from the drain current rising gate voltages of the N-channel type high-speed driving TFT 110 and P-channel type high-speed driving TFT 120.

Next, referring to FIG. 3, in the semiconductor device 100 of this embodiment, impurities are implanted into the channels 115, 125, 135, and 145 of the TFTs 110 to 140 at a dose of 1.0 × 10 ¹³ cm ^−2. Next, the drain current rising gate voltage will be described.

  FIG. 3A is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel type high-speed driving TFT 110 and the P-channel type high-speed driving TFT 120. In FIG. 3A, a line denoted by reference numeral 110A indicates a result of applying a source-drain voltage of + 8V to the N-channel type high-speed driving TFT 110, and a line denoted by reference numeral 110B is an N-channel type. The result of applying a source-drain voltage of +0.1 V to the high-speed driving TFT 110 is shown. A line denoted by reference numeral 120A indicates a result of applying a source-drain voltage of −8V to the P-channel type high-speed driving TFT 120, and a line denoted by reference numeral 120B is applied to the P-channel type high-speed driving TFT 120. The result of applying a source-drain voltage of −0.1 V is shown.

  As represented by the line denoted by reference numeral 110A in FIG. 3A, in the N-channel high-speed driving TFT 110, when the source-drain voltage is + 8V, the gate voltage increases and the drain current decreases once. , Increase exponentially. In this case, the drain current rising gate voltage is about −0.5V. Further, as represented by the line denoted by reference numeral 110B in FIG. 3A, when the source-drain voltage is + 0.1V, the drain current cannot be measured when the gate voltage is less than about −0.5V. The drain current increases exponentially when the gate voltage is greater than about −0.5V. Therefore, the drain current rising gate voltage of the N-channel type high-speed driving TFT 110 is about −0.5V.

  3A, in the P-channel type high-speed driving TFT 120, when the source-drain voltage is -8V, the gate voltage decreases and the drain current temporarily increases. After decreasing, it increases exponentially. In this case, the drain current rising gate voltage is about −0.5V. Also, as shown by the line with reference numeral 120B in FIG. 3A, when the source-drain voltage is -0.1V, the drain current is not measurable when the gate voltage is greater than -0.5V. When the gate voltage becomes smaller than −0.5V, the drain current increases exponentially. Therefore, the drain current rising gate voltage of the P-channel type high-speed driving TFT 120 is about −0.5 V, which is the same as that of the N-channel type high-speed driving TFT 110.

  FIG. 3B is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high voltage TFT 130 and the P-channel high voltage TFT 140. In FIG. 3B, the line denoted by reference numeral 130A indicates the result of applying a source-drain voltage of + 8V to the N-channel type high breakdown voltage TFT 130, and the line denoted by reference numeral 130B is the N-channel type. The result of applying a source-drain voltage of +0.1 V to the high voltage TFT 130 is shown. A line denoted by reference numeral 140A indicates a result of applying a source-drain voltage of −8V to the P-channel type high breakdown voltage TFT 140, and a line denoted by reference numeral 140B is a line applied to the P-channel type high breakdown voltage TFT 140. The result of applying a source-drain voltage of −0.1 V is shown.

  As represented by the line denoted by reference numeral 130A in FIG. 3B, in the N-channel high breakdown voltage TFT 130, when the source-drain voltage is +8 V, the gate voltage increases and the drain current decreases once. , Increase exponentially. In this case, the drain current rising gate voltage is about −0.5V. Further, as represented by the line denoted by reference numeral 130B in FIG. 3B, when the source-drain voltage is + 0.1V, the drain current cannot be measured when the gate voltage is less than about −0.5V. The drain current increases exponentially when the gate voltage is greater than about −0.5V. Therefore, the drain current rising gate voltage of the N-channel type high breakdown voltage TFT 130 is about −0.5V.

  3B, in the P-channel type high withstand voltage TFT 140, when the source-drain voltage is −8V, the gate voltage decreases and the drain current once increases. After decreasing, it increases exponentially. In this case, the drain current rising gate voltage is about −0.5V. Further, as represented by the line denoted by reference numeral 140B in FIG. 3B, when the source-drain voltage is -0.1V, the drain current cannot be measured when the gate voltage is greater than -0.5V. When the gate voltage becomes smaller than −0.5V, the drain current increases exponentially. Therefore, the drain current rising gate voltage of the P-channel type high breakdown voltage TFT 140 is about −0.5V. This is the same as the N-channel high voltage TFT 130.

  Here, FIG. 3A is compared with FIG. After channel doping, the drain current rising gate voltage of the N-channel high-speed driving TFT 110 and the P-channel high-speed driving TFT 120 is about −0.5 V, whereas the N-channel high-voltage TFT 130 and the P-channel high-voltage TFT The drain current rising gate voltage of the withstand voltage TFT 140 is about −0.5 V, and both are substantially the same. As described above, in the semiconductor device 100 according to the present embodiment, the gate insulating film has different thicknesses because the channel 115, 125, 135, and 145 of the TFTs 110 to 140 are doped with an appropriate amount of impurities. However, the drain current rising gate voltage is almost the same.

  An appropriate implantation amount is determined in advance using another semiconductor device 100X. Hereinafter, the injection amount will be described with reference to FIG.

  In the semiconductor device 100X, a plurality of TFTs including an N-channel TFT and a P-channel TFT are formed, and the thickness of the gate insulating film of the TFT is different every 10 nm. The TFTs of the semiconductor device 100X are formed in the same manner as the TFTs 110 to 140 of the semiconductor device 100. In this semiconductor device 100X, the change in the drain current rising gate voltage is measured by changing the amount of impurities injected into the channel.

FIG. 4 is a graph showing the relationship between the gate insulating film thickness (Tox) and the drain current rising gate voltage (VgRise) in the semiconductor device 100X. In FIG. 4, □ shows the result when channel doping (CD) is not performed, ○ shows the result when the implantation amount of impurity B (boron) is 1.0 × 10 ¹³ cm ⁻² , Δ Shows the result when the implantation amount of impurity B (boron) is 1.8 × 10 ¹³ cm ⁻² . In FIG. 4, □, ○, and Δ indicate the results of both the P-channel TFT and the N-channel TFT, respectively.

As indicated by □ in FIG. 4, when the impurity B (boron) is not doped, the drain current rising gate voltage decreases as the gate insulating film becomes thicker. In the semiconductor device 100X, when the implantation amount of the impurity B (boron) is increased, the drain current rising gate voltage increases, and when the implantation amount is 1.0 × 10 ¹³ cm ⁻² , as indicated by a circle in FIG. Regardless of the thickness of the gate insulating film, the drain current rising gate voltage is almost the same.

In the semiconductor device 100X, when the injection amount is further increased, the drain current rising gate voltage is further increased. When the implantation amount is 1.8 × 10 ¹³ cm ⁻² , the drain current rising gate voltage increases as the gate insulating film becomes thicker, as indicated by Δ in FIG.

Therefore, from FIG. 4, when the implantation amount is an appropriate value (here, 1.0 × 10 ¹³ cm ⁻² ), the drain current rising gate voltage is almost the same regardless of the thickness of the gate insulating film. I understand that. When the implantation amount, that is, the impurity concentration is not an appropriate value, the drain current rising gate voltage changes according to the thickness of the gate insulating film.

  As described above, in general, the influence of the fixed charge changes according to the thickness of the gate insulating film, but in this embodiment, the impurity implantation amount is set to an appropriate value, that is, the impurity concentration in the channel is changed. Since optimization is performed, the drain current rising gate voltage is almost the same regardless of the thickness of the gate insulating film. Therefore, according to the semiconductor device 100 of the present embodiment, the same gate voltage (here, −0.5 V) is applied without individually adjusting the gate voltage applied to the plurality of TFTs when the semiconductor device 100 is turned off. Thus, the off-leak current of each of the TFTs 110 to 140 can be minimized.

  2A corresponds to the reference symbol X1 in FIG. 4, and the result in FIG. 2B corresponds to the reference symbol Y1 in FIG. 3A corresponds to the reference symbol X2 in FIG. 4, and the result in FIG. 3B corresponds to the reference symbol Y2 in FIG.

  Next, with reference to FIGS. 5 and 6, a method for manufacturing the semiconductor device 100 of this embodiment will be described. The semiconductor device 100 of this embodiment is manufactured as follows.

  First, as shown in FIG. 5A, a substrate 151 is prepared. The substrate 151 is, for example, a glass substrate.

  Next, as illustrated in FIG. 5B, the base coat 152 is formed so as to cover the substrate 151, and then the semiconductor film 153 is formed so as to cover the base coat 152. The base coat 152 is made of, for example, silicon oxide, and the semiconductor film 153 is made of polysilicon.

Next, as shown in FIG. 5C, the semiconductor film 153 is doped with P-type impurity B (boron) at an implantation amount of 1.0 × 10 ¹³ cm ⁻² . As will be described later, finally, the source, drain, and channel of the TFTs 110 to 140 are formed using the semiconductor film 153. In order to form the sources and drains of the TFTs 110 to 140, impurities are doped later. However, the channels 115, 125, 135 and 145 of the TFTs 110 to 140 are doped only with the P-type impurity B (boron). The doping of the P-type impurity B (boron) is so-called channel doping.

  Next, as shown in FIG. 5D, the semiconductor film 153 is patterned to form a first semiconductor film 153a, a second semiconductor film 153b, a third semiconductor film 153c, and a fourth semiconductor film 153d.

  Next, as shown in FIG. 5E, a gate insulating film 154 is formed so as to cover the first semiconductor film 153a, the second semiconductor film 153b, the third semiconductor film 153c, and the fourth semiconductor film 153d. The gate insulating film 154 is made of, for example, silicon nitride or silicon oxide.

  Next, as shown in FIG. 5F, the gate insulating film 154 is patterned to form a gate insulating film 154c on a predetermined region of the third semiconductor film 153c, and a predetermined value of the fourth semiconductor film 153d. A gate insulating film 154d is formed over the region.

  Next, as shown in FIG. 5G, the first semiconductor film 153a, the second semiconductor film 153b, the third semiconductor film 153c, the fourth semiconductor film 153d, the gate insulating films 154c and 154d, and the base coat 152 are covered. Further gate insulating film 155 is formed. The gate insulating film 155 is made of, for example, silicon oxide.

  Next, as shown in FIG. 5H, the gate insulating film 155 is patterned. By patterning the gate insulating film 155, a gate insulating film 155a is formed on a predetermined region of the first semiconductor film 153a, and a gate insulating film 155b is formed on a predetermined region of the second semiconductor film 153b. The gate insulating film 155a becomes the gate insulating film 116 of the N-channel type high-speed driving TFT 110, and the gate insulating film 155b becomes the gate insulating film 126 of the P-channel type high-speed driving TFT 120. Further, by patterning the gate insulating film 155, a gate insulating film 155c covering the gate insulating film 154c is formed, and a gate insulating film 155d covering the gate insulating film 154d is formed. The gate insulating film 154c and the gate insulating film 155c become the gate insulating film 136 of the N-channel type high breakdown voltage TFT 130, and the gate insulating film 154d and the gate insulating film 155d become the gate insulating film 146 of the P channel type high breakdown voltage TFT 140.

  Next, as shown in FIG. 6A, the first semiconductor film 153a, the second semiconductor film 153b, the third semiconductor film 153c, the fourth semiconductor film 153d, the gate insulating films 116, 126, 136 and 146, and the base coat 152 are formed. An electrode layer 156 is deposited so as to cover the surface. The electrode layer 156 is made of metal, for example, tungsten.

  Next, as shown in FIG. 6B, the electrode layer 156 is patterned. By patterning the electrode layer 156, an electrode 117 covering the gate insulating film 116 is formed, and an electrode 127 covering the gate insulating film 126 is formed. The electrode 117 becomes the gate electrode 117 of the N-channel type high-speed driving TFT 110, and the electrode 127 becomes the gate electrode 127 of the P-channel type high-speed driving TFT 120. Further, by patterning the electrode layer 156, an electrode 137 covering the gate insulating film 136 is formed, and an electrode 147 covering the gate insulating film 146 is formed. The electrode 137 becomes the gate electrode 137 of the N-channel type high voltage TFT 130 and the electrode 147 becomes the gate electrode 147 of the P-channel type high voltage TFT 140.

Next, as shown in FIG. 6C, the first semiconductor film 153a and the third semiconductor film 153c are covered with a resist mask 161, and B (boron) which is a P-type impurity is doped. B (boron) is doped in a region of the second semiconductor film 153b that is not covered by the electrode 127, and is doped in a region of the fourth semiconductor film 153d that is not covered by the electrode 147. Here, the implantation amount of B (boron) is 1.0 × 10 ¹⁵ cm ⁻² , which is an area of the second semiconductor film 153b covered with the electrode 127 and an electrode of the fourth semiconductor film 153d. More than the amount of impurities implanted into the region covered with 147 (1.0 × 10 ¹³ cm ⁻² ). The region doped with B (boron) at an injection amount of 1.0 × 10 ¹⁵ cm ⁻² in the second semiconductor film 153b becomes the source 121 and the drain 123 of the P-channel type high-speed driving TFT 120, and the injection amount 1 in the fourth semiconductor film 153d. The region doped with B (boron) at 0.0 × 10 ¹⁵ cm ⁻² becomes the source 141 and the drain 143 of the P-channel high voltage TFT 140. Thereafter, the resist mask 161 is removed.

Next, as shown in FIG. 6D, the second semiconductor film 153b and the fourth semiconductor film 153d are covered with a resist mask 162, and P (phosphorus) which is an N-type impurity is doped. P (phosphorus) is doped into a region of the first semiconductor film 153a that is not covered with the electrode 117, and is doped into a region of the third semiconductor film 153c that is not covered with the electrode 137. Here, the injection amount of P (phosphorus) is 1.0 × 10 ¹⁵ cm ⁻² . The region doped with P (phosphorus) in the first semiconductor film 153a becomes the source 111 and the drain 113 of the N-channel high-speed driving TFT 110, and the region doped with P (phosphorus) in the third semiconductor film 153c It becomes the source 131 and the drain 133 of the withstand voltage TFT 130. Thereafter, the resist mask 162 is removed.

  Next, as shown in FIG. 6E, electrodes 112, 114, 122, 124, 132, 134, 142, and 144 are formed by depositing a conductive film and patterning the conductive film. The electrode 112 and the electrode 114 become the source electrode 112 and the drain electrode 114 of the N-channel type high-speed driving TFT 110, respectively. The electrode 122 and the electrode 124 become the source electrode 122 and the drain electrode 124 of the P-channel type high-speed driving TFT 120, respectively. . Similarly, the electrode 132 and the electrode 134 become the source electrode 132 and the drain electrode 134 of the N-channel type high breakdown voltage TFT 130, respectively, and the electrode 142 and the electrode 144 become the source electrode 142 and the drain electrode of the P channel type high breakdown voltage TFT 140, respectively. 144. The semiconductor device 100 is manufactured as described above.

  In the semiconductor device 100, the gate insulating film 136 of the N-channel type high breakdown voltage TFT 130 is composed of two films (gate insulating film 154c and gate insulating film 155c), while the gate insulating film 116 of the N-channel type high-speed driving TFT 110 is 1 Since it consists of two films (gate insulating film 155a), the gate insulating film 136 of the N-channel type high breakdown voltage TFT 130 is thicker than the gate insulating film 116 of the N-channel type high-speed driving TFT 110.

  Similarly, the gate insulating film 146 of the P-channel type high voltage TFT 140 is composed of two films (gate insulating film 154d and gate insulating film 155d), while the gate insulating film 126 of the P-channel type high-speed driving TFT 120 is one film. Since it is made of (gate insulating film 155b), the gate insulating film 146 of the P-channel type high breakdown voltage TFT 140 is thicker than the gate insulating film 126 of the P-channel type high-speed driving TFT 120.

  In order to make the drain current rising gate voltages of TFTs having different gate insulating film thicknesses substantially the same, channel doping is performed so that the impurity concentration in the TFT channel is changed according to the thickness of the gate insulating film. It is also possible. In this case, it is necessary to perform channel doping according to the thickness of the gate insulating film. In addition, it is necessary to perform photolithography for forming a resist mask according to the thickness of the gate insulating film before channel doping.

  However, in the semiconductor device 100 of this embodiment, since the impurity concentration in the channel of the TFT is almost the same, it is only necessary to perform channel doping once, and an increase in manufacturing process and cost can be suppressed.

(Embodiment 2)
In the first embodiment, the drain current rising gate voltage of TFTs having different gate insulating film thicknesses is set to about −0.5 V by setting the amount of impurities implanted into the TFT channel to an appropriate value. However, the present invention is not limited to this.

  Hereinafter, a second embodiment of the semiconductor device 100 according to the present invention will be described with reference to FIGS.

  FIG. 7 is a schematic cross-sectional view of the semiconductor device 100 of the present embodiment. The semiconductor device 100 includes four types of TFTs. FIG. 7 shows four types of TFTs, that is, an N-channel type high-speed driving TFT 110 and a P-channel type, as in FIG. 1 referred to in the first embodiment. A high-speed driving TFT 120, an N-channel high voltage TFT 130, and a P-channel high voltage TFT 140 are shown.

  The semiconductor device 100 of this embodiment has the same configuration as that of the semiconductor device described with reference to FIG. 1 in Embodiment 1 except that the material of the gate electrode is different. Specifically, in the semiconductor device described with reference to FIG. 1 in the first embodiment, the gate electrodes 117, 127, 137, and 147 are made of tantalum, whereas the semiconductor device 100 of the present embodiment. Then, each of the gate electrodes 117A, 127A, 137A, and 147A is formed of tungsten, molybdenum, or a silicide thereof.

  In the semiconductor device 100 of this embodiment, since the drain current rising gate voltages of the TFTs 110 to 140 are substantially the same, even when TFTs having different gate insulating film thicknesses are turned on, The off-leak current of each of the TFTs 110 to 140 can be suppressed without individually adjusting the gate voltage to be applied. In the semiconductor device 100 of the present embodiment, the impurity concentrations in the channels 115, 125, 135, and 145 of the TFTs 110 to 140 are substantially the same, and the gate electrodes 117A, 127A, 137A, and 147A are made of tungsten, molybdenum, or It is formed from the silicide, and the drain current rising gate voltage of each of the TFTs 110 to 140 is about 0.0V. Therefore, according to the semiconductor device 100 of this embodiment, the off-leakage current of the TFTs 110 to 140 can be reduced, and the power consumption during standby can be kept low.

  In the semiconductor device 100 of the present embodiment, an appropriate implantation amount of impurities is channel-doped into the channels 115, 125, 135, and 145 of the TFTs 110 to 140, and the appropriate value of the implantation amount is the same as that of the semiconductor device 100X. It is determined in advance. The semiconductor device 100X has the same configuration as that of the semiconductor device used to obtain an appropriate value of the implantation amount in the first embodiment except that the material of the gate electrode is different. Hereinafter, an appropriate value of the injection amount will be described with reference to FIG.

FIG. 8 is a graph showing the relationship between the gate insulating film thickness (Tox) and the drain current rising gate voltage (VgRise) in the semiconductor device 100X of the present embodiment. In FIG. 8, □ shows the result when channel doping (CD) is not performed, and ○ shows the result of channel doping (CD) with impurity B (boron) with an implantation amount of 1.0 × 10 ¹³ cm ^−2. ing. In FIG. 8, □ and ◯ indicate the results of both the P-channel TFT and the N-channel TFT, respectively.

As indicated by □ in FIG. 8, when channel doping is not performed, the drain current rising gate voltage decreases as the gate insulating film becomes thicker. However, in the semiconductor device 100X, channel doping is performed and the amount of implantation is increased. Then, the drain current rising gate voltage increases, and when the injection amount is 1.0 × 10 ¹³ cm ⁻² , the drain current rising gate voltage is shown regardless of the thickness of the gate insulating film, as shown by the circles in FIG. Are almost the same. At this time, the drain current rising gate voltage is about 0.0V.

Here, FIG. 8 referred to for explaining the present embodiment is compared with FIG. 4 referred to for explaining the first embodiment. In the semiconductor device described in the first embodiment, the drain current rising gate voltage of the TFT having an implantation amount of 1.0 × 10 ¹³ cm ⁻² is about −0.5 V, whereas the semiconductor device 100X in the present embodiment is used. Then, the drain current rising gate voltage of the TFT having the implantation amount of 1.0 × 10 ¹³ cm ⁻² is about 0.0V. As described above, this is because the material of the gate electrode of the TFT of the semiconductor device 100X used in the present embodiment is different from the material of the gate electrode of the TFT of the semiconductor device used in the first embodiment. Specifically, the work functions of the tungsten or molybdenum silicide material of the gate electrode of the semiconductor device of Embodiment 100 are 4.6 eV and 4.8 eV, respectively, while the gate electrode used in the semiconductor device of Embodiment 1 is The work function of the material tantalum is 4.1 eV, and the work function of the material of the gate electrode of the semiconductor device of Embodiment 100 is 0.5 eV higher than the work function of the material of the gate electrode used in the semiconductor device of Embodiment 1. Bigger than that. According to the present embodiment, by increasing the work function of the material of the gate electrode, the drain current rising gate voltage of the semiconductor device 100 of the present embodiment is larger than the drain current rising gate voltage of the semiconductor device of the first embodiment. Become.

  As described above, according to the semiconductor device 100 of this embodiment, since the materials of the gate electrodes 117A, 127A, 137A, and 147A are appropriately selected, the drain current rising gate voltages of the TFTs 110 to 140 are about 0. 0. Thus, the off-leakage current of the TFTs 110 to 140 can be reduced, and the power consumption during standby can be kept low. Also, according to the semiconductor device 100 of this embodiment, since the drain current rising gate voltage is about 0.0 V, the on-current of the TFTs 110 to 140 can be increased, thereby reducing the power consumption during operation. Can be suppressed.

  Next, with reference to FIG. 9, the drain current rising gate voltage of the TFTs 110 to 140 that are not channel-doped in the semiconductor device 100 of this embodiment will be described.

  FIG. 9A is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel type high-speed driving TFT 110 and the P-channel type high-speed driving TFT 120. In FIG. 9A, a line denoted by reference numeral 110A indicates a result of applying a source-drain voltage of +8 V to the N-channel type high-speed driving TFT 110, and a line denoted by reference numeral 110B is an N-channel type. The result of applying a source-drain voltage of +0.1 V to the high-speed driving TFT 110 is shown. A line denoted by reference numeral 120A indicates a result of applying a source-drain voltage of −8V to the P-channel type high-speed driving TFT 120, and a line denoted by reference numeral 120B is applied to the P-channel type high-speed driving TFT 120. The result of applying a source-drain voltage of −0.1 V is shown.

  As shown in FIG. 9A, the drain current rising gate voltage is −0.6 V in the N-channel high-speed driving TFT 110, and the drain current rising gate voltage is −0. 6V.

  FIG. 9B is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high voltage TFT 130 and the P-channel high voltage TFT 140. In FIG. 9B, the line denoted by reference numeral 130A indicates the result of applying a source-drain voltage of +8 V to the N-channel type high breakdown voltage TFT 130, and the line denoted by reference numeral 130B is the N-channel type. The result of applying a source-drain voltage of +0.1 V to the high voltage TFT 130 is shown. A line denoted by reference numeral 140A indicates a result of applying a source-drain voltage of −8V to the P-channel type high breakdown voltage TFT 140, and a line denoted by reference numeral 140B is a line applied to the P-channel type high breakdown voltage TFT 140. The result of applying a source-drain voltage of −0.1 V is shown.

  As shown in FIG. 9B, in the N-channel high voltage TFT 130, the drain current rising gate voltage is about −1.2V. In the P-channel type high breakdown voltage TFT 140, the drain current rising gate voltage is about −1.2V. As is clear from the comparison between FIG. 9A and FIG. 9B, the drain current rising gate voltage is different when the thickness of the gate insulating film is different.

Next, referring to FIG. 10, an impurity is channel-doped with an implantation amount of 1.0 × 10 ¹³ cm ⁻² in each of the channels 115, 125, 135, and 145 of the TFTs 110 to 140 in the semiconductor device 100 of this embodiment. Next, the drain current rising gate voltage will be described.

  FIG. 10A is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel type high-speed driving TFT 110 and the P-channel type high-speed driving TFT 120. In FIG. 10A, the line denoted by reference numeral 110A indicates the result of applying a source-drain voltage of +8 V to the N-channel type high-speed driving TFT 110, and the line denoted by reference numeral 110B is the N-channel type. The result of applying a source-drain voltage of +0.1 V to the high-speed driving TFT 110 is shown. A line denoted by reference numeral 120A indicates a result of applying a source-drain voltage of −8V to the P-channel type high-speed driving TFT 120, and a line denoted by reference numeral 120B is applied to the P-channel type high-speed driving TFT 120. The result of applying a source-drain voltage of −0.1 V is shown.

  As shown in FIG. 10A, the drain current rising gate voltage of the N-channel high-speed drive TFT 110 is about 0.0V. The drain current rising gate voltage of the P-channel type high-speed driving TFT 120 is about 0.0V.

  FIG. 10B is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high voltage TFT 130 and the P-channel high voltage TFT 140. In FIG. 10B, the line denoted by reference numeral 130A indicates the result of applying a source-drain voltage of +8 V to the N-channel type high breakdown voltage TFT 130, and the line denoted by reference numeral 130B is the N-channel type. The result of applying a source-drain voltage of +0.1 V to the high voltage TFT 130 is shown. A line denoted by reference numeral 140A indicates a result of applying a source-drain voltage of −8V to the P-channel type high breakdown voltage TFT 140, and a line denoted by reference numeral 140B is a line applied to the P-channel type high breakdown voltage TFT 140. The result of applying a source-drain voltage of −0.1 V is shown.

  As shown in FIG. 10B, the drain current rising gate voltage of the N-channel type high breakdown voltage TFT 130 is about 0.0V. Further, the drain current rising gate voltage of the P-channel type high breakdown voltage TFT 140 is about 0.0V.

  In the semiconductor device 100 of this embodiment, as is clear from a comparison between FIG. 10A and FIG. 10B, when the impurity is doped so as to have an appropriate impurity concentration, the thickness of the gate insulating film is reduced. Even if they are different, the drain current rising gate voltage is almost the same. At this time, the drain current rising gate voltage of the TFTs 110 to 140 is about 0.0V.

  9A corresponds to the reference symbol X1 in FIG. 8, and the result in FIG. 9B corresponds to the reference symbol Y1 in FIG. 10A corresponds to the reference symbol X2 in FIG. 8, and the result in FIG. 10B corresponds to the reference symbol Y2 in FIG.

  The semiconductor device 100 according to the present embodiment can be manufactured in the same manner as described with reference to FIGS. 5 and 6 in the first embodiment except that the material of the gate electrode is different. The detailed explanation is omitted.

  In the above description, the drain current rising gate voltage is increased by using tungsten or molybdenum silicide instead of tantalum as the material of the gate electrodes 117A, 127A, 137A, and 147A. However, the present embodiment is not limited to this. Not. The drain current rising gate voltage may be increased using a material other than the above-described tungsten or molybdenum silicide, for example, a refractory metal silicide film or metal nitride film such as tungsten silicide or tantalum nitride film. Even in the same electrode material, the work function, the fixed charge amount at the gate insulating film / silicon interface, and the fixed charge amount at the silicon / underlying insulating film interface change depending on the film forming conditions. The current rising gate voltage may be adjusted.

  Alternatively, if for some reason the drain current rise gate voltage of a TFT that has not been channel doped is positive, the drain current rise gate voltage can be changed by changing the film formation conditions in the same manner to change the work function or the fixed charge amount. May be reduced.

  In the semiconductor devices of the first and second embodiments described above, the impurity concentrations in the channels 125 and 145 of the P-channel TFTs 120 and 140 are substantially the same as the impurity concentrations in the channels 115 and 135 of the N-channel TFTs 110 and 130. The drain current rising gate voltage of the P-channel TFTs 120 and 140 is substantially the same as the drain current rising gate voltage of the N-channel TFTs 110 and 130, but the semiconductor device of the present invention is not limited to this. While the drain current rising gate voltage of the same channel type TFT is substantially the same, the drain current rising gate voltage of the P channel type TFTs 120 and 140 may be different from the drain current rising gate voltage of the N channel type TFTs 110 and 130. The reason is as follows.

  Due to variations in the manufacturing process of the semiconductor device 100, the drain current rising gate voltage may fluctuate within the same substrate or between lots. The drain current rising gate voltage of both the P-channel TFT and the N-channel TFT is set to 0.0V. Even if it is going to be done, the drain current rising gate voltage does not become 0.0V, but may vary by about ± 0.5V, for example. At this time, if the drain current rising gate voltage of the N-channel TFT is negative, the off-leak current of the N-channel TFT increases. If the drain current rising gate voltage of the P-channel TFT is positive, the off-leakage of the P-channel TFT is increased. The current increases.

  If the drain current rising gate voltage of the N-channel TFT is made positive, even if the drain current rising gate voltage varies, the off-leak current of the N-channel TFT can be suppressed, and the drain current rising of the P-channel TFT can be suppressed. When the gate voltage is negative, the off-leak current of the P-channel TFT can be suppressed even if the drain current rise gate voltage varies. Therefore, the drain current rising gate voltage of the N-channel TFT is made different from the drain current rising gate voltage of the P-channel TFT to make the drain current rising gate voltage of the N-channel TFT positive, and the drain current of the P-channel TFT. By making the rising gate voltage negative, the off-leakage current of the semiconductor device can be suppressed.

  Further, since the drain current rising gate voltage increases as the impurity concentration of the P-type impurity increases, the impurity concentration in the channels 125 and 145 of the P-channel TFTs 120 and 140 is set in the channels 115 and 135 of the N-channel TFTs 110 and 130. By making the concentration lower than the impurity concentration of N channel, the drain current rising gate voltage of the N-channel TFT can be made positive, and the drain current rising gate voltage of the P channel TFT can be made negative to suppress the off-leak current of the semiconductor device. .

(Embodiment 3)
In the first and second embodiments described above, even if the gate insulating films of the plurality of TFTs of at least the same channel type have different thicknesses, the impurity concentration in the channel of each TFT is appropriately made substantially the same, Although the drain current rising gate voltage of each TFT of at least the same channel type is made substantially the same, the present invention is not limited to this. In addition to making the impurity concentration in the channel substantially the same, other changes may be made to make the drain current rising gate voltage of each TFT substantially the same.

  Hereinafter, a third embodiment of the semiconductor device according to the present invention will be described with reference to FIGS.

  FIG. 11 is a schematic cross-sectional view of the semiconductor device 100 of the present embodiment. The semiconductor device 100 has two types of P-channel TFTs. FIG. 11 shows the two types of P-channel TFTs, that is, the same P as described with reference to FIG. A channel type high-speed driving TFT 120 and a P-channel type high breakdown voltage TFT 140 are shown. In the following description, the P-channel high-speed drive TFT 120 and the P-channel high-voltage TFT 140 may be collectively referred to simply as TFTs 120 and 140 in some cases.

As shown in FIG. 11, in the semiconductor device 100 of this embodiment, the length of the channel 125A of the P-channel type high-speed driving TFT 120 is shorter than the length of the channel 145A of the P-channel type high-voltage TFT 140, and the P-channel type high-speed driving is performed. The semiconductor device described in the first embodiment with reference to FIG. 1 except that the injection amount into each of the channel 125A of the TFT 120 and the channel 145A of the P-channel type high breakdown voltage TFT 140 is 1.4 × 10 ¹³ cm ⁻² . It has the same configuration as the device. Here, the length of the channel 125A of the P-channel type high-speed driving TFT 120 is 2 μm, and the length of the channel 145A of the P-channel type high voltage TFT 140 is 5 μm.

In the semiconductor device 100 of this embodiment, the channel 125A and 145A is doped with the impurity B (boron) at an implantation amount of 1.4 × 10 ¹³ cm ⁻² so that the impurity concentrations in the channels 125A and 145A are substantially the same. ing. In the semiconductor device 100 of the present embodiment, the length of the channel 125A of the P-channel type high-speed driving TFT 120 is the same as that of the P-channel type high-voltage TFT 140 so that the drain current rising gate voltages of the TFTs 120 and 140 are substantially the same. It is shorter than the length of the channel 145A. As described above, since the drain current rising gate voltages of the TFTs 120 and 140 are substantially the same, the gate voltages applied to the TFTs 120 and 140 when the TFTs 120 and 140 are turned off are not individually adjusted. Off-leakage current can be suppressed.

  In addition, according to the semiconductor device 100 of this embodiment, since the drain current rising gate voltage of each of the TFTs 120 and 140 is about 0.0 V, the off-leak current of the TFT is reduced and the power consumption during standby is reduced. Can be suppressed. Further, since the drain current rising gate voltage is about 0.0 V, the on-currents of the TFTs 120 and 140 can be increased, thereby reducing the power consumption during operation.

  In the semiconductor device 100 of this embodiment, the amount of impurities implanted into the channels 125A and 145A of the TFTs 120 and 140 is substantially the same. The impurity implantation amount and the channel length are determined in advance using the semiconductor device 100X.

  In the semiconductor device 100X, a plurality of P-channel TFTs are formed, and the thickness of the gate insulating film of the TFTs is different every 10 nm. The semiconductor device 100X is provided with TFTs having different channel lengths. The TFT of the semiconductor device 100X is formed in the same manner as the TFTs 120 and 140 of the semiconductor device 100. In this semiconductor device 100X, impurities are doped so that the impurity concentrations in the channel are the same, and the drain current rising gate voltage is measured.

  Hereinafter, with reference to FIG. 12, the relationship between the impurity implantation amount and channel length and the drain current rising gate voltage will be described.

  FIG. 12 is a graph showing the relationship between the gate insulating film thickness (Tox) and the drain current rising gate voltage (VgRise) in the P-channel TFT of the semiconductor device 100X.

In the semiconductor device 100X, when the impurity implantation amount into the TFT channel is 1.4 × 10 ¹³ cm ⁻² and the channel length is 5 μm, the gate of the P-channel TFT is shown in FIG. The thicker the insulating film, the higher the drain current rise gate voltage. For example, a drain current rising gate voltage of a P-channel TFT having a gate insulating film thickness of 50 nm is about −0.25 V, and a drain current rising gate of a P-channel TFT having a gate insulating film thickness of 100 nm. The voltage is about 0.0V.

  In the P-channel TFT, when the channel length is shortened, the drain current rising gate voltage shifts in the positive direction. As shown by Δ in FIG. 12, when the channel length of the TFT is 2 μm, the drain current rising gate voltage of the P-channel TFT having the gate insulating film thickness of 50 nm is 100 nm in the gate insulating film thickness. Similar to the drain current rising gate voltage of the P-channel TFT, it becomes about 0.0V.

Therefore, when the amount of impurities implanted into the channel of the P-channel TFT is 1.4 × 10 ¹³ cm ⁻² , the channel length of the P-channel TFT having a gate insulating film thickness of 50 nm is 2 μm, If the channel length of a P-channel TFT with a gate insulating film thickness of 100 nm is 5 μm, the drain current rising gate voltage of the P-channel TFT with a gate insulating film thickness of 50 nm is the thickness of the gate insulating film. Similar to the drain current rising gate voltage of a P-channel TFT having a thickness of 100 nm, it is about 0.0V.

  In the present embodiment, the short channel effect caused by shortening the channel length, specifically, the effect that the drain current rising gate voltage is shifted positively as the channel length is shortened, the drain current rising gate voltage is changed. It is about 0.0V.

  Note that the difference in thickness of the gate insulating film and the difference in channel length have a correlation but do not have a proportional relationship. Specifically, in the graph of FIG. 12, when the thickness of the insulating film of the P-channel TFT is 75 nm, the channel length for setting the drain current rising gate voltage to about 0.0 V is in the range of 2 to 5 μm. However, the intermediate length between the channel length of 2 μm when the insulating film thickness is 50 nm and the channel length of 5 μm when the insulating film thickness is 100 nm is not 3.5 μm.

  As described above, according to the present embodiment, even if the drain current rising gate voltage is not substantially the same only by adjusting the impurity concentration, the drain current rising gate voltage can be reduced by changing the channel length. Can be almost the same.

  The semiconductor device 100 according to the present embodiment is the same as that described with reference to FIGS. 5 and 6 in the first embodiment, except that the channel length of the P-channel TFT differs depending on the thickness of the gate insulating film. Therefore, detailed description is omitted here.

(Embodiment 4)
In Embodiment 3 described above, not only the impurity concentration in the channel is made substantially the same, but also the drain current is changed regardless of the thickness of the gate insulating film by changing the channel length according to the thickness of the gate insulating film. Although the rising gate voltages are substantially the same, the present invention is not limited to this. In addition to making the impurity concentration in the channel substantially the same, other changes may be made to make the drain current rising gate voltage substantially the same.

  A fourth embodiment of the semiconductor device according to the present invention will be described below with reference to FIGS.

  FIG. 13 is a schematic cross-sectional view of the semiconductor device 100 of this embodiment. The semiconductor device 100 has two types of N-channel TFTs. FIG. 13 shows the two types of N-channel TFTs, that is, the same N as described with reference to FIG. A channel type high-speed driving TFT 110 and an N-channel type high breakdown voltage TFT 130 are shown. In the following description, the N-channel high-speed driving TFT 110 and the N-channel high-voltage TFT 130 may be collectively referred to simply as TFTs 110 and 130 in some cases.

In the semiconductor device 100 of this embodiment, the amount of impurities injected into the channels 115 and 135 of the TFTs 110 and ¹³⁰ is 1.4 × 10 ¹³ cm ⁻² , and tungsten is used for the gate electrodes of the TFTs 110 and 130. Except for the semiconductor device described in Embodiment 1 with reference to FIG. In the semiconductor device 100 of this embodiment, the source-drain voltage of the N-channel type high-speed driving TFT 110 is different from the source-drain voltage of the N-channel type high voltage TFT 130. Specifically, the source-drain voltage of the N-channel high-speed driving TFT 110 is 3V, and the source-drain voltage of the N-channel high-voltage TFT 130 is 12V.

  In the semiconductor device 100 of this embodiment, the impurity B (boron) is doped in the respective channels 115 and 135 of the TFTs 110 and 130 so that the impurity concentrations in the channels 115 and 135 are substantially the same. In the semiconductor device 100 of the present embodiment, the source-drain voltage of the N-channel type high breakdown voltage TFT 130 is the source of the N-channel type high-speed driving TFT 110 so that the drain current rising gate voltages of the TFTs 110 and 130 are substantially the same. -It is higher than the drain voltage. According to the present embodiment, since the drain current rising gate voltages of the TFTs 110 and 130 are substantially the same, each gate voltage applied to each N-channel TFT when being turned off can be adjusted without individually adjusting each gate voltage. The off-leakage current of the N-channel TFT can be suppressed.

  Further, according to the semiconductor device 100 of this embodiment, since the drain current rising gate voltage of each of the TFTs 110 and 130 is about 0.0 V, the off-leak current of the TFTs 110 and 130 is reduced, and the power consumption during standby is reduced. Can be kept low. Also, according to the semiconductor device 100 of this embodiment, since the drain current rising gate voltage is about 0.0 V, the on-currents of the TFTs 110 and 130 can be increased, thereby reducing the power consumption during operation. Can be suppressed.

  In the semiconductor device 100 of this embodiment, the impurity concentrations in the channels 115 and 135 of the TFTs 110 and 130 are the same. Impurity implantation amounts and source-drain voltages are determined in advance using the semiconductor device 100X.

  A plurality of N-channel TFTs are formed in the semiconductor device 100X, and the thickness of the gate insulating film of the N-channel TFT differs every 10 nm. The TFT of the semiconductor device 100X is formed in the same manner as the TFTs 110 and 130 of the semiconductor device 100. In the semiconductor device 100X, the applied source-drain voltage is changed. In this semiconductor device 100X, impurities are doped so that the impurity concentrations in the channel are the same, and the drain current rising gate voltage is measured.

  Hereinafter, with reference to FIG. 14, the relationship between the impurity implantation amount and the source-drain voltage and the drain current rising gate voltage will be described.

  FIG. 14 is a graph showing the relationship between the gate insulating film thickness (Tox) and the drain current rising gate voltage (VgRise) in the N-channel TFT of the semiconductor device 100X.

When the impurity implantation amount into the TFT channel in the semiconductor device 100X is 1.4 × 10 ¹³ cm ⁻² and the source-drain voltage is 3 V, as shown by the line in FIG. The thicker the gate insulating film, the higher the drain current rising gate voltage. For example, a drain current rising gate voltage of a TFT having a gate insulating film thickness of 50 nm is about 0.0V, and a drain current rising gate voltage of a TFT having a gate insulating film thickness of 100 nm is about 0.25V. is there.

  When the source-drain voltage applied to the N-channel TFT is increased, the drain current rising gate voltage shifts in the negative direction. As indicated by Δ in FIG. 14, when the source-drain voltage is 12V, the drain current rising gate voltage of the TFT having the gate insulating film thickness of 100 nm is about 0.0V.

Therefore, when the amount of impurities implanted into the channel of the N-channel TFT is 1.4 × 10 ¹³ cm ⁻² , the source-drain voltage of the N-channel TFT having a gate insulating film thickness of 50 nm is 3 V. Assuming that the source-drain voltage of an N-channel TFT having a gate insulating film thickness of 100 nm is 12 V, the drain current rising gate voltage of the N-channel TFT having a gate insulating film thickness of 100 nm is Similar to the drain current rising gate voltage of an N-channel TFT having an insulating film thickness of 50 nm, it is about 0.0V.

  Note that the difference in thickness of the gate insulating film and the difference in source-drain voltage have a correlation, but not a proportional relationship. Specifically, in the graph of FIG. 14, when the insulating film thickness of the N-channel TFT is 75 nm, the source-drain voltage for setting the drain current rising gate voltage to about 0.0 V is 3 to 12 V. Although it is within the range, it becomes 7.5 V which is an intermediate value between 3 V which is a source-drain voltage when the thickness of the insulating film is 50 nm and 12 V which is a source-drain voltage when the thickness of the insulating film is 100 nm. Do not mean.

  As described above, according to the semiconductor device 100 of the present embodiment, even if the drain current rising gate voltage is not substantially the same only by adjusting the impurity concentration, by changing the source-drain voltage, The drain current rising gate voltage can be made substantially the same. In this embodiment, since the drain current rising gate voltage is changed by changing the source-drain voltage applied to the completed N-channel TFT, the drain current rising gate voltage can be easily adjusted. it can.

  Since the semiconductor device 100 of this embodiment can be manufactured in the same manner as described with reference to FIGS. 5 and 6 in the first embodiment, detailed description thereof is omitted here.

  In FIG. 14, the virtual drain current rising gate voltage of the TFT having the insulating film thickness of 0 nm is −0.25 V, whereas in FIG. A virtual drain current rising gate voltage of a TFT having a thickness of 0 nm is about −0.5V. This is because the semiconductor device 100 of this embodiment uses tungsten as the material of the gate electrode, whereas the semiconductor device described in Embodiment 1 uses tantalum as the material of the gate electrode. To do.

(Embodiment 5)
In Embodiments 3 and 4 described above, embodiments in which the drain current rising gate voltages of TFTs having different gate insulating film thicknesses are made substantially the same in any one of an N-channel TFT and a P-channel TFT are described. However, the present invention is not limited to this.
The drain current rising gate voltages of TFTs having different gate insulating film thicknesses in both the N-channel TFT and the P-channel TFT may be made substantially the same.

  A fifth embodiment of the semiconductor device according to the present invention will be described below with reference to FIGS.

  FIG. 15 is a schematic cross-sectional view of the semiconductor device 100 of the present embodiment. The semiconductor device 100 has four types of TFTs. FIG. 15 shows the four types of TFTs described with reference to FIG. 1 in the first embodiment, that is, the N-channel type high-speed driving TFT 110 and the P-channel type. A high-speed driving TFT 120, an N-channel high voltage TFT 130, and a P-channel high voltage TFT 140 are shown.

In the semiconductor device 100 of this embodiment, the amount of impurities injected into the channels 125A and 145A of the P-channel TFTs 120 and 140 is 1.4 × 10 ¹³ cm ⁻² , respectively. The amount of impurities implanted into the channels 115A and 135A is 1.8 × 10 ¹³ cm ⁻² . Tantalum is used for the gate electrodes of the TFTs 110 to 140. In the semiconductor device 100 of this embodiment, the channel length of the N-channel high-speed driving TFT 110 is 4 μm, the channel length of the P-channel high-speed driving TFT 120 is 2 μm, the channel length of the N-channel high-voltage TFT 130 is 4 μm, and the P-channel high-voltage TFT The channel length of the TFT 140 is 6 μm. In the semiconductor device 100 of the present embodiment, the source-drain voltage of the N-channel high-speed driving TFT 110, the P-channel high-speed driving TFT 120, and the P-channel high-voltage TFT 140 is 3V, whereas the N-channel high-voltage driving TFT 120 is 3V. The source-drain voltage of the TFT 130 is 12V.

  In the semiconductor device 100 of the present embodiment, as in the semiconductor device described with reference to the third embodiment, the impurity concentration in the channel 125A of the P-channel high-speed driving TFT 120 is the impurity concentration in the channel 145A of the P-channel high-voltage TFT 140. It is almost the same as the concentration, and the length of the channel 125A of the P-channel type high-speed driving TFT 120 is shorter than the length of the channel 145A of the P-channel type high voltage TFT 140. Note that the source-drain voltages of the TFTs 120 and 140 are the same. Thereby, the drain current rising gate voltages of the TFTs 120 and 140 are substantially the same.

  In the semiconductor device 100 of this embodiment, as in the semiconductor device described with reference to Embodiment 4, the impurity concentration in the channel 115A of the N-channel high-speed driving TFT 110 is equal to the channel 135A of the N-channel high-voltage TFT 130. The source-drain voltage of the N-channel type high breakdown voltage TFT 130 is larger than the source-drain voltage of the N-channel type high-speed driving TFT 110. Thereby, the drain current rising gate voltages of the TFTs 110 and 130 are substantially the same. The channel lengths of the TFTs 120 and 140 are the same.

Further, in the semiconductor device 100 of the present embodiment, the impurity implantation amount (1.8 × 10 ¹³ cm ⁻² ) in the N-channel TFTs 110 and 130 is equal to the impurity implantation amount (1.4 in the P-channel TFTs 120 and 140). × 10 ¹³ cm ⁻² ), the gate insulating film is thin (50 nm), and the drain current rising gate voltage of the N-channel high-speed driving TFT 110 is large (100 nm). It is equal to the drain current rising gate voltage of the P-channel type high voltage TFT 140. Therefore, all the drain current rising gate voltages of the TFTs 110 to 140 are substantially the same, so that the TFTs 110 to 110 can be adjusted without individually adjusting the gate voltages applied to the TFTs 110 to 140 when turning off. The off-leakage current of the TFT 140 can be suppressed.

  Further, according to the semiconductor device 100 of the present embodiment, the drain current rising gate voltage of each of the TFTs 110 to 140 is about 0.0 V, so that the off-leak current of the TFT is reduced and the power consumption during standby is reduced. Can be suppressed. Also, according to the semiconductor device 100 of this embodiment, since the drain current rising gate voltage is about 0.0 V, the on-current of the TFTs 110 to 140 can be increased, thereby reducing the power consumption during operation. Can be suppressed.

In the semiconductor device 100 of the present embodiment, the impurity implantation amounts in the same channel type TFT are substantially the same. Specifically, the impurity implantation amounts into the channels 115A and 135A of the TFTs 110 and 130 have the same value (1.8 × 10 ¹³ cm ⁻² ), and the TFTs 120 and 140 have the channel 125A and 145A into the channels 125A and 145A. The impurity implantation amount is the same value (1.4 × 10 ¹³ cm ⁻² ). The impurity implantation amount, channel length, and source-drain voltage are determined in advance using the semiconductor device 100X.

  A plurality of TFTs including an N-channel TFT and a P-channel TFT are formed in the semiconductor device 100X, and the thickness of the gate insulating film of the TFT is different every 10 nm. The TFTs of the semiconductor device 100X are formed in the same manner as the TFTs 110 to 140 of the semiconductor device 100. The semiconductor device 100X is provided with TFTs having different channel lengths. Further, in the semiconductor device 100X, the applied source-drain voltage is changed. In this semiconductor device 100X, impurities are doped so that the impurity concentrations in the channel are substantially the same, and the drain current rising gate voltage is measured.

  Hereinafter, with reference to FIG. 16, the relationship between the impurity implantation amount, the channel length, the source-drain voltage, and the drain current rising gate voltage will be described.

  FIG. 16A is a graph showing the relationship between the gate insulating film thickness (Tox) and the drain current rising gate voltage (VgRise) in the N-channel TFT of the semiconductor device 100X, and FIG. It is a graph which shows the relationship between the thickness (Tox) of the gate insulating film in P channel type TFT of the semiconductor device 100X, and drain current rising gate voltage (VgRise).

When the channel length of the P-channel TFT is 6 μm, the impurity injection amount into the channel of the P-channel TFT is 1.4 × 10 ¹³ cm ⁻² as shown by the line in FIG. In addition, the thicker the gate insulating film of the P-channel TFT, the higher the drain current rising gate voltage. For example, a drain current rising gate voltage of a P-channel TFT having a gate insulating film thickness of 50 nm is about −0.25 V, and a drain current rising gate of a P-channel TFT having a gate insulating film thickness of 100 nm. The voltage is about 0.0V. On the other hand, when the channel length of the P-channel TFT is 2 μm, as shown by Δ in FIG. 16B, the drain current rising gate voltage of the P-channel TFT having the gate insulating film thickness of 50 nm is about 0. 0.0V. This is because the drain current rising gate voltage is shifted in the positive direction as the channel length of the P-channel TFT is shortened, as described in the third embodiment with reference to FIG. Thus, by shortening the channel length and shifting the drain current rising gate voltage in the positive direction, the drain current rising gate voltages of P-channel TFTs having different gate insulating film thicknesses can be made substantially the same. . Here, the source-drain voltage in the P-channel TFT is 3 V, and the impurity implantation amount is 1.4 × 10 ¹³ cm ⁻² .

On the other hand, when the source-drain voltage of the N-channel TFT is 3 V, the impurity implantation amount into the channel of the N-channel TFT is 1.8 × 10 ¹³ cm ⁻² , as shown in FIG. As shown by the line a), the drain current rising gate voltage increases. For example, a drain current rising gate voltage of a TFT having a gate insulating film thickness of 50 nm is about 0.0V, and a drain current rising gate voltage of a TFT having a gate insulating film thickness of 100 nm is about 0.25V. is there.

On the other hand, when the source-drain voltage of the N-channel TFT is 12 V, the drain current rising gate voltage of the N-channel TFT having a gate insulating film thickness of 100 nm is as shown by Δ in FIG. It is about 0.0V. This is because the drain current rising gate voltage shifts in the negative direction when the source-drain voltage is large in the N-channel TFT as described in the fourth embodiment with reference to FIG. Note that here, the channel length in the N-channel TFT is 4 μm, and the impurity implantation amount is 1.8 × 10 ¹³ cm ⁻² .

Here, comparing the line in FIG. 16A and the line in FIG. 16B, the impurity implantation amount in the P-channel TFT is 1.4 × 10 ¹³ cm ⁻² , whereas N The implantation amount of impurities in the channel type TFT is 1.8 × 10 ¹³ cm ⁻² , so that the drain current rising gate voltage of the N channel type TFT is more shifted in the positive direction.

  As described above, according to the semiconductor device 100 of the present embodiment, the channel length and the source-drain voltage are changed even when the drain current rising gate voltage is not substantially the same only by adjusting the impurity concentration. As a result, the drain current rising gate voltages of TFTs having different gate insulating film thicknesses can be made substantially the same.

  The semiconductor device 100 according to the present embodiment is the same as that described with reference to FIGS. 5 and 6 in the first embodiment, except that the channel length of the P-channel TFT varies depending on the thickness of the gate insulating film. Therefore, detailed description is omitted here.

(Embodiment 6)
Hereinafter, an embodiment in which the semiconductor device described with reference to Embodiments 1 to 5 is used for an active matrix substrate of a display device, for example, a liquid crystal display device, will be described with reference to FIG.

  FIG. 17 is a schematic block diagram of the semiconductor device 100A of the present embodiment. The semiconductor device 100 </ b> A includes a glass substrate 170, a display unit 171, and a peripheral circuit unit 172 provided around the display unit 171. The display unit 171 and the peripheral circuit unit 172 are formed on the glass substrate 170.

  In the display portion 171, a plurality of gate lines 171a, a plurality of data lines 171b, a plurality of TFTs 171c, and a plurality of pixel electrodes 171d are provided. FIG. 17 schematically shows one pixel electrode 171d, a corresponding gate line 171a, a data line 171b, and a TFT 171c. The TFT 171c switches the electrical connection between the pixel electrode 171d and the data line 171b in accordance with the potential of the gate line 171a.

  The peripheral circuit unit 172 includes a gate driver 173, a data driver 174, and a control circuit 175 that controls the gate driver 173 and the data driver 174. The gate driver 173 and the data driver 174 drive the display unit 171. . The gate driver 173 includes a shift register 173a, a level shifter 173b, and an output buffer 173c. The gate driver 174 includes a shift register 174a, a level shifter 174b, and an analog switch 174c.

  FIG. 17 shows only one TFT 171 c in the display portion 171, but a plurality of TFTs are provided in both the display portion 171 and the peripheral circuit portion 172. Among the plurality of TFTs, some TFTs in the peripheral circuit portion 172 are high-speed driving TFTs, and TFTs 171c in the display portion 171 and other TFTs in the peripheral circuit portion 172 are high-voltage TFTs. Further, the TFTs 171c in the display portion 171 are all the same channel type high withstand voltage TFT, for example, an N channel type high withstand voltage TFT so that the operation does not vary. On the other hand, another TFT in the peripheral circuit portion 172 is more specifically provided with a high-speed driving TFT in the shift register 173a and the shift register 174a, and a high-speed driving TFT and a high breakdown voltage in the level shifter 173b and the level shifter 174b. Both TFTs are provided, and a high voltage TFT is provided in the output buffer 173c and the analog switch 174c.

  In the peripheral circuit portion 172, a complementary circuit in which an N-channel TFT and a P-channel TFT are combined is provided as necessary in order to ensure the reliability of the TFT and reduce the power consumption.

  As described above, in the semiconductor device 100A of this embodiment, the display unit 171 and the peripheral circuit unit 172 are integrally provided on one glass substrate 170, so that cost and space can be reduced. Can do. Further, according to the semiconductor device 100A of the present embodiment, the power consumption during standby can be kept low, and the power consumption during operation can be kept low. Furthermore, in the semiconductor device 100A of this embodiment, the TFT in the display portion 171 and the TFT in the peripheral circuit portion 172 can be manufactured with fewer steps.

  In the above description, the liquid crystal display device has been described as an example of the display device, but the present invention is not limited to this. The semiconductor device of the present invention may be applied to any other display device such as an organic EL display device.

(Embodiment 7)
In Embodiment 6 described above, an embodiment in which a semiconductor device is used for a liquid crystal display device has been described, but the present invention is not limited to this. A semiconductor device may be used for the integrated circuit.

  Hereinafter, an embodiment in which a semiconductor device according to the present invention is used in an integrated circuit will be described with reference to FIG.

  FIG. 18 is a schematic block diagram of the semiconductor device 100B of this embodiment. The semiconductor device 100B is used for an integrated circuit. The semiconductor device 100B includes a substrate 180, a low voltage driving unit 181 driven at a lower voltage, and a high voltage driving unit 182 driven at a higher voltage. Both the low voltage driving unit 181 and the high voltage driving unit 182 are provided on the substrate 180.

  Here, a case where the semiconductor device 100B is used as a memory device will be described. In this case, the high voltage driver 182 functions as a memory element (memory), and the low voltage driver 181 functions as a signal processor that processes a signal for the memory element 182. This is because in general, it is necessary to apply a high voltage in order to perform writing and erasing in the memory element 182, and signal processing is required to be performed at a high speed with a low voltage.

  In addition, in the low voltage driving unit 181 and the high voltage driving unit 182, a complementary type in which an N-channel TFT and a P-channel TFT are combined as necessary in order to ensure TFT reliability and reduce power consumption. A circuit is provided.

  As described above, in the semiconductor device 100B of the present embodiment, the low voltage driving unit 181 and the high voltage driving unit 182 are provided on one substrate 180, so that cost reduction and space saving can be achieved. In addition, according to the semiconductor device 100B of the present embodiment, it is possible to reduce power consumption during standby and power consumption during operation. Furthermore, in the semiconductor device 100B of this embodiment, the TFT in the low voltage driving unit 181 and the TFT in the high voltage driving unit 182 can be manufactured with fewer steps.

  In the sixth embodiment and the seventh embodiment described above, the embodiment in which the semiconductor device of the present invention is used for a display device and an integrated circuit has been described, but the present invention is not limited to this. You may use the semiconductor device of this invention for another use.

In the first to seventh embodiments described above, the channel of the TFT is doped with B (boron), which is a P-type impurity, but the present invention is not limited to this. BF ₂ may be used as the P-type impurity.

  Further, in Embodiments 1 to 7 described above, since the drain current rising gate voltage of the TFT not subjected to channel doping was negative, the channel was doped with a P-type impurity. However, the present invention is not limited to this, When the drain current rising gate voltage of a TFT not subjected to channel doping is positive for some reason, channel doping may be performed using an N-type impurity (for example, P (phosphorus) or As (arsenic)).

  In Embodiments 1 to 7 described above, the impurity concentration and drain current rising gate voltage in the channels of all TFTs of the semiconductor device are substantially the same, but the present invention is not limited to this. The semiconductor device includes a first group of TFTs and a second group of TFTs, the impurity concentration in the channel of the TFT and the drain current rising gate voltage are substantially the same in the first group, and in the second group The impurity concentration and drain current rising gate voltage in the channels of all TFTs may be substantially the same.

  In Embodiments 1 to 7 described above, the TFT has been shown to have a top gate structure, but the TFT of the present invention is not limited to this. The TFT may have a bottom gate structure.

  The semiconductor device of the present invention is suitably used for display devices such as liquid crystal display devices and organic EL display devices, and integrated circuits. Even when it is necessary to reduce the power supply voltage applied to the semiconductor device, the drain current rising gate voltage can be easily adjusted, thereby reducing the power consumption during standby of the semiconductor device. , Power consumption during operation can be kept low.

2 is a schematic cross-sectional view of the semiconductor device of Embodiment 1. FIG. (A) is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel type high-speed driving TFT and the P-channel type high-speed driving TFT that are not channel-doped in the semiconductor device of the first embodiment. And (b) shows the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high breakdown voltage TFT and the P-channel high breakdown voltage TFT that are not channel doped in the semiconductor device of the first embodiment. It is a graph. (A) is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high-speed drive TFT and the P-channel high-speed drive TFT after channel doping in the semiconductor device of Embodiment 1. (B) shows the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high-voltage TFT and the P-channel high-voltage TFT after channel doping in the semiconductor device of the first embodiment. It is a graph which shows. 6 is a graph showing the relationship between the thickness (Tox) of the gate insulating film of the semiconductor device and the drain current rising gate voltage (VgRise) in the first embodiment. (A)-(h) is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device of Embodiment 1, respectively. (A)-(e) is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device of Embodiment 1, respectively. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. 10 is a graph showing the relationship between the thickness (Tox) of the gate insulating film of the semiconductor device and the drain current rising gate voltage (VgRise) in the second embodiment. (A) is the graph which shows the relationship between the gate voltage (Vg) and drain current (Id) in the N channel type high speed drive TFT and P channel type high speed drive TFT which are not channel-doping in the semiconductor device of Embodiment 2. And (b) shows the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high breakdown voltage TFT and the P-channel high breakdown voltage TFT that are not channel doped in the semiconductor device of the second embodiment. It is a graph. (A) is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel high-speed drive TFT and the P-channel high-speed drive TFT after channel doping in the semiconductor device of the second embodiment. (B) shows the relationship between the gate voltage (Vg) and the drain current (Id) in the N-channel type high-voltage TFT and the P-channel type high-voltage TFT after channel doping in the semiconductor device of the second embodiment. It is a graph which shows. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. 10 is a graph showing the relationship between the gate insulating film thickness (Tox) and the drain current rising gate voltage (VgRise) in the P-channel TFT of the semiconductor device in Embodiment 3. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. 6 is a graph showing the relationship between the thickness (Tox) of a gate insulating film and the drain current rising gate voltage (VgRise) in an N-channel TFT of a semiconductor device in Embodiment 4. FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. (A) is a graph showing the relationship between the gate insulating film thickness (Tox) and the drain current rising gate voltage (VgRise) in the N-channel TFT of the semiconductor device in Embodiment 5, and (b) is an implementation graph. 16 is a graph showing the relationship between the thickness (Tox) of a gate insulating film and the drain current rising gate voltage (VgRise) in a P-channel TFT of a semiconductor device in Mode 5. FIG. 10 is a schematic block diagram of a semiconductor device according to a sixth embodiment. FIG. 10 is a schematic block diagram of a semiconductor device according to a seventh embodiment. It is a graph which shows the relationship between the gate voltage (Vg) and drain current (Id) in a general high-speed drive TFT and a high voltage | pressure-resistant TFT.

Explanation of symbols

100 Semiconductor device 110, 120, 130, 140 Thin film transistor 111, 121, 131, 141 Source 112, 122, 132, 142 Source electrode 113, 123, 133, 143 Drain 114, 124, 134, 144 Drain electrode 115, 125, 135 145 channel 116, 126, 136, 146 gate insulating film 117, 127, 137, 147 gate electrode

Claims (21)

A semiconductor device comprising a plurality of thin film transistors,
Each of the plurality of thin film transistors includes a source, a drain, a channel provided between the source and the drain, a gate electrode for controlling conductivity of the channel, and between the channel and the gate electrode. And a gate insulating film provided on
The plurality of thin film transistors includes a first plurality of thin film transistors;
The thickness of the gate insulating film of at least one thin film transistor of the first plurality of thin film transistors is different from the thickness of the gate insulating film of other thin film transistors of the first plurality of thin film transistors,
Each of the first plurality of thin film transistors has a substantially same drain current rising gate voltage.   2. The semiconductor device according to claim 1, wherein the channel of each of the first plurality of thin film transistors is doped with an impurity so that an impurity concentration is substantially the same.   2. The semiconductor device according to claim 1, wherein the first plurality of thin film transistors is one of an N-channel thin film transistor and a P-channel thin film transistor. The plurality of thin film transistors further includes a second plurality of thin film transistors,
The first plurality of thin film transistors is one of an N-channel thin film transistor and a P-channel thin film transistor, and the second plurality of thin film transistors is the other of an N-channel thin film transistor and a P-channel thin film transistor,
Each of the second plurality of thin film transistors has substantially the same drain current rising gate voltage;
2. The semiconductor device according to claim 1, wherein drain current rising gate voltages of the first plurality of thin film transistors are different from drain current rising gate voltages of the second plurality of thin film transistors. 3. The thickness of the gate insulating film of at least one thin film transistor of the second plurality of thin film transistors is different from the thickness of the gate insulating film of another thin film transistor of the second plurality of thin film transistors,
The channel of each of the second plurality of thin film transistors is doped with impurities so that the impurity concentration is substantially the same,
The semiconductor device according to claim 4, wherein an impurity concentration in each channel of the P-channel thin film transistor is lower than an impurity concentration in each channel of the N-channel thin film transistor.   The semiconductor device according to claim 1, wherein each of the plurality of thin film transistors has substantially the same drain current rising gate voltage.   The semiconductor device according to claim 6, wherein the channel of each of the plurality of thin film transistors is doped with an impurity so that an impurity concentration is substantially the same. The plurality of thin film transistors further includes a second plurality of thin film transistors,
The first plurality of thin film transistors is one of an N-channel thin film transistor and a P-channel thin film transistor, and the second plurality of thin film transistors is the other of an N-channel thin film transistor and a P-channel thin film transistor,
7. The semiconductor device according to claim 6, wherein each channel of the same channel type thin film transistor is doped with impurities so that the impurity concentration is substantially the same.   The semiconductor device according to claim 8, wherein an impurity concentration in each of the channels of the first plurality of thin film transistors is different from an impurity concentration in each of the channels of the second plurality of thin film transistors.   2. The semiconductor device according to claim 1, wherein the drain current rising gate voltage of each of the plurality of thin film transistors is about 0.0V.   2. The semiconductor device according to claim 1, wherein a work function of each gate electrode of each of the plurality of thin film transistors is different depending on a thickness of the gate insulating film of each of the plurality of thin film transistors.   2. The semiconductor device according to claim 1, wherein the channel length of each of the first plurality of thin film transistors varies depending on the thickness of the gate insulating film of each of the first plurality of thin film transistors.   2. The semiconductor device according to claim 1, wherein a source-drain voltage of each of the first plurality of thin film transistors varies depending on a thickness of the gate insulating film of each of the first plurality of thin film transistors.   A display device comprising the semiconductor device according to claim 1.   An integrated circuit comprising the semiconductor device according to claim 1. A method for manufacturing a semiconductor device for manufacturing a semiconductor device comprising a plurality of thin film transistors having a first plurality of thin film transistors,
Forming a source and a drain of each of the plurality of thin film transistors;
Forming a channel provided between the source and the drain of each of the plurality of thin film transistors, wherein each of the plurality of thin film transistors has the same impurity concentration. Doping each channel of the thin film transistor with an impurity; and
Forming a gate insulating film of each of the plurality of thin film transistors, wherein a thickness of a gate insulating film of at least one thin film transistor of the first plurality of thin film transistors is equal to that of the first plurality of thin film transistors; Forming the gate insulating film differently from the thickness of the gate insulating film of another thin film transistor; and
Forming a gate electrode facing the channel through the gate insulating film in each of the plurality of thin film transistors;
And a step of making the drain current rising gate voltages of the first plurality of thin film transistors substantially the same. The step of making the drain current rising gate voltages substantially the same includes the step of doping each channel of each of the first plurality of thin film transistors with an impurity having substantially the same impurity concentration. Determining the impurity concentration such that current rising gate voltages are substantially the same;
The method of manufacturing a semiconductor device according to claim 16, wherein the step of doping the channel with an impurity includes a step of doping the impurity so that the impurity concentration is determined.   The method of manufacturing a semiconductor device according to claim 16, wherein the step of making the drain current rising gate voltage substantially the same includes the step of setting the drain current rising gate voltage of each of the plurality of thin film transistors to about 0.0V.   In the step of making the drain current rising gate voltages substantially the same, in the step of forming the gate electrode, the work function of the gate electrode of each of the plurality of thin film transistors is the thickness of the gate insulating film of each of the plurality of thin film transistors. The method for manufacturing a semiconductor device according to claim 16, comprising a step of making the difference depending on the thickness.   In the step of making the drain current rising gate voltages substantially the same, in the step of forming the channel, the channel length of each of the first plurality of thin film transistors is the gate of each of the first plurality of thin film transistors. The method of manufacturing a semiconductor device according to claim 16, comprising a step of making the difference according to the thickness of the insulating film.   In the step of making the drain current rising gate voltages substantially the same, the source-drain voltages of the first plurality of thin film transistors are changed in accordance with the thickness of the gate insulating film of each of the first plurality of thin film transistors. The manufacturing method of the semiconductor device of Claim 16 including a process.

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