JP2001093986A - Mos device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a MOS device for improving reliability by reducing the number of processes, especially for controlling threshold. SOLUTION: A p-type well is formed on an n-type silicon substrate and an ion implantation process for controlling threshold is executed to each MOS formation region until a process (e). In the process (e), a polysilicon gate electrode is formed, but no doping is made at this time, and n-type and p-type polysilicon gates are formed at nMOS and pMOS in processes (f) and (g) for forming a source a drain. When the polysilicon gate is n and p types, for example a threshold voltage Vth differs by approximately 1 V according to the work function difference. Therefore, adjustment can be made, so that the threshold voltage Vth is positive (for example, +0.6 V) in the n-poly nMOS indicated by a process (h) for example in the nMOS, and the threshold voltage Vth becomes negative (for example, -0.4 V) in the p-poly nMOS, thus manufacturing two types of transistors of nMOSD and nMOSE by performing one-time ion implantation process for controlling threshold.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a MOS device and a method of manufacturing the same, and more particularly, to a threshold control technique for a MOS device.

[0002]

2. Description of the Related Art Conventionally, threshold value control of a MOS device is usually performed by an ion implantation method. Must be done for This will be described below with reference to examples shown in FIGS.

FIGS. 4 and 5 are diagrams (part 1) and (part 2) for explaining a conventional process for manufacturing a MOS transistor. For example, four types (n-channel / p-channel MOS) are shown.
Here, an enhancement type transistor and a depletion type transistor manufacturing process, respectively, are taken as examples.

Here, a MOS transistor has a gate
It is classified into an enhancement type and a depletion type depending on whether or not a drain current flows when the source-to-source voltage is zero. This depends on the value of the so-called "threshold" voltage (Vth). That is, an n-channel MOS transistor (nMOS) is an enhancement type (hereinafter referred to as nMOSE) if Vth is positive, and a depletion type (hereinafter referred to as nMOSD) if Vth is negative.
It is. On the other hand, a p-channel MOS transistor (pMO
If S), conversely, if Vth is negative, it is an enhancement type (hereinafter, referred to as pMOSE), and if Vth is positive, it is a depletion type (hereinafter, referred to as pMOSD).
It is.

First, in step (a) shown in FIG.
A p-type well 2 is formed in a type silicon substrate 1. Specifically, first, an oxide film (silicon dioxide; SiO ₂ ) is formed on the entire surface of the n-type silicon substrate 1 by a thermal oxidation method.
Next, the oxide film on the region where the p-type well 2 is to be formed is removed by photolithography (exposure, etching, etc.), ion implantation (ion implantation) and drive-in are performed to form the p-type well 2 and finally again. An oxide film is formed.

Next, CVD (Chemical Vapor Depositio)
After a nitride film (Si ₃ N ₄ ) is deposited on the entire surface of the substrate by the n) method, the nitride film 3 is left only in each transistor forming region by photolithography (step (b)).

The LOCOS (Local Oxidation of
In the oxidation process, a thicker oxide film 4 (SiO ₂ ) is formed by a thermal oxidation method using the nitride film 3 as a mask.
Is formed. At this time, an oxide film does not grow in a region covered with the nitride film 3 (Si ₃ N ₄ ). By removing the nitride film 3 (Si ₃ N ₄ ), the state shown in the step (c) is obtained, and the individual transistor formation regions are separated from each other by the thicker oxide film 4 (from the left side in FIG. In order, an nMOSD formation region, an nMOSE formation region, a pMOSD formation region, and a pMOSE formation region.

Next, as shown in steps (d) and (e),
Threshold voltage control is performed by ion implantation. This threshold control ion implantation conventionally required four steps. First, in a step (d), a threshold control step for enhancement type formation is performed. That is, first, as shown in the figure, the substrate is covered with a photoresist 5 except for the nMOSE formation region, and then the photoresist 5 is formed.
Is used as a mask, for example, the threshold Vth is set to +0.6 (V)
Is performed. As described above, in the nMOS, V
If th is positive, it is an enhancement type.

Next, although not shown in the figure, similarly, after covering the substrate with a photoresist except for the pMOSE formation region, using this photoresist as a mask, for example, the threshold Vth is set to -0.6 ( V) ion implantation is performed. As described above, a pMOS becomes an enhancement type if Vth is negative.

Hereinafter, similarly, in step (e), nM
In the OSD formation area, for depletion type formation,
For example, a threshold control ion implantation process for setting the threshold Vth to -0.4 (V) is executed.

Although not shown in the figure, in the same manner, in the pMOSD formation region, a threshold control ion implantation step for setting the threshold Vth to +0.4 (V) for forming a depletion type, for example. Execute

Thus, nMOSE, nMOSD, p
In order to form four types of MOSs, MOSE and pMOSD, an ion implantation process for controlling a threshold value for each of them is required. Therefore, four ion implantation processes are required as described above. The order of the four ion implantation steps is as follows.
The order may not be as described above.

Next, in step (f), polysilicon (polycrystalline silicon) is deposited by a CVD method, and a portion to be a gate is formed by photolithography. At this time, in order to reduce the resistance of the gate, the gate electrode is made n-type (n ++) which is highly doped. As a result, as shown in the step (f), a highly doped n-type polysilicon gate electrode 21 is formed.

Then, ion implantation steps (g) and (h) for forming S / D (source / drain) are performed. For example, as shown in the figure, in step (g), after excluding the nMOS formation region (left side in the figure) with a photoresist 5, ion implantation for S / D (source / drain) formation is performed using the photoresist 5 as a mask. Do. Next, in (h), the pMO
After covering with the photoresist 5 except for the S formation region (left side in the figure), ion implantation for S / D (source / drain) formation is performed using the photoresist 5 as a mask. And
After removing the photoresist 5 entirely, drive-in is performed to form an n + source 7 / drain 8 and a p + source 9 / drain 10 as shown in step (i).

Thereafter, for example, as shown in step (j), C
Steps such as formation of the insulating film 11 by the VD method, formation of a source / drain contact to the insulating film, formation of a metal electrode 12 connected to the source / drain through the contact, and the like are performed.

[0016]

As described above, in the threshold control of a MOS device by the conventional ion implantation method, a process for controlling the threshold is necessary for each type of threshold to be controlled. Becomes For example, nMOSE, nMOSD, pMOSE, pMOSE
In order to form four types of MOS devices called MOSD, an ion implantation process for controlling a threshold value is required for each device, so that four ion implantation processes are required as described above (four times in the figure). Are omitted from the illustration).

In general, the more steps (the more complicated the steps), the lower the reliability of the manufacturing process. Therefore, there is a demand for reducing the number of steps as much as possible.

It is an object of the present invention to provide a method of manufacturing a MOS device which can reduce the number of steps for controlling a threshold value and thereby improve the reliability.

[0019]

According to the method of manufacturing a MOS device according to the present invention, two types of MOs having the same conductivity type and different thresholds on the same semiconductor substrate are used.
In a method of manufacturing a MOS device in which an S transistor is formed, a step of performing ion implantation for threshold value control in each formation region of the two types of MOS transistors on the semiconductor substrate; Forming a non-doped polysilicon gate electrode on the region; and doping the polysilicon gate electrode of the two types of MOS transistors with impurities of different types, so that each formed region has a different shape. Setting a threshold value.

According to the method for manufacturing a MOS device,
For example, an ion implantation process for threshold control is performed once for each of the nMOS and the pMOS, and the nMOS / pMOS
When p-type and n-type polysilicon gate electrodes are formed respectively, two types of threshold values can be provided, respectively, because the work functions are different between p-type and n-type. As described above, if the above-described two ion implantation processes for controlling the threshold value are performed, a total of four types of threshold values can be provided. Can be performed at the same time as the step of ion implantation into the semiconductor device, so that the number of steps as a whole can be reduced. Then, by reducing the number of steps in this way, the reliability of the manufacturing process is improved.

The MO manufactured by the above manufacturing method is
An S device is a MOS device in which two types of MOS transistors having the same conductivity type and different thresholds are formed on the same semiconductor substrate. Are doped with the same type and the same concentration of impurities, and the polysilicon gate electrodes of the two types of MOS transistors are doped with impurities of different types so that the thresholds are different in the respective channel regions. Doped.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. Here, there are p-type and n-type poly-silicon (polycrystalline silicon) which is often used as a MOS gate electrode. However, due to a difference in work function, an MO using a p-type poly-silicon gate electrode is used.
The threshold voltage (Vth) of S (hereinafter, referred to as p-poly gate MOS) and the threshold voltage (Vth) of MOS (hereinafter, referred to as n-poly gate MOS) using an n-type polysilicon gate electrode are as follows. The difference differs by about 1 (V) when the gate oxide film thickness is about several tens (nm). For example, in the case of an nMOS, the threshold voltage (Vth) is higher when p-type polysilicon is used as the gate electrode than when n-type polysilicon is used as the gate electrode. For example, it becomes higher by about 1 (V).

In the present invention, utilizing this property, the threshold control ion implantation steps (steps (d) and (e) shown in FIGS. It is characterized in that the number of processes is only one. That is, as described above, the threshold voltage (Vth) varies depending on the type (work function) of the gate electrode in addition to being controlled by the ion implantation method. By using this and combining both,
The reference threshold voltage control is performed by ion implantation, and the final threshold voltage (Vth) is determined by this and the work function of the gate electrode. At this time, the polysilicon gate electrode (poly gate) is p-type. The final threshold voltage (Vth) is divided into positive / negative depending on whether it is n-type or n-type. As described above, when the polysilicon gate electrode is used, the threshold voltage (Vth) is about 1 for p-type and n-type.
(V), for example, one of them is Vth = + 0.6
(V), the other can be adjusted so that Vth = −0.4 (V).

In this way, for example, conventionally, for the nMOS, two ion implantation steps, one each for the enhancement type and the depletion type, were required. Only by performing the threshold voltage control as a reference, for example, if Vth = + 0.6 (V) in the p-poly gate MOS as described above, an enhancement type is obtained.
(V) Since Vth = −0.4 (V) due to the difference, it becomes a depletion type. Similarly, the pMOS can have two types of thresholds in one ion implantation process.

As will be described in detail later, an ion implantation process for forming a source / drain (S / D) is used to form p-type and n-type poly gates. As a result, conventionally, nMOSE, nMOSD, pMOSE, pM
MOS for forming four types of MOS transistors of OSD
In the device manufacturing process, the number of processes as a whole can be reduced. If the number of steps is reduced as described above, the reliability of the manufacturing process can be expected to be improved as described above.

Regarding the above, FIGS.
This will be described in more detail with reference to FIG. FIGS. 1 and 2 are views for explaining a manufacturing process of a MOS transistor according to an embodiment of the present invention. As in the conventional example shown in FIGS.
This shows a manufacturing process for forming four types of MOS transistors of MOSE, nMOSD, pMOST, and pMOSD, and the same reference numerals are given to those which may be substantially the same as those shown in FIGS.

The steps (a) to (c) shown in FIG. 1 are the same as the conventional steps (a) to (c) in FIG. 4 and will not be described in detail. In step (b), a p-type well 2 is formed in an n-type silicon substrate 1, and then, in step (b), a nitride film 3 (Si ₃ N ₄ ) is deposited by a CVD (Chemical Vapor Deposition) method. In the LOCOS oxidation step, a thicker oxide film 4 is formed.
(SiO ₂ ) is formed. Thus, the nitride film Si ₃ N ₄
Is removed, the state shown in step (c) is reached, and the individual transistor formation regions are separated from each other by a thick oxide film (nMOSD (n-poly nM
OS) formation region, nMOSE (p-poly nMOS) formation region, pMOSD (p-poly pMOS) formation region, pMOS
E (n-poly pMOS) formation region).

Subsequently, an ion implantation step for controlling the threshold voltage is started (step (d)). This ion implantation step (d)
Then, threshold control (nVth control) is performed on the nMOS formation region (left side in the figure). That is, nMO
After the substrate is covered with the photoresist 5 except for the S formation region, ion implantation is performed using the photoresist 5 as a mask. This ion implantation is performed using a p-poly gate nMO described later.
When S is formed, its threshold value Vth is positive (for example, +
0.5 (V), and when an n-poly gate nMOS is formed, the threshold value Vth is negative (for example, -0.5
(V).

Although not specifically shown, threshold voltage control (pVth control) is similarly performed on the pMOS formation region (right side in the figure). That is, pMOS
After covering the substrate with the photoresist 5 except for the formation area,
Ion implantation is performed using the photoresist 5 as a mask. This ion implantation is performed by a p-poly gate pMOS
Is formed, the threshold value Vth is positive (for example, +0.
5 (V), and when the n-poly gate pMOS is formed, its threshold Vth is negative (for example, -0.5 (V)).
(Near).

Next, in a step (e), a polysilicon (polycrystalline silicon) gate 6 is formed by the CVD method. At this time, the poly gate electrode 6 is not doped with p-type or n-type (an undoped poly gate), and an ion implantation step (step (f)) for forming S / D (source / drain) later , (G)) to form a p-type /
Make it n-type. By doing so, the p-type / n-type 2
Despite the formation of different types of poly gate electrodes 6, the number of steps does not need to be increased.

That is, in the nMOS formation region, n +
The poly gate 6 in the nMOSD formation region and the poly gate 6 in the pMOSE formation region are converted to n by using the ion implantation process (f) for forming the S / D (source 7 / drain 8).
Make it type. The poly gate 6 in the nMOSE formation region
As shown in the figure, the edge portions 6a at both ends thereof are made n-type due to the problem of processing accuracy when covering with the photoresist 5, but this will not affect the threshold Vth control, which will be described in detail later.

Similarly, using the ion implantation step (g) for forming p + S / D (source 9 / drain 10) in the pMOS formation region, the poly gate 6 in the pMOSD formation region and the poly gate 6 in the nMOSE formation region are used. To p
Make it type. Note that, similarly to the above, the edge portion 6a of the poly gate 6 in the pMOSE formation region is made p-type.

As described above, the n-poly nMOS and the p-poly pM
The OS can be created by self-alignment (self-alignment) using its own poly gate electrode 6 as a mask. However, as described above, the p-poly nMOS and n-poly pMOS poly gates 6 have both ends due to processing accuracy problems. , The n-poly gate and the p-poly gate overlap each other. However, this does not affect the threshold voltage Vth.

That is, for example, p
As shown in FIG. 3A, an edge portion 6a at both ends of the poly gate 6 of the poly nMOS becomes an n poly gate. In the case of an nMOS, as described above, the threshold voltage when a p poly gate is used is used. Vthp is higher than the threshold voltage Vthn when using an n-poly gate. on the other hand,
The overall threshold voltage Vth is ultimately determined by the higher threshold voltage Vthp. Therefore, even if the n-poly gates overlap, they do not affect the threshold voltage Vth (the threshold voltage Vthp when a p-poly gate is used).

The same applies to the n-poly pMOS. As shown in FIG. 3B, even if the p-poly gates overlap at both ends, the higher threshold voltage Vthn (pM
There is no problem because it is determined by the OS because positive / negative is considered reversely).

Then, in step (h), by driving in, n + and p + S / Ds (sources 7, 9 / drain 8, 10) are formed as shown in FIG.
Each polysilicon gate electrode 6 is an n-poly gate, a p-poly gate, a p-poly gate, and an n-poly gate in order from the left of the figure. Thereafter, steps such as formation of the insulating film 11 by the CVD method, formation of a source / drain contact on the insulating film, formation of the metal electrode 12 connected to the source / drain via the contact, and the like are performed as in the conventional case. (Step (i)).

As shown in FIG. 2 (i), the MOS devices manufactured by the above-described steps are formed on the same substrate 1 by depletion type and enhancement type n-channel MOS transistors (nMOSD, nMOST).
And depletion-type and enhancement-type p-channel MOS transistors (pMOSD, pMOSE)
Are formed. And nMOSD and nMOS
Each channel region in E is doped with the same type (n-type) and the same concentration of impurities by the ion implantation in the step (d).
Each polysilicon gate electrode in the SE is doped with impurities of different types (n-type and p-type) by the ion implantation in the steps (f) and (g). As a result, as described above, Different threshold voltages Vthn according to the depletion type and the enhancement type,
Vthp is set. Similarly, pMOSD and pM
The same type (p
Type) and doped with the same concentration of impurities,
Polysilicon gate electrodes in pMOSD and pMOSE are also doped with different types of impurities (p-type and n-type), and as a result, similarly, different threshold values according to the enhancement type and the depletion type are also used. Voltages Vthn and Vthp are set.

As described above, in the MOS device of the present invention, the threshold voltage does not differ depending on the type and concentration of the impurity doped in the channel region. Two types of threshold voltages, a depletion type and an enhancement type, are set depending on the type, and a novel threshold control which has not been achieved in the past can be realized.

In the above description of the embodiment, a semiconductor substrate in which a p-type well is formed on an n-type substrate has been described as an example.
Of course, the present invention is not limited to this. For example, a semiconductor substrate in which an n-type well is formed on a p-type substrate may be used.

In the description of the above embodiment, nMOSD, nMOSE, pMOST, and pMOSD
However, the present invention is not limited to this. For example, the present invention can be effectively applied to a device including two types of MOS transistors, an enhancement type and a depletion type. Further, the present invention is not limited to the enhancement type / depletion type, but may be any two types of MOS devices having the same channel type and different threshold voltages, for example, 1 (V) and 0.5 (V). , Is effectively applicable. That is, the present invention can be effectively applied to at least a MOS device in which two types of MOS transistors having the same conductivity type and different thresholds are formed on the same semiconductor substrate. .

[0041]

As described above, according to the present invention, two types of polysilicon gate electrodes (n-type and p-type) are used.
Type), two types of threshold values can be provided. Further, the step of converting the polysilicon gate electrode into an n-type / p-type is performed by an ion implantation step for forming any of the source / drain. Can be used, the number of steps in the entire manufacturing process of the MOS device can be reduced,
Thus, the reliability of the manufacturing process can be improved.

[Brief description of the drawings]

FIG. 1 is a view (No. 1) for explaining a manufacturing process of a MOS transistor according to an embodiment of the present invention;

FIG. 2 is a view (No. 2) for explaining the manufacturing process of the MOS transistor according to the embodiment of the present invention;

3 (a) is a p-poly nMOS, and FIG. 3 (b) is an n-poly pM
FIG. 5 is a diagram for explaining the influence of an OS on a threshold voltage Vth of an overlapped poly gate.

FIG. 4 is a view (No. 1) for explaining a manufacturing process of a conventional MOS transistor.

FIG. 5 is a view (No. 2) for describing a manufacturing step of the conventional MOS transistor.

[Explanation of symbols]

 Reference Signs List 1 n-type silicon substrate 2 p-type well 3 nitride film 4 thick oxide film 5 photoresist 6 polygate electrode 6 a edge 7 source (n +) 8 drain (n +) 9 source (p +) 10 drain (p +) 11 insulating film 12 metal electrode

Claims (3)

[Claims] 1. A method of manufacturing a MOS device, comprising forming two types of MOS transistors having the same conductivity type and different thresholds on the same semiconductor substrate, wherein the two types in the semiconductor substrate are provided. Performing ion implantation for threshold control in each formation region of the MOS transistor; forming an undoped polysilicon gate electrode on each formation region of the MOS transistor; Setting a different threshold value for each forming region by doping the polysilicon gate electrode of the MOS transistor with a different type of impurity. 2. The method according to claim 1, wherein the step of doping the polysilicon gate electrode with an impurity is performed simultaneously with the step of forming a source and a drain of one of the MOS transistors. 3. A MOS device in which two types of MOS transistors having the same conductivity type and different thresholds are formed on the same semiconductor substrate, wherein each channel region in the two types of MOS transistors is provided. Are doped with the same type and the same concentration of impurities. Each of the polysilicon gate electrodes in the two types of MOS transistors has different types of impurities so as to have different thresholds in the respective channel regions. A MOS device, characterized in that is doped.