JPH08204025A - Manufacture of cmos semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a CMOS semiconductor device whose manufacturing process is shortened by a method wherein a gate oxide film which is formed in a first gate oxidation process is etched by making use of a second resist film as a mask and a mask alignment process which is required for setting a threshold voltage at a proper value is reduced as far as possible. CONSTITUTION: While a first resist film 6 is used as a mask, P-type impurities are ion-implanted into a first NMOS transistor formation region, a second NMOS transistor formation region and a part under a field oxide film 4. While the first resist film 6 and the field oxide film 4 are used as a mask, N-type impurities are ion-implanted into the first and second NMOS transistor formation regions. While a second resist film 10 is used as a mask, P-type impurities are ion-implanted into a first PMOS transistor formation region and a first NMOS transistor formation region. While the second resist film 10 is used as a mask, gate oxide films 11, 12 which are formed in a first gate oxidation process are etched. Thereby, a threshold voltage can be set at a proper value, and a mask alignment process can be reduced.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a first PMOS transistor and an NMOS transistor, and a second PMOS transistor and an N transistor having a thicker gate oxide film.
C including a MOS transistor on the same semiconductor substrate
The present invention relates to a method for manufacturing a MOS semiconductor device, and more particularly, to an improvement in the threshold voltage setting methods for the above four types of MOS transistors. Here, the PMOS transistor means a P-channel MOS transistor, and the NMOS transistor means an N-channel MOS transistor.

[0002]

2. Description of the Related Art LSIs tend to shift from the conventional 5V system to 3.3V system as devices are miniaturized. However, at present, for the convenience of interfacing with a 5V LSI, the input / output circuit (I / O) is operated at 5V as usual and the internal circuit is 3.3V.
It is being operated in. In this case, since the voltage applied to the gate oxide film also differs, a gate oxide film which is thin at 3.3 V and relatively thick at 5.5 V is formed in order to realize reliability and high speed of the oxide film. There is a need.

FIG. 11 is a sectional view of a CMOS semiconductor device having such two types of gate oxide films. As is clear from the figure, there are four types of MOS transistors in this type of CMOS semiconductor device. That is, the first PMOS and the first N having a gate oxide film thickness of 110 Å, for example.
Second PM with MOS and gate oxide film thickness of 180Å
OS and second NMOS.

Since the channel conductivity type and the gate oxide film are different in these MOS transistors, the ion species and the implantation amount are individually selected to set the threshold voltage to a desired value by the ion implantation method. It is necessary to.

[0005]

However, in the conventional method for manufacturing a CMOS semiconductor device, when the threshold voltages of four types of MOS transistors are set, ion implantation is selectively performed in each transistor region. The mask alignment process was performed four times. Therefore, there are drawbacks that the manufacturing cost is high and the TAT is long.

[0006]

In order to solve the above-mentioned problems, a method of manufacturing a CMOS semiconductor device according to the present invention comprises a first PMOS transistor and an NMOS transistor, and a second PMOS transistor having a thicker gate oxide film. PMO
In a method of manufacturing a CMOS semiconductor device having an S transistor and an NMOS transistor on the same semiconductor substrate, a step of forming a field oxide film for separating each transistor and a first and a second PMOS transistor forming region are provided. And a step of ion-implanting P-type impurities into the formation regions of the first and second NMOS transistors and under the field oxide film using the first resist film as a mask, and the first resist film and A step of ion-implanting N-type impurities into the formation regions of the first and second NMOS transistors using the field oxide film as a mask, a step of removing the first resist film, and ion-implantation of P-type impurities on the entire surface of the semiconductor substrate. Step, first gate oxidation step, second PMOS transistor and NMO
The step of covering the formation region of the S transistor with the second resist film, and the first P film using the second resist film as a mask.
A step of ion-implanting P-type impurities into the formation region of the MOS transistor and the NMOS transistor, a step of etching the gate oxide film formed in the first gate oxidation step using the second resist film as a mask, and a second resist It has a step of removing the film and a second gate oxidation step.

[0007]

[Operation] According to the method of manufacturing a CMOS semiconductor device described above, the mask alignment process required to set the threshold voltages of the four types of MOS transistors to appropriate values can be minimized.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a CMOS semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. 1. Step of Forming Well Region and Field Oxide Film In FIG. 1, an N well region (2) is formed in a PMOS transistor formation region on a P-type silicon substrate (1) and an NMOS region is formed.
A P well region (3) is formed in the transistor formation region. In this step, the N well region (2) is exposed to phosphorus ions (31
P +) and arsenic ion (75As +) are accelerated at 160
KeV, the implantation amount is 6E12 / cm2 (6E12 means 6 times 10 to the 12th power. The same applies in the following.), And the P well region (2) is
Boron ion (11B +) acceleration voltage 80 KeV, injection amount 4
Ion implantation is performed under the condition of E12 / cm2, and then 1150
It is formed by performing thermal diffusion at 4 ° C. for 4 hours. Next, a field oxide film (4) of about 5000 Å is formed by a selective oxidation method in order to separate each transistor, and a dummy oxide film (5) of about 400 Å is formed in the transistor formation region excluding the field oxide film (4). ) Is formed.

2. FP ion implantation step In FIG. 2, the formation regions of the first and second PMOS transistors are covered with a first resist film (6), and boron ions which are P-type impurities are masked with the first resist film (6). (11B +) is ion-implanted into the formation regions of the first and second NMOS transistors and under the field oxide film (4) under the conditions of an acceleration voltage of 160 KeV and an implantation amount of 5E12 / cm @ 2. This ion implantation is called FP ion implantation.
The injection region of the formation region of the first and second NMOS transistors suppresses the short channel effect as a so-called deep channel dope layer (7), and the injection layer below the field oxide film (4) is a channel stopper layer (8). As a result, the field inversion is prevented.

3. NE ion implantation step In FIG. 3, arsenic ions (75As +), which are N-type impurities, are implanted with the first resist film (6) and the field oxide film (4) as a mask at an acceleration voltage of 160 KeV and an implantation amount of 1.
Ions are implanted into the formation regions of the first and second NMOS transistors under the condition of 0E12 to 1.5E12 / cm 2. This ion implantation is referred to as NE ion implantation.

4. G ion implantation step In FIG. 4, the first resist film (6) is removed, and boron ions (11B +), which is a P-type impurity, are deposited on the entire surface of the silicon substrate (1) at, for example, an acceleration voltage of 30 KeV and an implantation amount of 3.0E.
Ion implantation is performed on the entire surface under the condition of 12 to 4.0E12 / cm2. This ion implantation is called G ion implantation.

5. First Gate Oxidation Step In FIG. 5, the dummy oxide film (5) is removed and 110 Å
A gate oxide film (9) is formed to some extent. 6. GS ion implantation step Referring to FIG. 6, the second PMOS transistor and the NMO are formed.
A second resist film (10) is formed on the formation region of the S transistor.
And using the second resist film (10) as a mask,
Boron ions (11B +), which is a P-type impurity, are ion-implanted into the formation regions of the first PMOS transistor and NMOS transistor under the conditions of an acceleration voltage of 30 KeV and an implantation amount of 1.0E12 to 1.5E12/cm@2. This ion implantation is called GS ion implantation.

7. GS Photo-etching Step In FIG. 7, the gate oxide film (9) formed in the first gate oxidation step is removed by etching using the second resist film (10) as a mask. 8. Second Gate Oxidation Step In FIG. 8, the second resist film (10) is removed and a second gate oxidation step is performed. As a result, the first PMO
A thin gate oxide film (11) of about 110 Å is formed again in the S and NMOS formation regions, and the second PMOS is formed.
And a thick gate oxide film (12) is formed by additional oxidation in the NMOS formation region.

9. Gate Electrode and Source / Drain Forming Step In FIG. 9, the gate electrode (13) is formed on the gate oxide film (11, 12), and the N + type source layer (14) and drain layer (14) of the first and second NMOS are formed. 15), and then the P + type source layer (16) and the drain layer (17) of the first and second PMOSs are formed.

According to the method of manufacturing a CMOS semiconductor device described above, the mask alignment process required to set the threshold voltages of the four types of MOS transistors to appropriate values can be minimized. In particular, according to this embodiment, since the mask aligning process is also used, no dedicated process for setting the threshold voltage is required. Hereinafter, a method of setting the threshold voltage will be described with reference to FIGS. 10 and 11.

First, consider a transistor used for a 5V system. As for the second PMOS, as shown in FIG. 11, only -1.0 V is obtained by only G ion implantation (overall implantation).
Is set to The G, FP, and NE ions are implanted into the second NMOS, but the ion implantation is mainly controlled by the NE ion implantation. As a result, 1.0
It can be set to V. At this time, in the NE ion implantation, since the mask of the FP ion implantation for forming the channel stopper can be used as it is, the mask process is not increased.

Next, consider a 3.3V type transistor. Regarding the first PMOS, the above G ion implantation has been performed. However, since the threshold voltage is too high in this case, additional implantation is performed by GS ion implantation, and the appropriate value of −0.8V is set. There is. At this time, the mask alignment for GS ion implantation is also used as the mask alignment for etching the gate oxide film, so that the number of steps is not increased. As for the first NMOS, as a result of GS ion implantation in the same manner, the threshold voltage increased and was set to an appropriate value of 0.7V.

[0018]

As described above, according to the present invention,
C having MOS transistors having different gate oxide film thicknesses
In the method of manufacturing a MOS semiconductor device, it is possible to set the threshold voltages of four types of MOS transistors to appropriate values without using a special mask alignment process, which leads to a reduction in manufacturing cost and TAT as compared with the conventional method. It can greatly contribute to shortening.

[Brief description of drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a CMOS semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view explaining the method of manufacturing the CMOS semiconductor device according to the embodiment of the present invention.

FIG. 3 is a third cross-sectional view explaining the method of manufacturing the CMOS semiconductor device according to the embodiment of the present invention.

FIG. 4 is a fourth cross-sectional view illustrating the method of manufacturing the CMOS semiconductor device according to the embodiment of the present invention.

FIG. 5 is a fifth cross-sectional view illustrating the method for manufacturing the CMOS semiconductor device according to the embodiment of the present invention.

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the CMOS semiconductor device according to the embodiment of the present invention.

FIG. 7 is a seventh cross-sectional view illustrating the method for manufacturing the CMOS semiconductor device according to the embodiment of the present invention.

FIG. 8 is an eighth cross-sectional view explaining the method for manufacturing the CMOS semiconductor device according to the embodiment of the present invention.

FIG. 9 is a ninth cross-sectional view illustrating the method for manufacturing the CMOS semiconductor device according to the embodiment of the present invention.

FIG. 10 is a diagram showing a relationship between a threshold value of a MOS transistor and an ion implantation amount.

FIG. 11 is a diagram showing a relationship between a threshold value of a MOS transistor and an ion implantation amount.

FIG. 12 is a cross-sectional view illustrating the method of manufacturing the CMOS semiconductor device according to the conventional example.

Claims (1)

[Claims] 1. A first PMOS transistor and an NMO.
In a method of manufacturing a CMOS semiconductor device having an S transistor and a second PMOS transistor and an NMOS transistor having a thicker gate oxide film on the same semiconductor substrate, a step of forming a field oxide film for separating each transistor, The first and second PMOS transistor formation regions
And a step of ion-implanting P-type impurities into the formation regions of the first and second NMOS transistors and below the field oxide film using the first resist film as a mask, and the first resist film and A step of ion-implanting N-type impurities into the formation regions of the first and second NMOS transistors using the field oxide film as a mask, a step of removing the first resist film, and ion-implantation of P-type impurities on the entire surface of the semiconductor substrate. And a first gate oxidation step, a step of covering the formation regions of the second PMOS transistor and the NMOS transistor with a second resist film, and the first PMOS transistor and the first PMOS transistor using the second resist film as a mask. A step of ion-implanting P-type impurities into the formation region of the NMOS transistor, the first resist film as a mask, C for etching the gate oxide film formed in the gate oxidation process, and removing the second resist film, a second gate oxide process, characterized in that it has a
Manufacturing method of MOS semiconductor device.