JPS63119043U - - Google Patents
Info
- Publication number
- JPS63119043U JPS63119043U JP1987011306U JP1130687U JPS63119043U JP S63119043 U JPS63119043 U JP S63119043U JP 1987011306 U JP1987011306 U JP 1987011306U JP 1130687 U JP1130687 U JP 1130687U JP S63119043 U JPS63119043 U JP S63119043U
- Authority
- JP
- Japan
- Prior art keywords
- power line
- light emitting
- emitting diode
- diode elements
- individual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Dot-Matrix Printers And Others (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Exposure Or Original Feeding In Electrophotography (AREA)
Description
第１図は本考案の光プリンタヘツドの一実施例
を示す部分拡大平面図、第２図は第１図のＹ―Ｙ
線断面図、第３図は従来の光プリンタヘツドの部
分拡大平面図、第４図は第３図のＸ―Ｘ線断面図
である。 １：電気絶縁性基板、２：共通電力線、３：個
別駆動線、４：制御信号線、５：個別電力線、６
：発光ダイオード素子、７：スイツチング用集積
回路素子、９：被覆膜、１０：容量素子。
を示す部分拡大平面図、第２図は第１図のＹ―Ｙ
線断面図、第３図は従来の光プリンタヘツドの部
分拡大平面図、第４図は第３図のＸ―Ｘ線断面図
である。 １：電気絶縁性基板、２：共通電力線、３：個
別駆動線、４：制御信号線、５：個別電力線、６
：発光ダイオード素子、７：スイツチング用集積
回路素子、９：被覆膜、１０：容量素子。
Claims (1)
- 電気絶縁性基板の一表面上にａ一対の電極を有
する複数個の発光ダイオード素子と、ｂ該発光ダ
イオード素子の一方の電極に共通に接続される共
通電力線と、ｃ前記発光ダイオード素子の他方の
電極に接続される個別駆動線と、ｄ前記個別駆動
線の他端に接続されるスイツチング用集積回路素
子と、ｅ該集積回路素子に接続される制御信号線
及び個別電力線とを取着形成して成る光プリンタ
ヘツドにおいて、前記共通電力線と個別電力線と
を容量素子を介して接続したことを特徴とする光
プリンタヘツド。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987011306U JPS63119043U (ja) | 1987-01-28 | 1987-01-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987011306U JPS63119043U (ja) | 1987-01-28 | 1987-01-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63119043U true JPS63119043U (ja) | 1988-08-01 |
Family
ID=30798400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987011306U Pending JPS63119043U (ja) | 1987-01-28 | 1987-01-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63119043U (ja) |
-
1987
- 1987-01-28 JP JP1987011306U patent/JPS63119043U/ja active Pending