JPS63118849A - Tracer control system - Google Patents

Abstract

PURPOSE:To accurately grasp the overall working of a processor in case of a fault analysis, etc., by stopping the tracing action of a tracer incorporated to another processor synchronously with a fact that the tracing action of a tracer incorporated to a certain processor is stopped. CONSTITUTION:When a trace stopping indication signal line 5 is activated due to activation of a NOR gate 11 of a processor 1, the trace stopping indications are also given to tracers 20 and 30 of other processors 2 and 3 respectively. Thus the tracing actions are stopped with these processors. While the line 5 is also activated as long as the NOR gates serving as the trace signal generating circuits are active in the processors 2 and 3 even though the gate 11 of the processor 1 is inactive. Therefore a tracer 10 of the processor 1 stops its tracing action. Thus it is possible to accurately grasp the overall system working of a processor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tracer control method, and particularly to a trace stop control method for a built-in tracer that is effective for failure analysis of logical devices.

A conventional trace operation stop control system for such a built-in tracer is implemented using a configuration as shown in FIGS. 3 and 4. FIG. 3 is a system block diagram of the system, and each of the plurality of microprocessors 1, 2, and 3 (three are shown in this example) constituting the data processing device has a tracer 1.
0.20 and 30 respectively, each processor 1
．． Logic signals and various data in 2 and 3 are raced from 1 to 1 every system clock.

FIG. 4 is a specific configuration diagram for controlling the trace operation stop of the tracer 10 in the processor 1 in FIG. In response to the occurrence of a stop event, the negative logic 5TOP signal line becomes active, causing the tracer 10 to stop tracing. Other processors 2 and 3
etc., have exactly the same configuration and operation.

In this way, in the conventional trace stop control method, when an error occurs in each processor, a microinstruction that stops the tracer is executed, or a microinstruction at a specific address is executed, the Only tracers in compatible processors are stopped.

Since each built-in tracer is not stopped synchronously, even if the trace contents of each built-in tracer are read out during failure analysis, the temporal relationship between the trace data of each built-in tracer is not specified. Therefore, it is difficult to accurately grasp the operation of the entire logical processing device including a plurality of processors.

Particularly, in a processing device in which a plurality of processors 1 to 3 are connected to a common bus 4 and operate in close association with each other as shown in FIG. 3, the above drawback becomes fatal. There is.

The present invention has been made in order to eliminate the drawbacks of the conventional method, and its purpose is to stop the tracing of one built-in tracer in synchronization with the tracing of other built-in tracers. It is an object of the present invention to provide a tracer control method that can accurately grasp the system-like movement of the entire processing device during failure analysis, etc. by stopping the processing device.

Structure of the Invention According to the present invention, there is provided a tracer control method in a data processing device having a plurality of built-in tracers, in which when an event that requires stopping the tracing operation for one of the built-in tracers occurs, this method is implemented. When the tracing operation of one tray is stopped, the tracing operation of other built-in tracers is also stopped! A trainer control method characterized by the following features is obtained.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a system block diagram showing an embodiment of the present invention, FIG. 2 is a specific example without showing the details of this embodiment, and FIG.
．． Parts that are equivalent to those in Figure 4 are indicated by the same symbols.

The plurality of processors 1.2 and 3 are connected together to a common bus 4 and operate in close interaction with each other via this common bus 4. Each of these processors 1.2 and 3 is provided with a built-in tracer 10.20 and 30, respectively, and a trace stop instruction signal line 5 is provided in common to all these built-in tracers 10.20 and 30. There is.

As shown in FIG. 2, the built-in tracer 10 in the processor 1
The trace stop signal generating section of the processor 1 consists of a logical NOR gate 11, which includes an error signal detected in the processor 1, a microinstruction (decoded signal) instructing the processor 1 to stop tracing, and a microinstruction at a specific address. An address match signal indicating execution of an instruction, etc. is input to this NOR gate 11. Therefore, when any of these signals becomes active, the output of the NOR gate 11, 5
The TOP instruction signal becomes active and instructs the tracer 10 to stop its tracing operation.

In this case, since the output of the NOR gate 11 is also connected to the trace stop instruction signal line 5, when the output of the NOR gate 11 is activated as described above, the trace stop instruction signal line 5 is also activated at the same time. However, it is assumed that the processors 2 and 3 have exactly the same configuration as the processor 1 shown in FIG. 2, and the output of each Noah gate of the processors 2 and 3 is of the oven collector type. Therefore, if the trace stop instruction signal line 5 is activated due to activation of the NOR gate 11 of the processor 1, a trace stop instruction is also given to the tracers 20 and 30 of the other processors 2 and 3. to stop tracing.

Conversely, even if the NOR gate 11 of the processor 1 is inactive, if a NOR gate, which is a trace signal generation circuit in another processor 2 or 3, becomes active, the trace stop instruction signal line 5 also becomes active. . Therefore, the built-in trace 10 of the processor 1 stops tracing.

In this way, when an event occurs that causes a processor's built-in tracer to stop, it not only stops the tracing operation of that built-in tracer, but also simultaneously stops the tracing operations of the built-in tracers of other processors. Therefore, the movement of the system body of the processing device can be accurately grasped.

Effects of the Invention As described above, according to the present invention, when a trace stop event occurs for the built-in tracer of a certain processor, tracing is also stopped for the built-in tracers of other processors in synchronization with this event. Therefore, when analyzing a failure, etc., it is possible to read the trace contents of the built-in tracer in each processor and accurately understand the operation of the entire logic processing device.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of a trace stop signal generation section in the block of FIG. 1, and FIG. 3 is a system block diagram of a conventional tracer control method. FIG. 4 is a diagram showing a specific example of the trace stop signal generating section in the block of FIG. 3. Explanation of symbols of main parts 1.2.3...Processor 5...Trace stop instruction signal line

Claims (1)

[Claims] A tracer control method in a data processing device having a plurality of built-in tracers, in which when an event that requires stopping the tracing operation of one of the built-in tracers occurs, the tracing operation of this one tracer is stopped. A tracer control method characterized by controlling the tracing operations of other built-in tracers to be stopped in synchronization.