JPS63114150A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS63114150A
JPS63114150A JP25987286A JP25987286A JPS63114150A JP S63114150 A JPS63114150 A JP S63114150A JP 25987286 A JP25987286 A JP 25987286A JP 25987286 A JP25987286 A JP 25987286A JP S63114150 A JPS63114150 A JP S63114150A
Authority
JP
Japan
Prior art keywords
lead
circuit substrate
circuit
thickness
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25987286A
Other languages
Japanese (ja)
Inventor
Naoharu Senba
仙波　直治
Toshio Komiyama
込山　利男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25987286A priority Critical patent/JPS63114150A/en
Publication of JPS63114150A publication Critical patent/JPS63114150A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To eliminate the need for an island, to decrease the thickness of the plate thickness by the amount of the thickness of the island being eliminated and to change a circuit substrate into multilayers by directly joining a lead terminal for a lead frame made of a metal and the circuit substrate. CONSTITUTION:The inner end sections 2a of lead terminals 2 for a lead frame 1 made of a metal and a circuit substrate 4 are joined directly by using thermocompression bonding, welding, conductive paste, etc., active and passive circuit elements 5 are loaded onto the circuit substrate, connected by employing metallic small-gage wires 6, and shealed with a resin 7 through a transfer mold system. Separate lead terminal is detached from a lead connecting frame 3, and leads are formed. Accordingly, a hybrid integrated circuit can deal with the increase of plate thickness caused by the increase in the number of multilayers together with the miniaturization of products and the improvement of the function of the circuit substrate while allowing mechanical support, strength of which is augmented by the metallic small-gage wires.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、リードフレームにより混成集積回路基板に対
するリード付は組立を行ってなる混成集積回路に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit in which leads are attached to a hybrid integrated circuit board by assembly using a lead frame.

〔従来の技術〕[Conventional technology]

従来のこの種の混成集積回路は、第２図（ａｌの平面図
、同図（ｂｌの断面図に示すように、金属製のリードフ
レームのアイランド１１に絶縁性の回路基板４１＆：接
着剤により接層し、さらに、回路基板４の上にＩＣやト
ランジスタなどの能動回路素子およびコンデン？などの
受動回路素子５ｆｒ：搭載し、回路素子と回路基板の間
および回路基板４のボンディングバットとリードフレー
ムのリード１２との間を金属細線で接続し、樹脂７でも
って、回路素子を含むアイランド、接続の金属細線、お
よびリードの接続部？共に包覆し、七ｔからリードフレ
ームのリード連結枠１３からリード１２を個々に切り離
して完成品を得ていた。A conventional hybrid integrated circuit of this type is shown in FIG. In addition, active circuit elements such as ICs and transistors and passive circuit elements such as capacitors are mounted on the circuit board 4, and bonding butts and lead frames of the circuit board 4 and between the circuit elements and the circuit board are mounted. The lead 12 of the lead frame is connected with a thin metal wire, and the resin 7 is used to cover the island containing the circuit element, the thin metal wire of the connection, and the connection part of the lead. The finished product was obtained by cutting out the leads 12 individually.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の混成集積回路は、フラットな金属製のリ
ードフレームのアイランドに回路基板を搭載して構成し
ているため、回路基板の多層化及び高機能化を考えると
、板厚が厚くなり、製品の小型化に向かないという欠点
があった。The above-mentioned conventional hybrid integrated circuit has a circuit board mounted on an island of a flat metal lead frame, so as the circuit board becomes more multi-layered and highly functional, the board becomes thicker. The drawback was that it was not suitable for miniaturizing products.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の混成集積回路は金属製リードフレームのリード
端子と回路基板と全直接接合することにより、従来のリ
ードフレームのアイランドヲ不要にし、このアイランド
の板厚外だけ厚みの減少をもたらし、回路基板の多層化
が図詐る。The hybrid integrated circuit of the present invention completely directly connects the lead terminals of the metal lead frame and the circuit board, thereby eliminating the need for the island of the conventional lead frame, reducing the thickness only outside the board thickness of this island, and reducing the thickness of the circuit board. Multi-layering is a mistake.

〔実施例〕〔Example〕

次に、本発明について図面全参照して説明する。 Next, the present invention will be explained with reference to all the drawings.

第１図（ａ）は本発明の一実施例の平面図、同図（ｂ）
は同図（ａ）のＡ−Ａ断面図である。これらの図におい
て、金楓裏リードフレーム１のリード端子２の内端部２
ａと回路基板４を、熱圧着、ウェルド。FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
is a sectional view taken along line A-A in FIG. In these figures, the inner end 2 of the lead terminal 2 of the gold maple-backed lead frame 1
A and the circuit board 4 are thermocompressed and welded.

導１ペースト等を用いて直接接合し、この上に能動お工
び受動回路索子５ｔ−搭αし、金属細線６を用いて接伏
し、トランスファーモールド方式にて樹脂７の外装を流
子。しかる後、リード連結枠３から個々のリード端子に
切シ離し、リード成形を施して児底品とさｎる。They are directly bonded using a conductive paste or the like, and an active and passive circuit cord 5t is mounted on top of this, and is bonded using a thin metal wire 6, and the exterior of the resin 7 is molded using a transfer molding method. Thereafter, individual lead terminals are separated from the lead connection frame 3, and lead molding is performed to obtain a child's sole product.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は金属製リードフレームのリ
ード端子と回路基板と全熱圧着、ウェルド、専心ペース
ト等によシ直接接合する構造とした墨によ乃、回路基板
の多層化及び高機能化による板厚の増大と製品の小型化
指向に対応できると共に、従来の金属測線より−Ａ願向
上され几厳械的な支持をする効果がある。As explained above, the present invention has a structure in which lead terminals of a metal lead frame and a circuit board are directly joined by full heat compression bonding, welding, special paste, etc., multilayering of the circuit board, and high functionality. In addition to being able to cope with the increase in board thickness and the trend toward miniaturization of products due to metal cutting, it also has the effect of providing more precise and mechanical support than conventional metal survey lines.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は本発明の一実施例のリード連結枠切離し
前の平面図、同図（ｂ）は同図（ａ）のＡ−Ａｌ１面図
、第２図（ａ）は従来の汎成集績回路のリード連結枠切
離し前の平面図、同図（ｂｌは同図（ａｌのＡ−Ａ、ｉ
面図である。 １・・・・・・リードフレーム、１１・・・・・・アイ
ランド、２．１２・・・・・・リード馬子、３，１３・
川・・リード連結枠、４・・・・・・回路基板、５・・
・・・・回路素子、６・・・・・・金属測線、７・・・
・・・外装樹脂。 、・；、Ｊ 代理人　弁理士　　内　原　　　晋１．′・４・。 置〕 ゝ　、−ニFIG. 1(a) is a plan view of an embodiment of the present invention before the lead connecting frame is separated, FIG. 1(b) is a plane view of A-Al in FIG. 1(a), and FIG. A plan view of the general assembly circuit before the lead connection frame is separated, the same figure (bl is the same figure (al A-A, i
It is a front view. 1...Lead frame, 11...Island, 2.12...Lead Umako, 3,13.
River...Lead connection frame, 4...Circuit board, 5...
...Circuit element, 6...Metal measuring line, 7...
...Exterior resin. ,・;, J Agent Patent Attorney Susumu Uchihara 1. '・4・. Placeゝ , -d

Claims (1)

【特許請求の範囲】[Claims] 　リードフレームのリード端子と、絶縁性の回路基板と
を直接接合し、前記回路基板に能動および受動回路素子
を搭載し、樹脂封止してなる事を特徴とする混成集積回
路。A hybrid integrated circuit characterized in that lead terminals of a lead frame are directly bonded to an insulating circuit board, active and passive circuit elements are mounted on the circuit board, and the circuit board is sealed with resin.
JP25987286A 1986-10-30 1986-10-30 Hybrid integrated circuit Pending JPS63114150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25987286A JPS63114150A (en) 1986-10-30 1986-10-30 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25987286A JPS63114150A (en) 1986-10-30 1986-10-30 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS63114150A true JPS63114150A (en) 1988-05-19

Family

ID=17340123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25987286A Pending JPS63114150A (en) 1986-10-30 1986-10-30 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS63114150A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02192148A (en) * 1989-01-19 1990-07-27 Fujitsu Ltd Integrated circuit device
JPH02278757A (en) * 1989-04-19 1990-11-15 Nec Corp Hybrid integrated circuit
US5022960A (en) * 1989-05-01 1991-06-11 Ibiden Co., Ltd. Method of manufacturing circuit board for mounting electronic components
JPH03205857A (en) * 1990-01-06 1991-09-09 Fujitsu Ltd Resin-sealed electronic component
JPH04124864A (en) * 1990-09-14 1992-04-24 Matsushita Electric Works Ltd Lead frame
JPH04215461A (en) * 1990-12-14 1992-08-06 Matsushita Electric Works Ltd Package for semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5998545A (en) * 1982-11-26 1984-06-06 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5998545A (en) * 1982-11-26 1984-06-06 Hitachi Ltd Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02192148A (en) * 1989-01-19 1990-07-27 Fujitsu Ltd Integrated circuit device
JPH02278757A (en) * 1989-04-19 1990-11-15 Nec Corp Hybrid integrated circuit
US5022960A (en) * 1989-05-01 1991-06-11 Ibiden Co., Ltd. Method of manufacturing circuit board for mounting electronic components
US5088008A (en) * 1989-05-01 1992-02-11 Ibiden Co., Ltd. Circuit board for mounting electronic components
JPH03205857A (en) * 1990-01-06 1991-09-09 Fujitsu Ltd Resin-sealed electronic component
JPH04124864A (en) * 1990-09-14 1992-04-24 Matsushita Electric Works Ltd Lead frame
JPH04215461A (en) * 1990-12-14 1992-08-06 Matsushita Electric Works Ltd Package for semiconductor device

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