JPH07273275A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07273275A JPH07273275A JP6059023A JP5902394A JPH07273275A JP H07273275 A JPH07273275 A JP H07273275A JP 6059023 A JP6059023 A JP 6059023A JP 5902394 A JP5902394 A JP 5902394A JP H07273275 A JPH07273275 A JP H07273275A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor element
- tab
- semiconductor device
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数の半導体素子を有
する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of semiconductor elements.
【０００２】[0002]
【従来の技術】１つのパッケージ内に複数の半導体素子
（チップ）を搭載するハイブリットパッケージ型半導体
装置は、複数の半導体素子を基板上に横に並べたものと
して構成されている。各々の半導体素子と基板上のリー
ドとはワイヤを介して接続されている。つまり、図３に
示すように、基板１上に所定の間隔で平面的に半導体素
子２、２が配設されている。半導体素子２上のパッド
（端子）２ａ、２ａ、…はボンディングワイヤ３、３、
…を介して対応するリード１ａ、１ａ，…に接続されて
いる。2. Description of the Related Art A hybrid package type semiconductor device in which a plurality of semiconductor elements (chips) are mounted in one package is constructed by arranging a plurality of semiconductor elements laterally on a substrate. Each semiconductor element and the lead on the substrate are connected via a wire. That is, as shown in FIG. 3, the semiconductor elements 2 are arranged on the substrate 1 in a plane at a predetermined interval. Pads (terminals) 2a, 2a, ... On the semiconductor element 2 are bonding wires 3, 3,
Are connected to the corresponding leads 1a, 1a ,.
【０００３】[0003]
【発明が解決しようとする課題】従来のハイブリットパ
ッケージにおいては、上記のように、複数の半導体素子
を平面的に並べているため、パッケージが平面的に大き
くなり、実装密度が小さくなるという欠点があった。As described above, the conventional hybrid package has a drawback that the package becomes large in plane and the packaging density becomes small because a plurality of semiconductor elements are arranged in a plane as described above. It was
【０００４】本発明は、上記に鑑みてされたもので、そ
の目的は、複数の半導体素子を搭載するハイブリッドパ
ッケージ型の半導体装置における実装密度を向上させて
小型化を図ることにある。The present invention has been conceived in view of the above, and an object thereof is to improve the packaging density in a hybrid package type semiconductor device having a plurality of semiconductor elements mounted thereon and to achieve miniaturization.
【０００５】[0005]
【課題を解決するための手段】第１の発明は、第１、第
２の半導体素子を接着剤により互いに背中合わせに接合
し、前記第１の半導体素子の接続端子を基板上の第１の
リードに圧着し、前記第２の半導体体素子の接続端子と
前記基板上の第２のリードとをボンディングワイヤで接
続したものとして構成されている。According to a first aspect of the present invention, first and second semiconductor elements are joined back to back with an adhesive, and connection terminals of the first semiconductor element are connected to a first lead on a substrate. And is connected to the connection terminal of the second semiconductor element and the second lead on the substrate by a bonding wire.
【０００６】第２の発明は、第１の発明において、前記
接着剤としてエポキシ樹脂等の絶縁性の接着剤を用いた
ものとして構成されている。A second aspect of the present invention is the same as the first aspect of the present invention, in which an insulating adhesive such as an epoxy resin is used as the adhesive.
【０００７】第３の発明は、第１の発明において、前記
接着剤として半田又は銀等の導電性材料を有する導電性
の接着剤を用いたものとして構成されている。According to a third aspect of the present invention, in the first aspect, a conductive adhesive having a conductive material such as solder or silver is used as the adhesive.
【０００８】[0008]
【作用】２つの半導体素子は、それらが基板上に横に配
列されることなく、互いに積み重ねられた状態にして基
板上に載置される。これにより、２つの半導体素子は基
板上の小さな面積に取り付けられる。The two semiconductor elements are mounted on the substrate in a state where they are stacked on each other without being laterally arranged on the substrate. Thereby, the two semiconductor elements are mounted on a small area on the substrate.
【０００９】[0009]
【実施例】図１は、ＴＡＢテープ１１上に２つの半導体
素子（チップ）を背中合わせに接合した半導体素子組立
体１２を圧着し、その後、ワイヤボンディングした半導
体装置を示す。図２は図１の半導体装置の組み立ての概
念を示す説明図であるこの図２からわかるように、ＴＡ
Ｂテープ１１の１こま分は次のように構成されている。
即ち、ＴＡＢテープ１１における絶縁材製のＴＡＢ基板
１３はほぼ中央部分に半導体素子組立体１２を収納する
ための収納空間１３Ａが凹成されている。ＴＡＢ基板１
３の空間１３Ａにおける底面部分上に、ＴＡＢインナー
リード１４、１４、…が周辺から内側に向かって延びた
形に形成されている。これらのインナーリード１４、１
４、…上にはポリイミドテープ１５、１５、…が設けら
れ、これらのテープ１５、１５、…はＴＡＢ基板１３の
上側の上面に達している。これらのテープ１５の上端
は、ＴＡＢ基板１３上に設けられたリード１６、１６、
…の先端を絶縁状態に支持している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a semiconductor device in which two semiconductor elements (chips) are joined back to back on a TAB tape 11 and a semiconductor element assembly 12 is pressure-bonded and then wire-bonded. 2 is an explanatory view showing the concept of assembling the semiconductor device of FIG. 1. As can be seen from FIG.
One frame of the B tape 11 is constructed as follows.
That is, the TAB substrate 13 made of an insulating material in the TAB tape 11 has a recess 13A for accommodating the semiconductor element assembly 12 at a substantially central portion thereof. TAB board 1
The TAB inner leads 14, 14, ... Are formed on the bottom portion of the space 13A of No. 3 so as to extend inward from the periphery. These inner leads 14, 1
The polyimide tapes 15, 15, ... Are provided on the tops 4, ..., And these tapes 15, 15 ,. The upper ends of these tapes 15 have leads 16, 16 provided on the TAB substrate 13,
The tip of ... is supported in an insulated state.
【００１０】このように構成されたＴＡＢテープ１１の
１こま分の上に取り付けられる半導体素子組立体１２
は、第１の半導体素子２１と第２の半導体素子２２の裏
面同士を、接着剤２３によって接着したものである。こ
の接着剤２３としては、２つの半導体素子２１、２２の
半導体素子同士、つまり半導体基板同士の導通を取る必
要があるときは半田又は銀を主成分としたペーストを用
い、導通をとる必要のない絶縁時にはエポキシ樹脂等の
絶縁性の接着剤を用いる。これらの第１、第２の半導体
素子２１、２２には、その表面に、パッド２１ａ、２１
ａ、…；２２ａ、２２ａ、…がそれぞれ形成されてい
る。A semiconductor element assembly 12 mounted on one frame of the TAB tape 11 constructed as described above.
Is obtained by bonding the back surfaces of the first semiconductor element 21 and the second semiconductor element 22 to each other with an adhesive 23. As the adhesive 23, when the semiconductor elements of the two semiconductor elements 21, 22 need to be electrically connected to each other, that is, the semiconductor substrates, solder or paste containing silver as a main component is used, and it is not necessary to make the electrical connection. An insulating adhesive such as an epoxy resin is used for insulation. These first and second semiconductor elements 21 and 22 have pads 21a and 21 on their surfaces.
22a, 22a, ... are formed respectively.
【００１１】上記のように構成した半導体素子組立体１
２は、図２からわかるように、ＴＡＢテープ１１の１こ
ま分上に次のようにして取り付けられる。即ち、半導体
素子組立体１２をＴＡＢテープ１１の所期の位置に合わ
せる。この半導体素子組立体１２を、バンプ２４、２
４、…を介して、ＴＡＢテープ１１のインナーリード１
４、１４、…上に圧着する。この後、ワイヤボンディン
グを行い、上側の第１の半導体素子のパッド２１ａ、２
１ａ、…と、ＴＡＢテープ１１のリード１６、１６、…
とをボンディングワイヤ２５、２５、…で接続する。こ
れにより、図１の半導体装置が得られる。The semiconductor device assembly 1 constructed as described above.
As can be seen from FIG. 2, 2 is attached one frame above the TAB tape 11 as follows. That is, the semiconductor element assembly 12 is aligned with the intended position of the TAB tape 11. This semiconductor element assembly 12 is provided with bumps 24, 2
Inner lead 1 of TAB tape 11 via 4, ...
4, 14, ... Press on the top. After that, wire bonding is performed to form pads 21a, 2 of the upper first semiconductor element,
1a, ... and leads 16 of the TAB tape 11, 16 ,.
Are connected by bonding wires 25, 25, .... As a result, the semiconductor device of FIG. 1 is obtained.
【００１２】本発明の実施例によれば、２つの半導体素
子を、外部との接続端子のない面を互いに向かい合わせ
に貼り合わせることによって一体型のものとして、基板
に載着するようにしたので、半導体装置の実装密度を向
上させ、パッケージを小型化することができる。また、
ＴＡＢ基板に凹成した部分に半導体素子組立体を配設す
るようにしたので、上側の半導体素子がＴＡＢ基板から
浮かび上がる高さを従来のものと同じ高さにすることが
できる。よって、ワイヤボンディングについてみれば、
従来と同様に行うことができる。According to the embodiment of the present invention, the two semiconductor elements are mounted on the substrate as an integral type by adhering the two semiconductor elements so that the surfaces without connection terminals to the outside face each other. The packaging density of the semiconductor device can be improved and the package can be downsized. Also,
Since the semiconductor element assembly is arranged in the recessed portion of the TAB substrate, the height of the upper semiconductor element rising from the TAB substrate can be made the same as the conventional height. Therefore, regarding wire bonding,
It can be performed in the same manner as in the past.
【００１３】[0013]
【発明の効果】本発明よれば、２つの半導体素子を、互
いに背中合わせに接合した一体型のものとして基板に載
着するようにしたので、半導体装置の実装密度を向上さ
せ、パッケージ（製品）を小型化することができる。According to the present invention, the two semiconductor elements are mounted on the substrate as an integrated type which is joined back to back to each other, so that the packaging density of the semiconductor device is improved and the package (product) is manufactured. It can be miniaturized.
【図１】本発明の一実施例の側面図。FIG. 1 is a side view of an embodiment of the present invention.
【図２】図１の実施例の組み立て過程を説明するための
各部材の分離状態の側面図。FIG. 2 is a side view of each member in a separated state for explaining the assembling process of the embodiment of FIG.
【図３】従来例の側面図。FIG. 3 is a side view of a conventional example.
１ 基板 １ａ 基板リード ２、２１、２２ 半導体素子 ２ａ，２１ａ，２２ａ パッド ３、２５ ボンディングワイヤ １１ ＴＡＢテープ １２ 半導体素子組立体 １３ ＴＡＢ基板 １４ インナーリード １５ ポリイミドテープ １６ リード ２３ 接着剤 ２４ バンプ 1 Substrate 1a Substrate Lead 2, 21, 22 Semiconductor Element 2a, 21a, 22a Pad 3, 25 Bonding Wire 11 TAB Tape 12 Semiconductor Element Assembly 13 TAB Substrate 14 Inner Lead 15 Polyimide Tape 16 Lead 23 Adhesive 24 Bump
Claims (3)
いに背中合わせに接合し、前記第１の半導体素子の接続
端子を基板上の第１のリードに圧着し、前記第２の半導
体体素子の接続端子と前記基板上の第２のリードとをボ
ンディングワイヤで接続したことを特徴とする半導体装
置。1. A first semiconductor element and a second semiconductor element are bonded to each other back to back with an adhesive, and a connection terminal of the first semiconductor element is pressure-bonded to a first lead on a substrate to form the second semiconductor body. A semiconductor device characterized in that a connection terminal of an element and a second lead on the substrate are connected by a bonding wire.
の接着剤を用いたことを特徴とする請求項１記載の半導
体装置。2. The semiconductor device according to claim 1, wherein an insulating adhesive such as an epoxy resin is used as the adhesive.
料を有する導電性の接着剤を用いたことを特徴とする請
求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein a conductive adhesive having a conductive material such as solder or silver is used as the adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6059023A JPH07273275A (en) | 1994-03-29 | 1994-03-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6059023A JPH07273275A (en) | 1994-03-29 | 1994-03-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07273275A true JPH07273275A (en) | 1995-10-20 |
Family
ID=13101284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6059023A Pending JPH07273275A (en) | 1994-03-29 | 1994-03-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07273275A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000022676A1 (en) * | 1998-10-14 | 2000-04-20 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
| JP2001035994A (en) * | 1999-07-15 | 2001-02-09 | Toshiba Corp | Semiconductor integrated-circuit device and system substratte |
| JP2008522397A (en) * | 2004-11-26 | 2008-06-26 | イムベラ エレクトロニクス オサケユキチュア | Electronic module and manufacturing method thereof |
| JP2010129816A (en) * | 2008-11-28 | 2010-06-10 | Lintec Corp | Semiconductor chip laminated body and adhesive agent composition for laminating semiconductor chip |
-
1994
- 1994-03-29 JP JP6059023A patent/JPH07273275A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000022676A1 (en) * | 1998-10-14 | 2000-04-20 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
| US6552437B1 (en) | 1998-10-14 | 2003-04-22 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
| US6750080B2 (en) | 1998-10-14 | 2004-06-15 | Renesas Technology Corp. | Semiconductor device and process for manufacturing the same |
| JP2001035994A (en) * | 1999-07-15 | 2001-02-09 | Toshiba Corp | Semiconductor integrated-circuit device and system substratte |
| JP2008522397A (en) * | 2004-11-26 | 2008-06-26 | イムベラ エレクトロニクス オサケユキチュア | Electronic module and manufacturing method thereof |
| JP2010129816A (en) * | 2008-11-28 | 2010-06-10 | Lintec Corp | Semiconductor chip laminated body and adhesive agent composition for laminating semiconductor chip |
| KR101105470B1 (en) * | 2008-11-28 | 2012-01-13 | 린텍 가부시키가이샤 | Semiconductor chip laminate and adhesive composition for semiconductor chip lamination |
| US8716401B2 (en) | 2008-11-28 | 2014-05-06 | Lintec Corporation | Semiconductor chip laminate and adhesive composition for semiconductor chip lamination |
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