JPH04215461A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH04215461A JPH04215461A JP40210490A JP40210490A JPH04215461A JP H04215461 A JPH04215461 A JP H04215461A JP 40210490 A JP40210490 A JP 40210490A JP 40210490 A JP40210490 A JP 40210490A JP H04215461 A JPH04215461 A JP H04215461A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- semiconductor package
- resin
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 20
- 239000008393 encapsulating agent Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 238000000465 moulding Methods 0.000 abstract 3
- 239000000565 sealant Substances 0.000 description 16
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体チップが搭載さ
れたプリント配線板の一部又は全部が樹脂封止された半
導体パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package in which part or all of a printed wiring board on which a semiconductor chip is mounted is sealed with resin.
【０００２】0002
【従来の技術】従来より、プリント配線板などに搭載さ
れた半導体チップを保護するためにエポキシ樹脂とかシ
リコン樹脂により封止された半導体パッケージが提供さ
れていいる。2. Description of the Related Art Conventionally, semiconductor packages sealed with epoxy resin or silicone resin have been provided to protect semiconductor chips mounted on printed wiring boards or the like.
【０００３】0003
【発明が解決しようとする課題】例えばＱＦＰ９の場合
は、第８図及び第９図に示すように封止部分内には半導
体チップ１、アイランド１０及びリードフレーム６の一
部が位置しているだけであり、薄いものであって、半導
体パッケージＡ′の厚さ全体にしめる割合が小さく、又
、金型５の上型５ｂと下型５ａの分離部分に位置するの
もアイランド１０のみであり、しかもパッケージ面積に
占めるリードフレーム６の面積も小さく（通常５０％以
下）できることから、金型５内に樹脂封止剤３を均一に
流入させることができる。[Problems to be Solved by the Invention] For example, in the case of a QFP 9, as shown in FIGS. 8 and 9, the semiconductor chip 1, the island 10, and part of the lead frame 6 are located within the sealing part. The island 10 is the only one that is thin and occupies a small proportion of the total thickness of the semiconductor package A', and the island 10 is the only one that is located at the part where the upper mold 5b and the lower mold 5a of the mold 5 are separated. Moreover, since the area occupied by the lead frame 6 in the package area can be reduced (usually 50% or less), the resin sealant 3 can be uniformly flowed into the mold 5.
【０００４】しかしながら、プリント配線板２から形成
される半導体パッケージＡ″にあっては、封止する部分
の形状により封止剤３の流れが部分的に乱れボイド等の
欠陥が発生する。即ち、第１０図に示すようにプリント
配線板２が金型５の上型５ａと下型５ｂの分離部分に位
置しており、従って、ａ＞ｂとなり、このため、ランナ
ー８から注入され流路Ｆａを流れる樹脂封止剤３は流路
Ｆｂに流れ込み図中１１で示す箇所にボイドを発生して
しまうものである。従って、特にプリント配線板２全体
を封止する場合は金型５内でのプリント配線板２の位置
、形状等を配慮して充填しなければならないという問題
があった。However, in the semiconductor package A'' formed from the printed wiring board 2, the flow of the sealant 3 is partially disturbed due to the shape of the part to be sealed, resulting in defects such as voids. As shown in FIG. 10, the printed wiring board 2 is located at the separation part between the upper mold 5a and the lower mold 5b of the mold 5. Therefore, a>b, and therefore, the printed wiring board 2 is injected from the runner 8 into the flow path Fa. The resin sealant 3 flowing through the flow path Fb flows into the flow path Fb and causes voids at the location indicated by 11 in the figure.Therefore, especially when sealing the entire printed wiring board 2, There was a problem in that the position, shape, etc. of the printed wiring board 2 had to be taken into consideration when filling.
【０００５】本発明は上記問題を解決するためになされ
たものであり、その目的とするところは封止剤の充填性
が向上し、信頼性の高い半導体パッケージを提供するこ
とにある。The present invention has been made to solve the above problems, and its purpose is to provide a highly reliable semiconductor package in which the fillability of the sealant is improved.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体パッケー
ジは、半導体チップ１が搭載されたプリント配線板２の
一部又は全部が樹脂封止剤３により封止された半導体パ
ッケージであって、プリント配線板２上の封止される箇
所に凸部４を設けて成るものであり、この構成により上
記課題が解決されたものである。[Means for Solving the Problems] The semiconductor package of the present invention is a semiconductor package in which a part or all of a printed wiring board 2 on which a semiconductor chip 1 is mounted is sealed with a resin sealant 3. A convex portion 4 is provided at a portion of the wiring board 2 that is to be sealed, and this structure solves the above problem.
【０００７】[0007]
【作用】プリント配線板２上の封止される箇所に凸部４
を設けているので、金型５内での樹脂封止剤３の流れる
スペースが均一化され、封止の際に生ずるボイド等の欠
陥の発生を防止でき、信頼性を高めることができるもの
である。[Function] Convex portions 4 are formed on the printed wiring board 2 at the locations to be sealed.
Since this is provided, the space in which the resin sealant 3 flows within the mold 5 is made uniform, and defects such as voids that occur during sealing can be prevented from occurring, and reliability can be improved. be.
【０００８】[0008]
【実施例】プリント配線板２上には半導体チップ１が搭
載されており、４方向にリードフレーム６が引き出され
ている。プリント配線板２の中央部には半導体チップ１
が搭載されており、ボンディングワイヤ７によりリード
フレーム６に接続されている。第１図乃至第２図に示す
実施例にあっては、凸部４として半導体チップ１を囲む
ように突脈４ａが形成されている。このプリント配線板
２は第３図に示すように金型５内に配置され、下型５ｂ
のランナー８からエポキシ樹脂やシリコン樹脂のような
樹脂封止剤が注入され封止される。この場合、突脈４ａ
が形成されているので、プリント配線板２が金型５の上
型５ａと下型５ｂの分離部分に位置しており、従って、
ａ＞ｂとなっているが、突脈４ａにより流路Ｆａを流れ
る樹脂封止剤３と流路Ｆｂを流れる樹脂封止剤３の量は
略等しくなり、下型５ａ部分にボイド等の欠陥が発生す
ることがなく信頼性の高い半導体パッケージＡとなるも
のである。Embodiment A semiconductor chip 1 is mounted on a printed wiring board 2, and lead frames 6 are drawn out in four directions. A semiconductor chip 1 is placed in the center of the printed wiring board 2.
is mounted and connected to the lead frame 6 by bonding wires 7. In the embodiment shown in FIGS. 1 and 2, a protrusion 4a is formed as the convex portion 4 so as to surround the semiconductor chip 1. As shown in FIG. This printed wiring board 2 is placed in a mold 5 as shown in FIG.
A resin sealant such as epoxy resin or silicone resin is injected from the runner 8 and sealed. In this case, the ridge 4a
is formed, the printed wiring board 2 is located at the separated part of the upper mold 5a and lower mold 5b of the mold 5, and therefore,
Although a>b, the amount of the resin sealant 3 flowing in the flow path Fa and the resin sealant 3 flowing in the flow path Fb are approximately equal due to the protrusion 4a, and defects such as voids may occur in the lower mold 5a portion. This provides a highly reliable semiconductor package A that does not cause any of the following.
【０００９】第４図に示す実施例にあっては、凸部４は
円柱体４ｂであり、プリント配線板２の４隅に設けられ
ている。この場合、凸部４の形状及び設置の位置はプリ
ント配線板２の形状等により変更される。尚、第５図に
示すように凸部４の断面が方形状であり、プリント配線
板２とのなす角度が９０°以下であれば、矢印で示すよ
うに、この部分で樹脂封止剤３に乱流を生じるおそれが
あるが、第６図に示すように凸部４の断面形状を台形と
して凸部４とプリント配線板２のなす角度が９０°以上
であれば、第７図に示すように樹脂封止剤３がスムーズ
に流れてより一層樹脂封止剤３の流れを均一化させるこ
とができる。In the embodiment shown in FIG. 4, the protrusions 4 are cylindrical bodies 4b, and are provided at the four corners of the printed wiring board 2. As shown in FIG. In this case, the shape and installation position of the convex portion 4 are changed depending on the shape of the printed wiring board 2, etc. Note that, as shown in FIG. 5, if the cross section of the convex part 4 is rectangular and the angle formed with the printed wiring board 2 is 90 degrees or less, the resin sealant 3 is applied at this part as shown by the arrow. However, if the cross-sectional shape of the convex part 4 is a trapezoid as shown in FIG. 6 and the angle formed between the convex part 4 and the printed wiring board 2 is 90 degrees or more, the turbulence as shown in FIG. In this way, the resin sealant 3 flows smoothly, and the flow of the resin sealant 3 can be made even more uniform.
【００１０】0010
【発明の効果】本発明は半導体チップが搭載されたプリ
ント配線板の一部又は全部が樹脂封止剤により封止され
た半導体パッケージであって、プリント配線板上の封止
される箇所に凸部を設けているので、封止に際してプリ
ント配線板が金型の上型と下型の分離部分に位置してい
ても、凸部により上型と下型の樹脂封止剤の流入量が略
等しくなり、従って、上型を流れていた樹脂封止剤が下
型に流れ込んでボイドを発生させることなどないもので
ある。Effects of the Invention The present invention is a semiconductor package in which a part or all of a printed wiring board on which a semiconductor chip is mounted is sealed with a resin encapsulant. Even if the printed wiring board is located in the separation area between the upper and lower molds during sealing, the convex parts prevent the amount of resin sealant from flowing into the upper and lower molds. Therefore, the resin sealant flowing in the upper mold will not flow into the lower mold and cause voids.
【図１】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】本発明の一実施例におけるプリント配線板を示
す斜視図である。FIG. 2 is a perspective view showing a printed wiring board in one embodiment of the present invention.
【図３】本発明の一実施例の製造を示す断面図である。FIG. 3 is a cross-sectional view showing the manufacture of an embodiment of the present invention.
【図４】本発明の他の実施例におけるプリント配線板を
示す斜視図である。FIG. 4 is a perspective view showing a printed wiring board in another embodiment of the present invention.
【図５】本発明の実施例のおける樹脂封止剤の流れを示
す断面図である。FIG. 5 is a sectional view showing the flow of a resin sealant in an example of the present invention.
【図６】本発明の更に他の実施例におけるプリント配線
板を示す断面図である。FIG. 6 is a sectional view showing a printed wiring board in still another embodiment of the present invention.
【図７】本発明の更に他の実施例におけるプリント配線
板の作用を示す断面図である。FIG. 7 is a sectional view showing the function of a printed wiring board in still another embodiment of the present invention.
【図８】ＱＦＰにて形成された従来例を示す断面図であ
る。FIG. 8 is a cross-sectional view showing a conventional example formed of QFP.
【図９】従来例におけるＱＦＰを示す平面図である。FIG. 9 is a plan view showing a QFP in a conventional example.
【図１０】プリント配線板にて形成された従来例を示す
断面図である。FIG. 10 is a sectional view showing a conventional example formed of a printed wiring board.
Ａ 半導体パッケージ １ 半導体チップ ２ プリント配線板 ３ 樹脂封止剤 ４ 凸部 A Semiconductor package 1 Semiconductor chip 2 Printed wiring board 3 Resin sealant 4 Convex part
Claims (4)
の一部又は全部が樹脂封止剤により封止された半導体パ
ッケージであって、プリント配線板上の封止される箇所
に凸部を設けて成ること特徴とする半導体パッケージ。Claim 1: A semiconductor package in which part or all of a printed wiring board on which a semiconductor chip is mounted is sealed with a resin encapsulant, wherein a convex portion is provided at a portion of the printed wiring board to be sealed. A semiconductor package characterized by:
を囲む環状の突脈であることを特徴とする請求項１記載
の半導体パッケージ。2. The semiconductor package according to claim 1, wherein the convex portion is an annular protuberance surrounding a portion to be sealed on the printed wiring board.
に１個又は分離した複数個形成されて成ることを特徴と
する請求項１記載の半導体パッケージ。3. The semiconductor package according to claim 1, wherein one or a plurality of separate protrusions are formed at a portion of the printed wiring board to be sealed.
９０°以上であることを特徴とする請求項１、２又は３
記載の半導体パッケージ。4. Claim 1, 2 or 3, characterized in that the angle between the side of the convex portion and the printed wiring board is 90° or more.
Semiconductor package as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2402104A JP2723195B2 (en) | 1990-12-14 | 1990-12-14 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2402104A JP2723195B2 (en) | 1990-12-14 | 1990-12-14 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04215461A true JPH04215461A (en) | 1992-08-06 |
| JP2723195B2 JP2723195B2 (en) | 1998-03-09 |
Family
ID=18511917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2402104A Expired - Lifetime JP2723195B2 (en) | 1990-12-14 | 1990-12-14 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2723195B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596227A (en) * | 1994-09-01 | 1997-01-21 | Yamaha Corporation | Ball grid array type semiconductor device |
| WO2003094221A1 (en) * | 2002-04-04 | 2003-11-13 | Infineon Technologies Ag | Encapsulation of an integrated circuit |
| JP2010056355A (en) * | 2008-08-29 | 2010-03-11 | Hitachi Ltd | Transfer mold type electronic control device |
| CN111276448A (en) * | 2018-12-03 | 2020-06-12 | 三菱电机株式会社 | Semiconductor device and power conversion device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59141288A (en) * | 1983-01-31 | 1984-08-13 | 日本電気株式会社 | Hybrid integrated circuit device |
| JPS63114150A (en) * | 1986-10-30 | 1988-05-19 | Nec Corp | Hybrid integrated circuit |
| JPS63274152A (en) * | 1987-05-06 | 1988-11-11 | Nec Yamagata Ltd | Manufacture of semiconductor device |
| JPH01187846A (en) * | 1988-01-22 | 1989-07-27 | Hitachi Ltd | Semiconductor device |
| JPH0463463A (en) * | 1990-07-03 | 1992-02-28 | Hitachi Ltd | Resin sealed type semiconductor device |
-
1990
- 1990-12-14 JP JP2402104A patent/JP2723195B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59141288A (en) * | 1983-01-31 | 1984-08-13 | 日本電気株式会社 | Hybrid integrated circuit device |
| JPS63114150A (en) * | 1986-10-30 | 1988-05-19 | Nec Corp | Hybrid integrated circuit |
| JPS63274152A (en) * | 1987-05-06 | 1988-11-11 | Nec Yamagata Ltd | Manufacture of semiconductor device |
| JPH01187846A (en) * | 1988-01-22 | 1989-07-27 | Hitachi Ltd | Semiconductor device |
| JPH0463463A (en) * | 1990-07-03 | 1992-02-28 | Hitachi Ltd | Resin sealed type semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596227A (en) * | 1994-09-01 | 1997-01-21 | Yamaha Corporation | Ball grid array type semiconductor device |
| WO2003094221A1 (en) * | 2002-04-04 | 2003-11-13 | Infineon Technologies Ag | Encapsulation of an integrated circuit |
| JP2010056355A (en) * | 2008-08-29 | 2010-03-11 | Hitachi Ltd | Transfer mold type electronic control device |
| CN111276448A (en) * | 2018-12-03 | 2020-06-12 | 三菱电机株式会社 | Semiconductor device and power conversion device |
| US11450594B2 (en) | 2018-12-03 | 2022-09-20 | Mitsubishi Electric Corporation | Semiconductor device and power converter |
| DE102019218322B4 (en) | 2018-12-03 | 2022-11-03 | Mitsubishi Electric Corporation | semiconductor device and power converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2723195B2 (en) | 1998-03-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19950822 |