CA1272306A - Support assembly for integrated circuits - Google Patents

Support assembly for integrated circuits

Info

Publication number
CA1272306A
CA1272306A CA000555855A CA555855A CA1272306A CA 1272306 A CA1272306 A CA 1272306A CA 000555855 A CA000555855 A CA 000555855A CA 555855 A CA555855 A CA 555855A CA 1272306 A CA1272306 A CA 1272306A
Authority
CA
Canada
Prior art keywords
tape
assembly
frame
lead fingers
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA000555855A
Other languages
French (fr)
Inventor
Jon Long
Vahak Karekin Sahakian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of CA1272306A publication Critical patent/CA1272306A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

SUPPORT ASSEMBLY FOR INTEGRATED CIRCUITS
V. K. Sahakian Jon Long ABSTRACT
A composite support assembly for an integrated circuit chip includes a rigid lead frame that is attached to a relatively thin flexible tape-like structure. The tape-like structure is etched with inner lead fingers and outer lead fingers to allow a short pitch, high density arrangement of the lead fingers, thereby enabling bond wires that connect an IC chip to the support assembly to be shortened. As a result, a significant increase in the number of leads is realized, using a standard size IC package.

Description

~2~3~i 1 SUPPORT ASS~MBLY FOR INTEGRATED CIRCUITS
2 V. K~ Sahakian
3 Jon Long ACKGROUND OF THE INVENTION
6 Field of the Invention 7 This invention relates to an integrated circuit package 8 and in particular to a support assembly for integrated g circuit chips.
1~
11 Description of the Prior Art 1~ Integrated circuits (IC) generally comprise a number of 13 gates or flip-flops that are packaged in a single IC
14 container. The IC package provides input and output pins, pads, or leads which are connected to plated strips on 16 circuit boards or other means to form a complete circuit of 17 which the IC is a part. The IC chips are packaged by die 1~ attachment to paddles of lead frames. The lead frames are 19 either stamped or etched according to the quantity to be made. In the event that a large quantity is to be produced, 21 then stamping techniques are employed. On the other hand, 22 if only a small quantity of frames are needed, then they may 2 be made by slower photolithography and etching techniques.

24 The etching techniques allow finer tolerances than the stamping method. After die attachment, the bond pads of the 26 device are connected to the leads of the lead f rame by means ~7 of a fine metallic wire. Upon completion of the chip to 2B frame interconnection, the chip and interconnections are 2g encompassed by the IC package.
33 One problem that is encountered with stamped frames is 31 the limitation of the space between the leads and components 3 of the IC assembly imposed by the thickness of the metallic frame. The acceptable space between leads is approximately l.S times the thickness of the metal, which generally is a copper sheet of about .008 inches thick, for example.

Therefore, the spacing between leads that is required is at least .012 inches. If 25 leads, by way of example, are to 37 be provided, then a total spacin~ of .300 inches i5 ^~
p~

~2~3~

l needed. This spacing creates too large a distance between 2 the IC device, which is located centrally on the frame, and 3 the leads at the periphery of the frame. Therefore a lower
4 yield in production is obtained due to excessive length of the interconnecting wires. Also, the extra length required 6 does not allow for a compact assembly with dimensions that 7 are required by IC technology. The problem is compounded when the number of leads is increased thus necessitating a g significant increase in space of the IC and the frame leads.
1~ On the other hand, if a relatively thin tape-like ~1 support is used, such as an .001 inch thick metallic sheet, ~2 the spacing re~uirement is substantially reduced so that the 13 leads can be located close to the IC device. However, such ~4 thin metal tapes of this type are too flexible and are not rigid enough for assembly.

SUMMARY OF TEIE INVENTION

18 An object of this invention is to provide an improved 19 support assembly (lead frame) for integrated circuit chips.
Another object of the invention is to provide a com-21 posite IC support which provides a needed rigidi~y, and 22 realixes proper alignment of the IC device and conductive leads.
Another object is to provide a support assembly for an IC package that achieves high density of the conductive bond 26 locations of the IC device and a high pin count.
27 According to this invention, an IC package includes a composite support assembly formed with a rigid lead frame and a thin flexible tape-like structure. The tape-like structure is configured, preferably by etching, with inner bonding fingers, and with outer lead fingers that connect to the inner lead ingers. The lead fingers on the tape-like structure are disposed in a short pitch, high density pattern that can be formed as a result of the very thin structure of the flexible tape material. The lead frame is formed with leads that connect to the outer lead fingers of 36 the tape-like structure and external circuitry. The 37 composite support assembly allows the wire lengths ~723~
l connecting the IC chip to be shortened. As a result, the 2 support assembly can be made with a greater number of leads 3 and a higher pin count employing a standard size frame.
~ Fine line definition of the high density lead fingers is realized with resultant improved accuracy and proper 6 alignment of the tape-like structure on the lead frame.

BRIEF DESCRIPTION OF THÆ DRAWINGS
g The invention will be described in greater detail with reference to the drawings in which:
1} Fig. l is a top plan Yiew of a support assembly for an 12 IC chip, made in accordance with this invention;
13 Fig. 2 is an enlarged sectional view of a portion of 1~ the assembly of Fig. l including the IC chip and package;
l~ Fig. 3 is a side sectisnal ~iew of a support assembly 16 for an IC chip incorporating the flexible tape-like struc-17 ture and rigid lead frame assembly of this invention with 1~ the IC chip and package; and 19 Figs. 4A-4H illustrate the process steps of assembling the composite IC assembly.
21 Similar numerals refer to similar elements throughout 22 the drawings.

With reference to Fig. l, a composite support assembly 26 (lead frame) for an IC chip includes a flexible tape-like structure 14 that is joined to a rigid lead frame 12. The tape-like structure, which is preferably made of a thin copper sheet of about .001 inches in thickness and a dielectric film of about .003 inches in thickness, is configured by well known photolithography and etching processes. The lead frame is preferably made as an integral piece that has been mass produced by stamping. The lead frame is formed from a rigid copper plate, about .008 inches in thickness.
As illustrated in Figs~ 2 and 3, the thin tape-like 3~ structure 14 is configured with inner lead fingers 1~ that 37 are electrically connected by bond wires 18 to bond pads 20 C~P/M- 4 2 3 1 formed on an exposed surface of the IC chip 10. The 2 ~pposing surface of the IC chip is attached to tape-like 3 s~ructure 14 through a die attach pad 22. Th~ tape-like ~ structure 14 is formed with outer lead fingers 24 that extend from the inner lead fingers 16 to make contact with 6 coupling lead bonds 26~ thereby providing a continuous 7 conductive path from the i~tegrated circuit to external 8 package leads 28. The assembly including the structure 14 g and frame 12 are housed in a package or module 32. As a result of the constricted geometry and the necessity for 11 closely spaced patterned elements, including the lead 12 fingers, ~anufacture of an IC package 32 with a relatively 13 large number of lead fingers would be extremely difficult 14 when employing conventional IC packaged designs. The use of a thin tape-like structure to enable the shaping of the 16 closely spaced lead fingers with fine definition, in 17 combination with the lead frame 12 to provide rigidity, 18 overcomes the difficulties encountered in the prior art.
19 Etching o a thin structure to obtain a desired pattern affords finer tolerances and better line delineation, which 21 allows a short pitch, high density arran~ement of the etched 2~ elements, including the conductive lead fingers.
23 During production, the flexible tape-like structure 12 24 and the rigid lead frame 14 are positioned in a bonder apparatus comprising a stripper 34, a thermode 36 and a 26 punch 38 (Figs. 4Ap 4B~. The outer lead fingers 24 of the 27 tape-like structure are aligned with respective coupling 28 lead bonds 26. The punch separates a tape unit 12A from the tape strip, and the tape unit is moved into contact with the frame 14 (Fig. 4C). The tape unit is welded t~ the frame by the application of heat fro~ the thermode, i.e. thermo-compression bonding or eutectic bonding. The thermode and the punch are then returned to the home position, and the assembly of the lead frame with the tape unit is advanced, enabling repetition of the assembly process (Fig. 4E).
~~ An IC device 10 is then mounted on the composite frame and tape unit assembly 40 (Fig. 4F), and the IC device is 37 wire bonded to the composite rame ~Fig. 4G). Finally, the 3~

~2~

1 assembly of the bonded devise and the frame 14 is encap~
2 sulated to form an IC package 32 (Fig. 4E~.
3 The composite IC support assembly allows a high pin 4 count with accurate definition of the connecting lead
5 fingers. By virtue of the design of the assembly disclosed herein, production yield is significantly increased and 7 manufacturing costs are reduced. Since the outer and inner lead fingers can be brought closer to the IC chip, the bond g wires between the chip and the inner lead fingers are shortened. AS a result, a relatively high number of leads 11 can be incorporated in an IC package design. In successful 12 implementations, packages having 68 leads and 132 leads were 13 made employing a standard package mold. The support 14 assembly design vir~ually eliminates losses of IC assemblies and production resulting from high temperature processing by 16 mechanical orces, such as experienced in previous approaches to manufacture IC packages. It will be apparent 18 to one skilled in the art that it is not necessary to employ 19 the materials and thicknesses of the frame and tape-like structure given as examples herein. It is understood that 21 various modifications may be made without departing rom the 22 spirit and scope of the instant invention.

2~
~9

Claims (6)

What is claimed is:
1. A composite package assembly for supporting an integrated circuit chip comprising:
a relatively thin flexible tape-like structure having inner lead fingers, and having outer lead fingers electrically connected to said inner lead fingers;
a die attach pad seated in said structure;
a rigid lead frame joined to said structure and having internal leads aligned to and connected to said outer lead fingers; and package leads electrically connected to said internal leads for connection to external circuitry.
2. A composite assembly as in Claim 1, including a chip on said die attach pad with metallic wires connecting the IC chip to the inner lead fingers.
3. A composite assembly as in Claim 1, including a package encompassing said assembly.
4. A composite assembly as in Claim 1 wherein said tape-like structure has a metal thickness of about .001 inch and a dielectric film thickness of about .003 inches and said frame has a thickness of about .008 inches.
5. A composite assembly as in Claim 1 wherein said tape-like structure is configured by etching and said frame is configured by stamping.
6. A method of assembling a composite integrated circuit package comprising the steps of:
bonding a tape-like structure to a rigid frame;
attaching an integrated circuit chip device to the bonded assembly of said tape-like structure and frame;

bonding conductive wires to conductive elements of said integrated circuit device; and encapsulating said assembly of said tape-like structure and frame, so that said conductive wires are accessible to external circuitry.
CA000555855A 1987-01-28 1988-01-05 Support assembly for integrated circuits Expired - Lifetime CA1272306A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US008,208 1987-01-28
US07/008,208 US4800419A (en) 1987-01-28 1987-01-28 Support assembly for integrated circuits

Publications (1)

Publication Number Publication Date
CA1272306A true CA1272306A (en) 1990-07-31

Family

ID=21730351

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000555855A Expired - Lifetime CA1272306A (en) 1987-01-28 1988-01-05 Support assembly for integrated circuits

Country Status (6)

Country Link
US (1) US4800419A (en)
EP (1) EP0349549A4 (en)
JP (1) JPH02502323A (en)
KR (1) KR920008253B1 (en)
CA (1) CA1272306A (en)
WO (1) WO1988005962A1 (en)

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US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
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Also Published As

Publication number Publication date
KR920008253B1 (en) 1992-09-25
EP0349549A1 (en) 1990-01-10
EP0349549A4 (en) 1990-09-05
US4800419A (en) 1989-01-24
KR890700924A (en) 1989-04-28
JPH02502323A (en) 1990-07-26
WO1988005962A1 (en) 1988-08-11

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