JPS63112337U - - Google Patents
Info
- Publication number
- JPS63112337U JPS63112337U JP316487U JP316487U JPS63112337U JP S63112337 U JPS63112337 U JP S63112337U JP 316487 U JP316487 U JP 316487U JP 316487 U JP316487 U JP 316487U JP S63112337 U JPS63112337 U JP S63112337U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- etching rate
- insulating
- thickness
- upper layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Drying Of Semiconductors (AREA)
Description
第１図は本考案に係る半導体装置の一実施例を
示すもので、絶縁層に形成されたコンタクトホー
ルの形状を示す要部拡大断面図、第２図は絶縁層
の一例を示す要部拡大断面図、第３図は常圧ＣＶ
Ｄ装置の概略図である。第４図乃至第９図は従来
のコンタクトホールの形状を示す要部拡大断面図
である。
１…半導体基板、１２…下層（ＳｉＯ２膜）、
１３…上層（ＰＳＧ膜）、１４…絶縁層。
FIG. 1 shows an embodiment of a semiconductor device according to the present invention, and FIG. 2 is an enlarged cross-sectional view of a main part showing the shape of a contact hole formed in an insulating layer, and FIG. 2 shows an enlarged main part of an example of an insulating layer. Cross-sectional view, Figure 3 is normal pressure CV
It is a schematic diagram of D apparatus. 4 to 9 are enlarged sectional views of main parts showing the shape of a conventional contact hole. 1... Semiconductor substrate, 12... Lower layer (SiO 2 film),
13... Upper layer (PSG film), 14... Insulating layer.
Claims (1)
形成し、前記下層上にエツチレートが速い上層を
ＣＶＤ法により積層して２層構造の絶縁層を形成
したものに於て、 上記上層の層厚を絶縁層の層厚の１／３以下１
／２以上としたことを特徴とする半導体装置。[Claims for Utility Model Registration] A two-layer insulating layer is formed by forming a lower layer with a slow etching rate on the surface of a semiconductor substrate, and laminating an upper layer with a fast etching rate on the lower layer by CVD method, The layer thickness of the above upper layer is 1/3 or less of the layer thickness of the insulating layer1
A semiconductor device characterized in that: /2 or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP316487U JPS63112337U (en) | 1987-01-12 | 1987-01-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP316487U JPS63112337U (en) | 1987-01-12 | 1987-01-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63112337U true JPS63112337U (en) | 1988-07-19 |
Family
ID=30782670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP316487U Pending JPS63112337U (en) | 1987-01-12 | 1987-01-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63112337U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09251996A (en) * | 1995-06-20 | 1997-09-22 | Semiconductor Energy Lab Co Ltd | Manufacturing method for semiconductor device |
-
1987
- 1987-01-12 JP JP316487U patent/JPS63112337U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09251996A (en) * | 1995-06-20 | 1997-09-22 | Semiconductor Energy Lab Co Ltd | Manufacturing method for semiconductor device |
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