JPS6310567U - - Google Patents
Info
- Publication number
- JPS6310567U JPS6310567U JP10505186U JP10505186U JPS6310567U JP S6310567 U JPS6310567 U JP S6310567U JP 10505186 U JP10505186 U JP 10505186U JP 10505186 U JP10505186 U JP 10505186U JP S6310567 U JPS6310567 U JP S6310567U
- Authority
- JP
- Japan
- Prior art keywords
- frame
- leads
- plan
- view
- tie bar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000000465 moulding Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
第１図は本考案の第１の実施例の平面図、第２
図は第１の実施例の樹脂成形後の平面図、第３図
は本考案の第２の実施例の平面図、第４図は従来
のリードフレームの平面図、第５図は従来のリー
ドフレームの樹脂成形後の平面図である。
１……放熱板、２……外部リード、３……外部
リード固定用タイバー、４……枠部、５……半導
体素子、６……金属ワイヤー、７……成形樹脂、
８……樹脂成形時のエアベント部、９，９′……
巾広部。
Figure 1 is a plan view of the first embodiment of the present invention;
The figure is a plan view of the first embodiment after resin molding, FIG. 3 is a plan view of the second embodiment of the present invention, FIG. 4 is a plan view of a conventional lead frame, and FIG. 5 is a plan view of a conventional lead frame. FIG. 3 is a plan view of the frame after resin molding. DESCRIPTION OF SYMBOLS 1... Heat sink, 2... External lead, 3... Tie bar for fixing external lead, 4... Frame, 5... Semiconductor element, 6... Metal wire, 7... Molding resin,
8...Air vent part during resin molding, 9,9'...
Wide part.
Claims (1)
、枠部から延長したリード間を固定するタイバー
の前記リードとは接しない部分に巾広部を設けた
事を特徴とするリードフレーム。 1. A lead frame for use in semiconductor devices, characterized in that a tie bar that fixes between leads extending from a frame has a wide portion in a portion that does not come into contact with the leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986105051U JPH0521887Y2 (en) | 1986-07-08 | 1986-07-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986105051U JPH0521887Y2 (en) | 1986-07-08 | 1986-07-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6310567U true JPS6310567U (en) | 1988-01-23 |
| JPH0521887Y2 JPH0521887Y2 (en) | 1993-06-04 |
Family
ID=30979113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986105051U Expired - Lifetime JPH0521887Y2 (en) | 1986-07-08 | 1986-07-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0521887Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669852A (en) * | 1979-11-09 | 1981-06-11 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
-
1986
- 1986-07-08 JP JP1986105051U patent/JPH0521887Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669852A (en) * | 1979-11-09 | 1981-06-11 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0521887Y2 (en) | 1993-06-04 |