JPS63102271A - Vertical field effect transistor - Google Patents

Abstract

PURPOSE:To be able to supply a current having a value faithfully and effectively in response to the value of a control voltage to a load by forming other semiconductor layer so formed as to bury a gate electrode layer except cavities to the electrode layer on a semiconductor layer. CONSTITUTION:A semiconductor layer 16 formed by burying an electrode layer 14 on a semiconductor layer 13 is formed except a cavities 31 to the layer 14. The layer 16 is formed scarcely in contact with the layer 14. The layer 16 is so formed scarcely with a crystal defect at the layer 14. Thus, a control voltage is applied between the layers 14 and 17 thereby to obtain a depletion layer formed extensively between the adjacent layers 14 of the layer 13 to be effectively extended so that the extensions scarcely have an irregularity. Accordingly, a current having a value faithfully and effectively in response to the value of a control voltage can be supplied to a load.

Description

[Detailed description of the invention] Industrial applications The present invention relates to vertical field effect transistors.

2. Description of the Related Art Conventionally, a vertical field effect transistor having the configuration described below with reference to FIG. 3 has been proposed.

That is, it has a semiconductor substrate 1 having, for example, an n-type and made of, for example, GaAs, and a semiconductor layer 2 having the same conductivity type and made of the same semiconductor as the semiconductor substrate 1 is formed on the semiconductor substrate 1. There is.

Therefore, at the interface position between the semiconductor substrate 1 and the semiconductor layer 2,
n which is of the opposite conductivity type to the semiconductor substrate 1 and the semiconductor layer-2.
A plurality of gate electrode layers 3 made of a type of semiconductor layer are formed with required spacing and slightly extending toward the semiconductor substrate 1 and semiconductor layer 2 sides, respectively.

Further, on the surface of the semiconductor substrate 1 opposite to the semiconductor layer 2 side, a source electrode layer (or drain electrode layer) 4 made of metal is provided.
is ohmically applied, and a drain electrode layer (or source electrode layer) 5 is ohmically applied on the surface of the semiconductor layer 2 opposite to the semiconductor substrate 1 side.

Further, a vertical field effect transistor having the following structure (described below with reference to FIG. 4) has also been proposed.

That is, a semiconductor substrate 11 having, for example, an n-type and made of, for example, GaAs is provided, and a semiconductor substrate 11 having the same conductivity type as the semiconductor substrate 11 and having the same conductivity type as the semiconductor substrate 11 is placed on the semiconductor substrate 11.
Through the semiconductor layer 12 made of the same semiconductor as that of the semiconductor layer 12, there is formed a semiconductor layer 13 having the same conductivity type as the semiconductor layer 12, but having a lower impurity 'fji degree, and made of the same semiconductor as the semiconductor layer 12.

On the semiconductor layer 13, a plurality of gate electrode layers 14 made of metal are formed at required intervals to form Schottky junctions 15.

Further, on the semiconductor layer 13, a semiconductor □16 having the same conductivity type as the semiconductor layer 13 and made of the same semiconductor as the semiconductor layer 13 is provided.
is formed so as to bury the plurality of gate electrode layers 14 and form a Schottky junction 15' with the plurality of gate electrode layers 14.

Further, a source electrode layer (or drain electrode layer 17) is formed on the surface of the semiconductor substrate 11 opposite to the semiconductor layer 12 side.
is attached to Ohmic.

Further, a semiconductor layer 1 having the same conductivity type as the semiconductor layer 16 but having a higher impurity concentration than the semiconductor layer 16 is provided.
8, the train electrode layer (or source electrode 4\i [
)19 is attached to Ohmic.

In the case of the vertical field effect transistor shown in Figure 3, the voltage PI is
A plurality of gate electrode layers 3 and electrode layers 4 or 5 are connected between iNs 4 and 5 through a load with a required power source connected between them.
When no control voltage is applied between
flows between them, thus supplying current to the load. In addition, in such a state, if a ha-control voltage is applied between the gate electrode layer 3 and the electrode layer 4 or 5 with a polarity such that the semiconductor layer 3 side is negative, the semiconductor substrate 1 to the semiconductor layer 2 A depletion layer, which spreads between the adjacent gate electrode layers 3 of the semiconductor substrate 1 to the semiconductor layer 2 from the PN junction between the gate electrode layer 3 and the gate electrode layer 3, has a spread depending on the value of the control voltage. Therefore, a current having a value corresponding to the value of the control voltage flows between adjacent gate electrode layers 3 of the semiconductor substrate 1 and the semiconductor layer 2.

Therefore, a current having a value corresponding to the value of the limiting 'm'Fi pressure can be supplied to the load.

However, in the case of the conventional vertical field effect transistor shown in FIG. 3, since the gate electrode layer 3 is formed of a semiconductor layer, the resistivity of the gate electrode layer 3 is 10 to 10.
It has a relatively large value such as 1-Ω·cIIl, and therefore the gate resistance as a vertical field effect transistor has a large value.

For this reason, in the case of the conventional vertical field effect transistor shown in FIG. 3, only when the control 2D voltage lead changes at a relatively slow rate does the load have a current that has a value that faithfully corresponds to the value of the control voltage. It had the disadvantage of not being able to supply

In addition, in the case of the conventional vertical field effect transistor shown in FIG. 4, as in the case of the conventional vertical field effect transistor described above in FIG. If no control voltage is applied between the plurality of gate electrode layers 14 and one or more electrode layers 17 in the connected state, the current flows between the semiconductor layers 13 to 1.
The current flows internally through 14 adjacent gate electrode layers of 6, and therefore supplies current to the load. In addition, if a control voltage is applied between the gate electrode layer 14 and the electrode layer 17 or one of the gate electrode layers 14 in such a state, a Schottky junction between each of the semiconductor layers 13 and 16 and the gate electrode layer 14 is formed. 15 and 15', the depletion layer extending between the adjacent gate electrode layers 14 of the semiconductor layers 13 to 16 is formed with a spread corresponding to the value of the control voltage. A current having a value corresponding to the current flows between adjacent gate electrode layers 14 of semiconductor layers 13 to 16. Therefore, as in the case of the conventional vertical field effect transistor 1 to transistor described above with reference to FIG. 3, a current having a value corresponding to the value of the control 2I voltage can be supplied to the load.

However, in the case of the conventional vertical field effect transistor shown in FIG. 4, the gate electrode layer 14 is made of a metal layer, so that the resistivity of the gate electrode layer 14 is lower than that of the vertical field effect transistor shown in FIG. It has a much smaller value than that in the case of the gate electrode layer 3 made of a semiconductor layer.

Therefore, the gate resistance of the vertical field effect transistor has a much smaller value than that of the vertical field effect transistor described above in FIG.

Therefore, in the case of the conventional vertical field effect transistor shown in FIG. 4, the value of the control voltage is a value that faithfully corresponds to the value of the control voltage in the case of the conventional vertical field effect transistor described above in FIG. Even if the control voltage value changes at a rate sufficiently faster than the maximum rate of change at which the current value can be supplied to the load, the load is supplied with a current having a value that faithfully corresponds to the value of the control voltage. , can be supplied.

However, in the case of the conventional vertical field effect transistor shown in FIG. 4, the semiconductor layer 16 formed by embedding the gate electrode layer 14 on the semiconductor layer 13 is
4 to form a Schottky junction 15' with the gate electrode T! Since the semiconductor layer 16 is formed in contact with the side surface and the top surface of J14 over the entire area thereof,
It is formed to have many crystal defects 2o on the side surfaces of the gate electrode layer 14 and on the upper surface side of the gate electrode layer 14.

For this reason, the gate electrode FM layer 14 and the electrode layer 17 or 19
Control 1] By applying a voltage, the depletion layer formed by spreading between the adjacent gate electrode layers 14 of the semiconductor layers 13 to 16 is not effectively spread and iqed; There are variations in its spread.

Therefore, in the case of the conventional vertical field effect transistor shown in FIG. 4, it is not possible to supply to the load a current having a value that faithfully and effectively corresponds to the value of the control voltage.
It had the following drawback.

By means of solving the problem, the present invention seeks to propose a new vertical field effect transistor, which does not have the above-mentioned drawbacks.

The vertical field effect transistors according to the first invention and the second invention of the present application have a predetermined conductivity type formed on a semiconductor substrate, as in the case of the conventional vertical field effect transistor described above in FIG. A second semiconductor layer having the same conductivity type as the first semiconductor layer but having a lower impurity concentration than the first half-containing layer is formed with or without the first semiconductor layer having the structure. Moreover, on the second semiconductor layer, Y! made of metal scraps is formed. The number of gate electrode layers is
A third semiconductor layer is formed with a required spacing to form a Schottky junction, and further, a third semiconductor layer having the same conductivity type as the second semiconductor layer embeds the plurality of gate electrode layers. It has a configuration that is formed as follows.

However, in the vertical field effect transistor according to the first invention of the present application, in the vertical field effect transistor having such a structure, a plurality of grooves are formed in the second semiconductor layer from the third semiconductor layer side. , the plurality of gate electrode layers are formed on the second semiconductor layer in the plurality of grooves, and the third semiconductor layer is formed on the second semiconductor layer with a required spacing. It has a structure in which a hole is formed on the second semiconductor layer with a hole left between it and the gate electrode layer.

Further, the vertical field effect transistor 1 to transistor according to the second invention of the present application is a vertical field effect transistor having the above-described configuration similar to that of the conventional vertical field effect transistor described above in FIG. A fourth semiconductor layer having the same conductivity type as those of the second and third semiconductor layers is formed, and a plurality of grooves are formed in the fourth semiconductor layer from the third semiconductor layer side as required. The plurality of gate electrodes are formed on the second semiconductor layer to a depth that reaches the second semiconductor layer with an interval of . Further, the third semiconductor layer buries the fourth semiconductor layer on the second semiconductor layer and has a contact with the gate electrode. It has a structure in which a hole is left in between.

Effects and Effects According to the configuration of the vertical field effect transistor according to the first invention of the present application described above, the first electrode layer is attached to the semiconductor substrate or the first semiconductor layer, and the third semiconductor layer is provided with the first electrode layer. Another second electrode layer is applied with or without a semiconductor layer having the same conductivity type but a higher impurity concentration, and a load is applied between the first and second electrode layers. between the plurality of gate electrode layers and the first or second electrode layer, with a required power supply connected through the
When no control voltage is applied, current flows inward between adjacent gate electrode layers of the second semiconductor layer, thus supplying current to the load. In addition, in such a state, if a suppressing voltage is applied between the gate electrode layer and the first or second electrode layer, the Schottky junction between the second semiconductor layer and the gate electrode layer is removed. , the depletion layer spreading between adjacent gate electrode layers of the second semiconductor layer is formed with a spread depending on the value of the control voltage, so that the depletion layer spreads depending on the value of the control voltage. A current having the current flows between adjacent gate electrode layers of the second semiconductor layer. For this reason,
The load can be supplied with a current having a value depending on the value of the i, +1111 voltage.

Further, in the case of the vertical field effect transistor according to the first invention of the present application, the gate electrode layer is made of a metal layer as in the case of the conventional vertical field effect transistor described above in FIG. The gate resistance as an effect transistor is much smaller than that of the conventional vertical field effect transistor shown in FIG. 3, as in the case of the conventional vertical field effect transistor shown above in FIG. has value. Therefore, as in the case of the conventional vertical field effect transistor described above in FIG. Even if the value of the control voltage changes at a rate sufficiently higher than the maximum rate of change at which the load can be supplied with a current with a faithfully corresponding value,
A current having a value that closely depends on the value of the control voltage can be supplied.

However, in the case of the vertical field effect transistor according to the first invention of the present application, the third semiconductor layer formed on the second semiconductor layer so as to bury the gate electrode layer is between the third semiconductor layer and the gate electrode layer. Because it is formed with holes left in it,
The third semiconductor layer is formed with almost no contact with the gate electrode layer, and therefore the third semiconductor layer is
The gate electrode layer side is also formed to have almost no crystal defects.

Therefore, by applying a control voltage between the gate electrode lfi layer and the first or second electrode layer, a depletion layer that is formed by spreading between adjacent gate electrode layers of the second semiconductor layer has an effect. It can be obtained with a wide spread, and there is almost no variation in the spread.

Therefore, in the case of the vertical field effect transistor according to the first invention of the present application, a current having a value that faithfully and effectively corresponds to the value of the control voltage can be supplied to the load.

Further, according to the structure of the vertical field effect transistor 1 to transistor according to the second invention of the present application, as described above for the vertical field effect transistor according to the first invention of the present application, the semiconductor substrate or the first semiconductor A first electrode layer is applied to the third semiconductor layer, and another second electrode layer is applied to the third semiconductor layer, with or without intervening a semiconductor layer having the same conductivity type but a higher impurity concentration. between the plurality of gate electrode layers and the first or second electrode layer, and a required power source is connected between the first and second electrode layers through a load. , when the control tII voltage is not applied, current flows internally between the adjacent gate electrodes 8i of the second semiconductor layer, thus supplying current to the load. Further, as described above with respect to the vertical field effect transistor according to the first invention of the present application, from such a state, the gate electrode layer and the first or second
If a control voltage is applied to the gate between the second and fourth semiconductor layers and the gate electrode layer, the Schottky junction between each of the second and fourth semiconductor layers and the gate electrode layer Since the depletion layer that spreads between the gate electrode layers is formed with a spread that corresponds to the value of the control voltage, a current having a directivity that corresponds to the value of the control XI lightning voltage flows through the second to fourth semiconductors. It flows between adjacent gate electrode layers of the layer. Therefore, a current having a value corresponding to the value of the control voltage can be supplied to the load.

Further, in the case of the vertical field effect transistor according to the second invention of the present application, as described above for the vertical field effect transistor according to the first invention of the present application, the gate electrode layer is different from the conventional vertical field effect transistor described above in FIG. As in the case of the conventional vertical field effect transistor, the gate resistance as a vertical field effect transistor is as shown in FIG. 3 as in the case of the conventional vertical field effect transistor described above in FIG. Compared to the conventional vertical field effect transistor mentioned above,
It has a significantly smaller value. Therefore, as in the case of the conventional vertical field effect transistor described above in FIG. 4, the value of the control voltage is faithful to the value of the control voltage in the case of the conventional vertical field effect transistor described above in FIG. When a current having a value according to can be supplied to the load,
Even when the value of the control voltage changes at a rate sufficiently higher than the maximum rate of change, it is possible to supply the load with a current having a value that faithfully corresponds to the value of the control voltage.

However, in the case of the vertical field effect transistor according to the second invention of the present application, as in the case of the vertical field effect transistor according to the first invention of the present application, the gate electrode layer is buried on the second hand core layer. Since the third semiconductor layer formed on the gate electrode layer is formed with a hole left between it and the gate electrode layer, the third semiconductor layer is formed with almost no contact with the gate electrode layer. Therefore, the third semiconductor layer is formed with almost no crystal defects even on the gate electrode layer side.

Therefore, by applying a control voltage between the gate electrode layer and the first or second electrode layer, a depletion layer is formed by spreading between the adjacent gate electrode layers of the second to fourth semiconductor layers. , can be obtained by spreading effectively, and there is almost no variation in the spread.

Therefore, in the case of the vertical field effect transistor according to the second invention of the present application, as in the case of the vertical field effect transistor according to the first invention of the present application, it is possible to faithfully and effectively respond to the load and the value of the control voltage. A current having a value can be supplied.

Embodiment 1 Next, an embodiment of a vertical field effect transistor according to the first invention of the present invention will be described with reference to FIG.

In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

The vertical field effect transistor according to the '51st invention of the present application shown in FIG. 1 has the same structure as the conventional vertical field effect transistor described above in FIG. 4, except for the following points.

That is, the semiconductor layer 13 has a depth of, for example, 0.1 to 0.2 μm and a width of, for example, 25 μm from the semiconductor layer 16 side.
A plurality of relatively small grooves 30 are formed at required intervals by, for example, a dry etching process utilizing anisotropy, and a plurality of gate electrode MA layers 14 made of a metal plate each have a plurality of grooves. In the groove 30 of
It is formed.

In this case, each gate electrode layer 14 is formed using a sputtering method.
A Schottky junction 15a is formed by EB method or the like to have a concave cross section, and the outer bottom surface and outer surface of the gate electrode layer 14 are formed on the inner bottom surface and inner surface of the groove 30 corresponding to the gate electrode layer 14, respectively. and 15b, thus connecting the semiconductor layer 13 and the gate electrode 1 to 4.
The Schottky junction 15 between the two is formed as the Schottky junction 15a and 15b just described.

Further, the semiconductor layer 16 is formed on the semiconductor layer 13, leaving a hole 31 between it and the gate electrode 814 described above.

In this case, the semiconductor layer 16 contacts the gate electrode layer 14 only on the upper end surface of the portion extending in contact with the inner surface of the FS 30, and a Schottky junction 15' is formed there. Even if it is, it is not in contact with other parts of the gate electrode layer 14.

To form the semiconductor layer 16 in this way, the semiconductor layer 16
are formed by various epitaxial growth methods, similar to semiconductor layers 12.13 and 18, and in this case:
The fact that the growth rate in the direction along the main surface of the semiconductor layer 16 is higher than the growth rate in the thickness direction of the semiconductor layer 16 can be effectively utilized.

The above is the configuration of the embodiment of the vertical field effect transistor according to the first invention of the present application.

According to the vertical field effect transistor according to the first invention of the present application having such a configuration, it has the same configuration as the conventional vertical field effect transistor described above in FIG. 4, except for the matters mentioned above. Although the detailed explanation will be omitted, since the gate electrode layer 14 is made of a metal layer as in the case of the conventional vertical field effect transistor described above in FIG.
The gate resistance as a vertical field effect transistor has a small value, and therefore, as in the case of the conventional vertical field effect transistor described above in FIG. When a power supply is applied between the electrode layers 17 and 19, a current is applied between the electrode layers 17 and 19, and the value of the control voltage applied therebetween corresponds faithfully to the value of the control voltage in the case of the conventional vertical field effect transistor described above in FIG. The control voltage has a value that faithfully corresponds to the value of the control voltage to the load, even if it changes at a rate sufficiently higher than the maximum rate of change when the control voltage can be supplied to the load connected through it. Current can be supplied.

However, in the case of the vertical field effect transistor according to the first invention of the present application shown in FIG. Since the semiconductor layer 16 is formed with holes 31 left in the gate electrode layer 14, the semiconductor layer 16 is formed with almost no contact with the gate electrode layer 14 (the gate electrode layer 14
The contact area is sufficiently small compared to the total area of the gate electrode layer 14 when viewed from above. , ), the semiconductor layer 16 is formed so as to have almost no crystal defects 20, even on the gate electrode layer 14 side, as in the case of the conventional vertical field effect transistor described above with reference to FIG.

Therefore, by applying a control voltage between the gate electrode layer 14 and the electrode layer 17 or 19, the semiconductor layer 13
The depletion layer formed to spread between adjacent gate electrode layers 14 is effectively spread, and the spread has almost no discontinuity.

Therefore, in the case of the vertical field effect transistor according to the first invention of the present application shown in FIG. 1, a current having a value that faithfully and effectively corresponds to the value of the control voltage can be supplied to the load.

Embodiment 2 Next, an embodiment of a vertical field effect transistor according to the second invention of the present application will be described with reference to FIG.

In FIG. 2, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

The vertical field effect transistor according to the second invention of the present application shown in FIG. 2 has the same structure as the conventional vertical field effect transistor described above in FIG. 4, except for the following points.

That is, another new semiconductor FI 32 having the same conductivity type as those of the semiconductor layers 13 and 16 and having a thickness of, for example, 0.1 to 0.2 μm is formed, and in this semiconductor layer 32, From the semiconductor layer 16 side, the width is, for example, 0.
A plurality of relatively small grooves 33 of 25 μm are formed at a required interval by, for example, a dry etching process using anisotropy, and a plurality of gate electrode layers 14 made of a metal layer are respectively It is formed so that a Schottky junction 34 is also formed between the groove 33 and the semiconductor layer 32 .

In this case, the semiconductor layer 13 may be made of a semiconductor having a larger energy level in the conduction band (wider energy gap) than the semiconductor layer 32 . That is, the semiconductor layer 32
When it is made of GaAS like the other semiconductor layers 12, 16, etc., for example, A I Ga1-x As
(x≦O4×45) is acceptable. Further, each gate electrode layer 14 is formed by sputtering, as in the case of the vertical field effect transistor according to the present invention described above in FIG.
A semiconductor layer 13 is formed by an EB method or the like to have a concave cross section, and the outer bottom surface and outer surface of the gate electrode layer 14 face into the trench 33 corresponding to the gate electrode layer 14.
are formed in contact with the upper surface of the semiconductor layer 32 and the side surface of the semiconductor layer 32 so as to form Schottky junctions 15 and 34, respectively.

Further, the semiconductor layer 16 is formed on the semiconductor layer 13 , burying the above-described semiconductor layer 32 and leaving a hole 31 between it and the gate electrode layer 14 .

In this case, the semiconductor layer 16 contacts the gate electrode layer 14 only on the upper end surface of the portion extending in contact with the side surface of the semiconductor layer 32 facing the groove 33, and there, a Schottky junction is formed. 15', it does not contact other parts of the gate electrode layer 14.

To form the semiconductor layer 16 in this way, the semiconductor layer 16 is formed by forming the semiconductor layers 12, 13, 18 and 32 in the same manner as in the case of the vertical field effect transistor according to the first invention of the present application.
Similarly, it is formed by various epitaxial growth methods, and in this case, the growth rate in the direction along the main surface of the semiconductor layer 16 is higher than the growth rate in the direction along the thickness direction of the semiconductor layer 16. You just have to take advantage of that fact.

The above is the configuration of the embodiment of the vertical field effect transistor according to the second invention of the present application.

According to the vertical field effect transistor according to the second invention of the present application having such a configuration, it has the same configuration as the conventional vertical field effect transistor described above in FIG. 4, except for the matters mentioned above. Therefore, detailed explanation will be omitted, but if a control voltage is applied between the gate electrode layer 14 and the electrode layer 17 or 19, the voltage between each of the semiconductor layers 13 and 32 and the gate electrode layer 14 will be reduced. Schottky junction 15
and 34, a depletion layer is formed that spreads between the adjacent gate electrode 8i layers 14 of the semiconductor layers 13 to 32, and a current having a value corresponding to the value of the control voltage 21I can be supplied to the load. In this case, since the gate electrode i-layer 14 is made of a metal layer as in the case of the conventional vertical field effect transistor described above in FIG. 4, the gate resistance as a vertical field effect transistor has a small value. Therefore, as in the case of the conventional vertical field effect transistor described above in FIG. 4, the value of the control voltage applied between the gate electrode layer 14 and the electrode layer 17 or 19 is as shown in FIG. In the case of the above-mentioned conventional vertical field effect transistor, when a current having a value that faithfully corresponds to the value of the control voltage can be supplied to the load connected between the electrode layers 17 and 19 via the power supply. Even when the value of the control voltage changes at a rate sufficiently higher than the maximum rate of change, it is possible to supply the load with a current having a value that faithfully corresponds to the value of the control voltage.

However, in the case of the vertical field effect transistor according to the second invention of the present application shown in FIG. 2, the semiconductor layer 16 formed by embedding the electrode layer 14 on the semiconductor layer 13 is As in the case of a vertical field effect transistor, since the semiconductor layer 16 is formed with holes 31 left between the gate electrode layer 14 and the gate electrode layer 14, the semiconductor layer 16
The layer 14 is formed with almost no contact (
The gate electrode 14 is in contact with the upper end surface of the portion extending along the inner surface of the groove 33, and the contact area is the same as the gate electrode t! ! Since the semiconductor layer 16 is sufficiently small compared to the total area seen from above of the Jiliff 14), the semiconductor layer 16 also has a crystalline structure on the gate electrode layer 14 side as in the case of the conventional vertical field effect transistor described above in FIG. It is formed to have almost no defects 20.

Therefore, by applying a control voltage between the gate electrode layer 14 and the electrode layer 17 or 19, the semiconductor layer 13
The depletion layer formed between 32 to 32 adjacent gate electrode layers 14 is effectively depleted, and there is almost no variation in its spread.

Therefore, in the case of the vertical field effect transistor according to the second invention of the present application shown in FIG. 2, as in the case of the vertical field effect transistor according to the first invention of the present application described above in FIG. A current having a value that faithfully and effectively corresponds to the control voltage can be supplied.

Further, in the case of the vertical field effect transistor according to the second invention of the present application shown in FIG.
When the semiconductor layer 32 is made of a semiconductor having a large conduction band energy level (wide energy gap) compared to
Even if the value of the voltage changes at a rate faster than the maximum rate if the semiconductor layer 13 is not formed of a semiconductor having a larger conduction band energy level than the semiconductor layer 32, the control voltage is applied to the load. It is possible to supply a current having a value that closely corresponds to the value of .

In addition, in the above description, only one embodiment has been shown for each of the assembled field effect transistors according to the first invention of the present application and the second invention of the present application, and detailed description of the drawings will be omitted. And in the configuration described above in FIG. 2, the semiconductor layer 12 is omitted, and therefore the semiconductor substrate 1
Alternatively, the semiconductor substrate 1 may be a semi-insulating semiconductor substrate, and the electrode layer 17 may be omitted accordingly. It is also possible to form a window that exposes the semiconductor layer 12 to the outside, and to ohmically attach an electrode layer to the semiconductor layer 12 in place of the electrode layer 17 at a position facing the window. Furthermore, the semiconductor layer 1
8 is omitted, and therefore the electrode layer 19 is directly connected to the semiconductor layer 1.
It is also possible to adopt an ohmic structure as shown in FIG. 6, and various other modifications and changes may be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of a vertical field effect transistor according to the first invention of the present application. FIG. 2 is a cross-sectional view showing an embodiment of a vertical field effect transistor according to the second invention of the present application. FIGS. 3 and 4 are sectional views showing conventional vertical field effect transistors, respectively. 1.11... Semiconductor substrate 2.12.13.16.18... Semiconductor layer 14... Gate electrode layer 15.15a, 15b, 15'. ......Schottky junction 20...Crystal defect 30.33...Groove 31...Vacancy 32... ... Semiconductor layer 34 ... Schottky junction Applicant Nippon Telegraph and Telephone Corporation Figure 1

Claims (1)

[Claims] 1. On a semiconductor substrate, with or without a first semiconductor layer having a predetermined conductivity type, the first semiconductor layer having the same conductivity type as the first semiconductor layer, but having the same conductivity type as the first semiconductor layer. A second semiconductor layer having an impurity concentration lower than that of the semiconductor layer is formed, and a plurality of gate electrode layers made of metal layers are formed on the second semiconductor layer with required spacing to form a Schottky junction. and a third semiconductor layer having the same conductivity type as the second semiconductor layer is formed so as to bury the plurality of gate electrode layers. In the transistor, a plurality of grooves are formed in the second semiconductor layer from the third semiconductor layer side at a required interval, and the plurality of gate electrode layers are formed on the second semiconductor layer. ,
The third semiconductor layer is formed in the plurality of grooves, and the third semiconductor layer is formed on the second semiconductor layer with a hole left between it and the gate electrode layer. type field effect transistor. 2. On the semiconductor substrate, with or without a first semiconductor layer having a predetermined conductivity type, a semiconductor layer having the same conductivity type as the first semiconductor layer but lower than the first semiconductor layer. a second semiconductor layer having an impurity concentration is formed; a plurality of gate electrode layers made of metal layers are formed on the second semiconductor layer with required spacing to form a Schottky junction; A vertical field effect transistor having a configuration in which a third semiconductor layer having the same conductivity type as the second semiconductor layer is formed on the second semiconductor layer so as to bury the plurality of gate electrode layers. and a fourth semiconductor layer having the same conductivity type as those of the third semiconductor layer, and a plurality of grooves are formed in the fourth semiconductor layer at required intervals from the third semiconductor layer side. The plurality of gate electrodes are formed on the second semiconductor layer, within the plurality of grooves, and between the plurality of gate electrodes and the fourth semiconductor layer. The third semiconductor layer is formed so as to form a Schottky junction, and the third semiconductor layer buries the fourth semiconductor layer on the second semiconductor layer and leaves a hole between it and the gate electrode. A vertical field effect transistor characterized by being formed. 3. In the vertical field effect transistor according to claim 1 or 2, each of the plurality of gate electrode layers has a concave cross section, and an outer bottom surface and an outer surface of the gate electrode layer A vertical field effect transistor, wherein the vertical field effect transistor is in contact with an inner bottom surface and an inner surface of the groove corresponding to the trench so as to form a Schottky junction, respectively. 4. The vertical field effect transistor according to claim 2, wherein the second semiconductor layer is made of a semiconductor having a conduction band energy level larger than that of the fourth semiconductor layer. Vertical field effect transistor.